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Artykuły w czasopismach na temat "Digital Receiver Design"
Bakhru, Kesh. "Communications receiver design using digital processing". Digital Signal Processing 2, nr 1 (styczeń 1992): 2–13. http://dx.doi.org/10.1016/1051-2004(92)90018-t.
Pełny tekst źródłaLiu, Yu Peng, Chao Du i Dong Lin Liu. "Design and Implementation of Multi-Frequency Digital Receiver Based on FPGA". Applied Mechanics and Materials 643 (wrzesień 2014): 117–23. http://dx.doi.org/10.4028/www.scientific.net/amm.643.117.
Pełny tekst źródłaZhang, Lin, Yi Wen Liu i Yi Cao. "Design of Digital Receiver Based on FPGA". Applied Mechanics and Materials 419 (październik 2013): 528–32. http://dx.doi.org/10.4028/www.scientific.net/amm.419.528.
Pełny tekst źródłaRevathi, V., P. Parvati i G. Hemachandra. "Design and Simulation of Digital Beacon Receiver". i-manager’s Journal on Wireless Communication Networks 5, nr 4 (2017): 20. http://dx.doi.org/10.26634/jwcn.5.4.13555.
Pełny tekst źródłaShazly, Khadija, Mohamed E. .. i Sunil Kumar. "Design and FPGA Implementation of Digital Frequency Modulation Receiver". International Journal of Wireless and Ad Hoc Communication 4, nr 2 (2022): 107–66. http://dx.doi.org/10.54216/ijwac.040206.
Pełny tekst źródłaSakr, Ahmed, Aziza I. Hussein, Ghazal Fahmy i Mahmoud A. Abdelghany. "Design of PWM-Based Digital Receiver for 5G". Procedia Computer Science 182 (2021): 159–65. http://dx.doi.org/10.1016/j.procs.2021.02.021.
Pełny tekst źródłaKim, Seung-Geun, Chang-Ho Yun, Sea-Moon Kim i Yong-Kon Lim. "Baseband Receiver Design for Maritime VHF Digital Communications". Journal of Korea Information and Communications Society 36, nr 8B (31.08.2011): 1012–20. http://dx.doi.org/10.7840/kics.2011.36b.8.1012.
Pełny tekst źródłaLim, Eun-Jae, Hee-Geun Hwang i Young-Chul Rhee. "A Study on RF Receiver Design and Analysis of Digital Radar Receiver". Journal of Korean Institute of Electromagnetic Engineering and Science 25, nr 3 (31.03.2014): 282–88. http://dx.doi.org/10.5515/kjkiees.2014.25.3.282.
Pełny tekst źródłaPodstrigaev, Alexey S. "UWB digital receiver design methodology with sub-Nyquist sampling". T-Comm 15, nr 10 (2021): 11–17. http://dx.doi.org/10.36724/2072-8735-2021-15-10-11-17.
Pełny tekst źródłaZhang, Chengchang, i Lihong Zhang. "Intermediate Frequency Digital Receiver Based on Multi-FPGA System". Journal of Electrical and Computer Engineering 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/6123832.
Pełny tekst źródłaRozprawy doktorskie na temat "Digital Receiver Design"
Benson, Stephen Ray. "Modern Digital Chirp Receiver: Theory, Design and System Integration". Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1450737245.
Pełny tekst źródłaDe, Leon Phillip, Qingsong Wang, Steve Horan i Ray Lyman. "A DESIGN FOR SATELLITE GROUND STATION RECEIVER AUTOCONFIGURATION". International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/607484.
Pełny tekst źródłaIn this paper, we propose a receiver design for satellite ground station use which can demodulate a waveform without specific knowledge of the data rate, convolutional code rate, or line code used. Several assumptions, consistent with the Space Network operating environment, are made including only certain data rates, convolutional code rates and generator polynomials, and types of line encoders. Despite the assumptions, a wide class of digital signaling (covering most of what might be seen at a ground station receiver) is captured. The approach uses standard signal processing techniques to identify data rate and line encoder class and a look up table with coded sync words (a standard feature of telemetry data frame header) in order to identify the key parameters. As our research has shown, the leading bits of the received coded frame can be used to uniquely identify the parameters. With proper identification, a basic receiver autoconfiguration sequence (date rate, line decoder, convolutional decoder) may be constructed.
Lennen, G. R. "The application of digital techniques to Navstar GPS receiver design". Thesis, University of Leeds, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234682.
Pełny tekst źródłaGeorge, Kiranraj. "Design and Performance Evaluation of 1 Giga Hertz Wideband Digital Receiver". Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1183662240.
Pełny tekst źródłaBochuan, Zhang, Kou Yanhong, Zhang Qishan i Chang Qing. "DESIGN OF A HIGH DYNAMIC GPS RECEIVER". International Foundation for Telemetering, 2005. http://hdl.handle.net/10150/605033.
Pełny tekst źródłaHigh dynamic and multi-channel digital GPS receiver can handle the signals with high dynamic range, low S/N ratio and refresh data quickly. A hardware design of high dynamic GPS digital receiver is given. Based on analysis of the effect that high dynamic movement makes on the receiving signals, a scheme of fast-acquisition high dynamic GPS receiver is presented. Exact reckoning of the orbit parameters and the satellite clock parameters are integrated with appropriate algorithms. A DDLL is used to precisely estimate the C/A code delay, a CPAFC loop and a Costas loop to precisely estimate the carrier frequency and phase. The DDLL is assisted with carrier phase. The experimental results show that the receiver meets the design request.
Lentini, Dario, i Gustav Salenby. "Design and implementation of UPnP network functionality for a digital TV receiver". Thesis, Linköping University, Department of Computer and Information Science, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16462.
Pełny tekst źródłaMedia extenders or digital media receivers are network devices that are used to retrieve digital media files (such as music, pictures, or video) from a media server and play or show them on a TV or home theater system. A technology that is often associated with these devices is the Universal Plug and Play (UPnP) technology. This technology enables network devices to be used without requiring the user to do network configuration on it. This thesis demonstrates how a device that is normally used for receiving digital television broadcasts can be enhanced to support media extender functionality. The thesis describes the design and implementation of the technologies that are needed to accomplish this functionality. The main topics are centered around on how UPnP awareness and media rendering (decoding) are incorporated into the device.
Runyon, Ginger R. "Parallel processor architecture for a digital beacon receiver". Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41422.
Pełny tekst źródłaStröm, Marcus. "System Design of RF Receiver and Digital Implementation of Control Logic". Thesis, Linköping University, Department of Science and Technology, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1848.
Pełny tekst źródłaThis report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.
The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).
The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.
A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.
When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.
The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.
Wu, Jingxian. "Optimum receiver design and performance analysis for wireless communication". Diss., Columbia, Mo. : University of Missouri-Columbia, 2005. http://hdl.handle.net/10355/4177.
Pełny tekst źródłaThe entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (July 19, 2006) Vita. Includes bibliographical references.
Madishetty, Suresh. "Design of Multi-Beam Hybrid Digital Beamforming Receivers". University of Akron / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1545178805415923.
Pełny tekst źródłaKsiążki na temat "Digital Receiver Design"
McClaning, Kevin. Wireless receiver design for digital communications. Wyd. 2. Raleigh, NC: SciTech, 2012.
Znajdź pełny tekst źródłaJohnson, C. Richard. Software receiver design: Build your own digital communication system in five easy steps. Cambridge, UK: Cambridge University Press, 2011.
Znajdź pełny tekst źródłaMartelli, Chiara. Multi-standard low-power base-band digital receiver, enhanced for HSDPA. Konstanz: Hartung-Gorre, 2006.
Znajdź pełny tekst źródłaInc, ebrary, red. Special design topics in digital wideband receivers. Boston, Mass: Artech House, 2010.
Znajdź pełny tekst źródłaMengali, Umberto. Synchronization techniques for digital receivers. New York: Plenum Press, 1997.
Znajdź pełny tekst źródłaFerrate, Andres. Building web apps for Google TV. Sebastopol, CA: O'Reilly Media, 2011.
Znajdź pełny tekst źródłaKalivas, Grigorios. Digital radio system design. Chister, West Sussex, U.K: J. Wiley, 2009.
Znajdź pełny tekst źródłaAmos, S. W. Principles of transistor circuits: Introduction to the design of amplifiers, receivers, and digital circuits. Wyd. 9. Oxford: Newnes, 2000.
Znajdź pełny tekst źródłaAmos, S. W. Principles of transistor circuits: Introduction to the design of amplifiers, receivers, and digital circuits. Wyd. 8. Oxford: Butterworth-Heinemann, 1994.
Znajdź pełny tekst źródłaAmos, S. W. Principles of transistor circuits: Introduction to the design of amplifiers, receivers and digital circuits. Wyd. 7. London: Butterworths, 1990.
Znajdź pełny tekst źródłaCzęści książek na temat "Digital Receiver Design"
Dixon, Robert C. "Implementation with Digital Methods". W Radio Receiver Design, 299–320. Boca Raton: CRC Press, 2024. http://dx.doi.org/10.1201/9781003573500-11.
Pełny tekst źródłaLee, Edward A., i David G. Messerschmitt. "Signal and Receiver Design". W Digital Communication, 279–310. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4684-0004-5_7.
Pełny tekst źródłaFrerking, Marvin E. "Digital Receiver/Exciter Design". W Digital Signal Processing in Communication Systems, 305–91. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4757-4990-8_7.
Pełny tekst źródłaGrötker, Thorsten, Uwe Lambrette i Heinrich Meyr. "Efficient VHDL Code Generation for Digital Receiver Design". W Information Technology: Transmission, Processing and Storage, 423–34. London: Springer London, 1996. http://dx.doi.org/10.1007/978-1-4471-1013-2_33.
Pełny tekst źródłaBenkeser, Christian, i Qiuting Huang. "Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE". W VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 100–127. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28566-0_5.
Pełny tekst źródłaZervas, N. D., S. Theoharis, A. P. Kakaroudas, D. Soudris, G. Theodoridis i C. E. Goutis. "Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers". W Integrated Circuit Design, 47–55. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_6.
Pełny tekst źródłaHou, Qitong, Rui Wang, Erwu Liu i Dongliang Yan. "Digital Precoding Design for MIMO System with One-Bit ADC Receivers". W Lecture Notes in Electrical Engineering, 704–12. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-6264-4_83.
Pełny tekst źródłaZervas, Nikos D., Spyros Theoharis, Minas Perakis, Costas E. Goutis i Dimitrios Soudris. "Run-Time Power Management for Low and Medium Bit-Rate Digital Receivers". W Unified low-power design flow for data-dominated multi-media and telecom applications, 135–57. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3182-8_6.
Pełny tekst źródłaBagheri, Rahim, Ahmad Mirzaei, Saeed Chehrazi i Asad A. Abidi. "Software-Defined Radio Receiver Architecture and RF-Analog Front-End Circuits". W Digitally-Assisted Analog and RF CMOS Circuit Design for Software-Defined Radio, 85–112. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8514-9_4.
Pełny tekst źródłaBächler, Liane, i Hauke Behrendt. "Participation in Work of People with Disabilities by Means of Technical Assistance". W New Digital Work, 118–34. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-26490-0_7.
Pełny tekst źródłaStreszczenia konferencji na temat "Digital Receiver Design"
Sikora, Paul A. "An EMI Receiver Design Using Modern Digital Techniques". W 11th International Zurich Symposium and Technical Exhibition on Electromagnetic Compatibility, 453–58. IEEE, 1995. https://doi.org/10.23919/emc.1995.10784244.
Pełny tekst źródłaSheng, Xiaochun, Min Lu, Hongyu Fu i Yang Wei. "Design and Implementation of 32-Channel C-Band Digital Transmitter/Receiver Module". W 2024 IEEE 16th International Conference on Advanced Infocomm Technology (ICAIT), 49–53. IEEE, 2024. https://doi.org/10.1109/icait62580.2024.10808136.
Pełny tekst źródłaSong, Zequn, Shigeki Takeda, Takayuki Shimizu, Osamu Mineta i Motoki Oshima. "Model Base Design of MIMO Transmitter and Receiver Implementation on an FPGA Board". W 2024 2nd International Symposium on Information Technology and Digital Innovation (ISITDI), 270–73. IEEE, 2024. https://doi.org/10.1109/isitdi62380.2024.10796719.
Pełny tekst źródłaKumar, I. Vijay, i M. B. Srinivas. "Design of a digital CDMA receiver". W the 2003 conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/1119772.1119904.
Pełny tekst źródłaFitz, S. M. "Receiver architectures for GSM handsets". W IEE Colloquium on Design of Digital Cellular Handsets. IEE, 1998. http://dx.doi.org/10.1049/ic:19980231.
Pełny tekst źródłaFerrett, Terry, Matthew C. Valenti i Don Torrieri. "Receiver design for noncoherent digital network coding". W MILCOM 2010 - 2010 IEEE Military Communications Conference. IEEE, 2010. http://dx.doi.org/10.1109/milcom.2010.5680474.
Pełny tekst źródłaGao, Li-Peng, i Jian Liu. "Design of Dual-Channel AIS Digital Receiver". W 2012 Second International Conference on Instrumentation, Measurement, Computer, Communication and Control (IMCCC). IEEE, 2012. http://dx.doi.org/10.1109/imccc.2012.61.
Pełny tekst źródłaPeter Zepter. "Digital Receiver Design Using VHDL Generation From Data Flow Graphs". W 32nd Design Automation Conference. ACM, 1995. http://dx.doi.org/10.1109/dac.1995.250095.
Pełny tekst źródłaLiu, Yuan, Chenling Huang, Hao Min, Guohong Li i Yifeng Han. "Digital Correlation Demodulator Design for RFID Reader Receiver". W 2007 IEEE Wireless Communications and Networking Conference. IEEE, 2007. http://dx.doi.org/10.1109/wcnc.2007.313.
Pełny tekst źródłaHorii, Shiraishi, Shinjo, Suzuki i Takegahara. "Practical Design Of Receiver For Satellite Digital Broadcasting". W 1998 International Conference on Consumer Electronics. IEEE, 1998. http://dx.doi.org/10.1109/icce.1998.678256.
Pełny tekst źródłaRaporty organizacyjne na temat "Digital Receiver Design"
Dudley, Peter A. Design guidelines for SAR digital receiver/exciter boards. Office of Scientific and Technical Information (OSTI), sierpień 2009. http://dx.doi.org/10.2172/1145166.
Pełny tekst źródłaAhouansou, Wildfrid, Fadhel Medard Salifou-Bio i Arnaud Dangvenon. Academic success of students and educational trajectories: Characteristics and needs for a digital learning environment at the University of Abomey-Calavi. Mary Lou Fulton Teachers College, luty 2024. http://dx.doi.org/10.14507/mcf-eli.i15.
Pełny tekst źródłaBykova, Tatyana B., Mykola V. Ivashchenko, Darja A. Kassim i Vasyl I. Kovalchuk. Blended learning in the context of digitalization. [б. в.], czerwiec 2021. http://dx.doi.org/10.31812/123456789/4441.
Pełny tekst źródłaPetrunoff, Nick, Bess Jackson, Samuel Harley, Alexandra Schiavuzzi, Melissa McEnallay, Cathelijne van Kemenade, Myfanwy Maple, Sarah Wayland, Alice Knight i Eileen Goldberg. Non-clinical interventions and services for individuals with suicide distress or crisis: an Accelerated Evidence Snapshot. The Sax Institute, luty 2025. https://doi.org/10.57022/fknj4927.
Pełny tekst źródłaGroening, Edward, Mick Moore, Denis Mukama i Ronald Waiswa. Pathways Into the Tax Net: Better Ways to Register African Taxpayers. Institute of Development Studies, maj 2024. http://dx.doi.org/10.19088/ictd.2024.029.
Pełny tekst źródłade Brauw, Alan, Daniel Gilligan, Laura Leavens, Fekadu Moges, Shalini Roy i Mulugeta Tefera. Impact Evaluation of the SHARPE Programme in Ethiopia: Academic Report. Centre for Excellence and Development Impact and Learning (CEDIL), marzec 2023. http://dx.doi.org/10.51744/crpp6.
Pełny tekst źródłaThe Launch of the National Rollout of the Municipal Innovation Maturity Index (MIMI) (A tool to measure innovation in municipalities). Academy of Science of South Africa (ASSAf), 2021. http://dx.doi.org/10.17159/assaf.2021/0076.
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