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Rozprawy doktorskie na temat „Formal verification”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 25 lipca 2025

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1

Tristan, Jean-Baptiste. "Formal verification of translation validators." Phd thesis, Université Paris-Diderot - Paris VII, 2009. http://tel.archives-ouvertes.fr/tel-00437582.

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Comme tout logiciel, les compilateurs, et tout particulièrement les compilateurs optimisant, peuvent être défectueux. Il est donc possible qu'ils changent la sémantique du programme compilé, et par conséquent ses propriétés. Dans le cadre de développement de logiciels critiques, où des méthodes formelles sont utilisées pour s'assurer qu'un programme satisfait certaines propriétés, et cela avant qu'il soit compilé, cela pose un problème de fond. Une solution à ce problème est de vérifier le compilateur en s'assurant qu'il préserve la sémantique des programmes compilés. Dans cette thèse, nous év

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Trinh, Cong Quy. "Formal Verification of Skiplist Algorithms." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-160314.

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Dragomir, Ciprian. "Formal verification of P systems." Thesis, University of Sheffield, 2016. http://etheses.whiterose.ac.uk/15452/.

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Membrane systems, also known as P systems, constitute an innovative computational paradigm inspired by the structure and dynamics of the living cell. A P system consists of a hierarchical arrangement of compartments and a finite set of multiset rewriting and communication rules, which operate in a maximally parallel manner. The organic vision of concurrent dynamics captured by membrane systems stands in antithesis with conventional formal modelling methods which focus on algebraic descriptions of distributed systems. As a consequence, verifying such models in a mathematically rigorous way is o

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4

Hurd, J. "Formal verification of probabilistic algorithms." Thesis, University of Cambridge, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604823.

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We begin with an extensive foundational development of probability, creating a higher-order logic formalization of mathematical measure theory. This allows the definition of the probability space we use to model a random bit generator, which informally is a stream of coin-flips, or technically an infinite sequence of IID Bernoulli( 1/2 ) random variables. Probabilistic programs are modified using the state-transformer monad familiar from functional programming, where the random bit generator is passed around in the computation. Functions remove random bits from the generator to perform their c

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5

Botinčan, Matko. "Formal verification-driven parallelisation synthesis." Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/274136.

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Concurrency is often an optimisation, rather than intrinsic to the functional behaviour of a program, i.e., a concurrent program is often intended to achieve the same effect of a simpler sequential counterpart, just faster. Error-free concurrent programming remains a tricky problem, beyond the capabilities of most programmers. Consequently, an attractive alternative to manually developing a concurrent program is to automatically synthesise one. This dissertation presents two novel formal verification-based methods for safely transforming a sequential program into a concurrent one. The first me

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6

Jobredeaux, Romain J. "Formal verification of control software." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53841.

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In a context of heightened requirements for safety-critical embedded systems and ever-increasing costs of verification and validation, this research proposes to advance the state of formal analysis for control software. Formal methods are a field of computer science that uses mathematical techniques and formalisms to rigorously analyze the behavior of programs. This research develops a framework and tools to express and prove high level properties of control law implementations. One goal is to bridge the gap between control theory and computer science. An annotation language is extended with s

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7

Parikh, Ankur. "Abstraction Guided Semi-formal Verification." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/33596.

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Abstraction-guided simulation is a promising semi-formal framework for design validation in which an abstract model of the design is used to guide a logic simulator towards a target property. However, key issues still need to be addressed before this framework can truly deliver on it's promise. Concretizing, or finding a real trace from an abstract trace, remains a hard problem. Abstract traces are often spurious, for which no corresponding real trace exits. This is a direct consequence of the abstraction being an over-approximation of the real design. Further, the way in which the abstract mo

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8

Bubel, Richard. "Formal verification of recursive predicates." [S.l. : s.n.], 2007. http://digbib.ubka.uni-karlsruhe.de/volltexte/1000008366.

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9

Suresh, Amrita. "Formal Verification of Communicating Automata." Electronic Thesis or Diss., université Paris-Saclay, 2022. http://www.theses.fr/2022UPASG092.

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Les systèmes distribués concernent des processus qui s’exécutent indépendamment et communiquent de manière asynchrone. Bien qu’ils couvrent un large éventail de cas d’utilisation et soient donc omniprésents dans notre monde, il est particulièrement difficile de garantir leur exactitude. Dans cette thèse, nous modélisons de tels systèmes en utilisant une formulation mathématique et logique, et nousles vérifions algorithmiquement. En particulier, nous nous concentrons sur les automates FIFO (First In First Out), et plus précisément sur des systèmes à un ou plusieurs automates finis qui communiqu

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10

Wei, Jijie. "Formal verification of a digital PLL." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/50048.

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Common AMS circuit are composed from blocks that can be modeled accurately using linear differential inclusions to enable verification of important properties using reachability analysis. This dissertation presents a formal verification of Digital Phase Locked Loop (PLL) using reachability techniques. PLLs are ubiquitous in analog mixed signal (AMS) designs and are widely used in modern communication equipment, clock generation for CPUs in computers, clock-acquisition in high-speed links etc. The most important property of a PLL is convergence, which means starting from any possible initial

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11

Pike, Lee. "Formal verification of time-triggered systems." [Bloomington, Ind.] : Indiana University, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3215296.

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Thesis (Ph.D.)--Indiana University, Dept. of Computer Science, 2006.<br>Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2086. Adviser: Steven D. Johnson. "Title from dissertation home page (viewed June 20, 2007)."

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12

Brückner, Ingo. "Slicing integrated formal specifications for verification /." Oldenburg : Univ., Fak. II, Dep. für Informatik, 2008. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016564256&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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13

Arnaud, Mathilde. "Formal verification of secured routing protocols." Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2011. http://tel.archives-ouvertes.fr/tel-00675509.

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With the development of digital networks, such as Internet, communication protocols are omnipresent. Digital devices have to interact with each other in order to perform the numerous and complex tasks we have come to expect as commonplace, such as using a mobile phone, sending or receiving electronic mail, making purchases online and so on. In such applications, security is important. For instance, in the case of an online purchase, the right amount of money has to be paid without leaking the buyer personal information to outside parties. Communication protocols are the rules that govern these

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14

Compton, Michael James. "Formal verification of process algebra systems." Thesis, University of Cambridge, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612067.

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15

Myreen, Magnus Oskar. "Formal verification of machine-code programs." Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611450.

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16

Olthuis, Jorrit. "Verification of Formal Requirements through Tracing." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-289947.

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Software development in the railway application is governed by strict standards which aim to ensure safety. It is for example highly recommended to use formal methods when specifying requirements. Moreover, it is mandatory to have certain roles be fulfilled by different people. A common technique is developing software tests for the requirements. Making sure that software requirements are properly described, interpreted and implemented by different people is a major challenge. Tests fully depend on the tester to cover all scenarios. Having more methods that simplify requirement tracing and tha

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17

Limaye, Chinmay Avinash. "Formal Verification Techniques for Reversible Circuits." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/33406.

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As the number of transistors per unit chip area increases, the power dissipation of the chip becomes a bottleneck. New nano-technology materials have been proposed as viable alternatives to CMOS to tackle area and power issues. The power consumption can be minimized by the use of reversible logic instead of conventional combinational circuits. Theoretically, reversible circuits do not consume any power (or consume minimal power) when performing computations. This is achieved by avoiding information loss across the circuit. However, use of reversible circuits to implement digital logic requires

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18

Vimjam, Vishnu Chaithanya. "Strategies for SAT-Based Formal Verification." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/26078.

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Verification of digital hardware designs is becoming an increasingly complex task as the designs are incorporating more functionality, becoming complex and growing larger in size. Today, verification remains a bottleneck in meeting time-to-market requirements and consumes more than 70% of the overall design-costs. Traditionally, verification has been done using simulation-based approaches, where a set of appropriate test-stimuli is used by the designer. As the designs become more complex, however, simulation-based techniques often fail to capture corner-case errors. Furthermore, unless exhaust

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19

Lu, Tianxiang. "Formal verification of the Pastry protocol." Thesis, Université de Lorraine, 2013. http://www.theses.fr/2013LORR0179/document.

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Le protocole Pastry réalise une table de hachage distribué sur un réseau pair à pair organisé en un anneau virtuel de noeuds. Alors qu'il existe plusieurs implémentations de Pastry, il n'y a pas encore eu de travaux pour décrire formellement l'algorithme ou vérifier son bon fonctionnement. Intégrant des structures de données complexes et de la communication asynchrone entre des noeuds qui peuvent rejoindre ou quitter le réseau, ce protocole représente un intérêt certain pour la vérification formelle. La thèse se focalise sur le protocole Join de Pastry qui permet à un noeud de rejoindre le rés

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20

Lu, Tianxiang. "Formal verification of the Pastry protocol." Electronic Thesis or Diss., Université de Lorraine, 2013. http://www.theses.fr/2013LORR0179.

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Le protocole Pastry réalise une table de hachage distribué sur un réseau pair à pair organisé en un anneau virtuel de noeuds. Alors qu'il existe plusieurs implémentations de Pastry, il n'y a pas encore eu de travaux pour décrire formellement l'algorithme ou vérifier son bon fonctionnement. Intégrant des structures de données complexes et de la communication asynchrone entre des noeuds qui peuvent rejoindre ou quitter le réseau, ce protocole représente un intérêt certain pour la vérification formelle. La thèse se focalise sur le protocole Join de Pastry qui permet à un noeud de rejoindre le rés

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21

Powell, Daniel, and n/a. "Formal Methods For Verification Based Software Inspection." Griffith University. School of Computing and Information Technology, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030925.154706.

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Useful processes, that are independently repeatable, are utilised in all branches of science and traditional engineering disciplines but seldom in software engineering. This is particularly so with processes used for detection and correction of defects in software systems. Code inspection, as introduced by Michael Fagan at IBM in the mid 1970's is widely recognised as an effective technique for finding defects in software. Despite its reputation, code inspection, as it is currently practiced, is not a strictly repeatable process. This is due to the problems faced by inspectors when they attemp

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22

Pompeo, François. "A formal verification assistant for TROMLAB environment." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape7/PQDD_0003/MQ43667.pdf.

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23

Lu, Jianping. "On the formal verification of ATM switches." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0001/MQ43654.pdf.

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24

Zhang, Bairong. "Formal specification and verification of OSI protocols." Thesis, University of Bristol, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337284.

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25

Mancini, Loretta Ilaria. "Formal verification of privacy in pervasive systems." Thesis, University of Birmingham, 2015. http://etheses.bham.ac.uk//id/eprint/6105/.

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Pervasive systems enhance a user's everyday experience. However, the use of pervasive sensing and context aware devices can result very intrusive from a privacy perspective. A familiar pervasive device is a mobile phone. Mobile telephony equipment is daily carried everywhere. Avoiding linkability of subscribers by third parties, and protecting their privacy is one of the goals of mobile telecommunication protocols. We use experimental and formal methods to model and analyse the security properties of mobile telephony protocols. We expose novel threats to the user privacy, which make it possibl

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26

Smith, Mark Anthony Shawn 1968. "Formal verification of TCP and T/TCP." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/42779.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.<br>Includes bibliographical references (p. 421-424).<br>by Mark Anthony Shawn Smith.<br>Ph.D.

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Davidson, Timothy A. S. "Formal verification techniques using quantum process calculus." Thesis, University of Warwick, 2012. http://wrap.warwick.ac.uk/51368/.

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Quantum communication is a rapidly growing area of research and development. While the successful construction of a large-scale quantum computer may be some years away, there are already commercial implementations of secure communication using quantum cryptography. The application of formal methods to classical communication and cryptographic systems has been very successful, and is now widely used in industry by organisations such as Intel, Microsoft and NASA. There is reason to believe that similar benefits can be expected for the verification of quantum systems. In this thesis, we focus on

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28

Fang, Lei. "Exploring Constraint Satisfiability Techniques in Formal Verification." Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/27573.

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Due to the widespread demands for efficient Propositional Satisfiability (SAT) solvers and its derivatives in Electronic Design Automation applications, methods to boost the performance of the SAT solver are highly desired. This dissertation aims to enhance the performance of SAT and related SAT solving problems. A hybrid solution to boost SAT solver performance is proposed as an initial attack in this dissertation, via an integration of local and DPLL-based search approaches. Next, a different hybrid strategy is attempted that takes advantage of the conflicts in the SAT search, which plays a

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29

Sawada, Jun. "Formal verification of an advanced pipelined machine /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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30

Kühne, Ulrich. "Advanced automation in formal verification of processors." Aachen Shaker, 2009. http://d-nb.info/998313092/04.

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Miyazawa, Alvaro Heiji. "Formal verification of implementations of stateflow charts." Thesis, University of York, 2012. http://etheses.whiterose.ac.uk/2353/.

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Simulink diagrams are widely used in industry for specifying control systems, and a particular type of block used in them is a Stateflow chart. Often, the systems specified are safety-critical ones. Therefore, the issue of correctness of implementations of these systems is relevant. We are interested in the verification of implementations of Stateflow charts. In this thesis, we propose a formal model of Stateflow charts in the Circus notation. The proposed model makes a distinction between the general semantics of Stateflow charts and the specific aspects of each chart, and maintains the opera

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32

Powell, Daniel. "Formal Methods For Verification Based Software Inspection." Thesis, Griffith University, 2003. http://hdl.handle.net/10072/366466.

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Useful processes, that are independently repeatable, are utilised in all branches of science and traditional engineering disciplines but seldom in software engineering. This is particularly so with processes used for detection and correction of defects in software systems. Code inspection, as introduced by Michael Fagan at IBM in the mid 1970's is widely recognised as an effective technique for finding defects in software. Despite its reputation, code inspection, as it is currently practiced, is not a strictly repeatable process. This is due to the problems faced by inspectors when they attemp

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33

Livadas, Carolos. "Formal verification of safety-critical hybrid systems." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/42817.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.<br>Includes bibliographical references (p. 181-185).<br>This thesis investigates how the formal modeling and verification techniques of computer science can be used for the analysis of hybrid systems [7,14,22,37] - systems involving both discrete and continuous behavior. The motivation behind such research lies in the inherent similarity of the hierarchical and decentralized control strategies of hybrid systems and the communication and operation protocols used for distributed sy

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34

Griggio, Alberto. "An Effective SMT Engine for Formal Verification." Doctoral thesis, Università degli studi di Trento, 2009. https://hdl.handle.net/11572/368265.

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Formal methods are becoming increasingly important for debugging and verifying hardware and software systems, whose current complexity makes the traditional approaches based on testing increasingly-less adequate. One of the most promising research directions in formal verification is based on the exploitation of Satisfiability Modulo Theories (SMT) solvers. In this thesis, we present MathSAT, a modern, efficient SMT solver that provides several important functionalities, and can be used as a workhorse engine in formal verification. We develop novel algorithms for two functionalities which are

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Griggio, Alberto. "An Effective SMT Engine for Formal Verification." Doctoral thesis, University of Trento, 2009. http://eprints-phd.biblio.unitn.it/145/1/thesis.pdf.

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Formal methods are becoming increasingly important for debugging and verifying hardware and software systems, whose current complexity makes the traditional approaches based on testing increasingly-less adequate. One of the most promising research directions in formal verification is based on the exploitation of Satisfiability Modulo Theories (SMT) solvers. In this thesis, we present MathSAT, a modern, efficient SMT solver that provides several important functionalities, and can be used as a workhorse engine in formal verification. We develop novel algorithms for two functionalities whi

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36

Griggio, Alberto. "An Effective SMT Engine for Formal Verification." Doctoral thesis, Università degli studi di Trento, 2009. https://hdl.handle.net/11572/368765.

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Formal methods are becoming increasingly important for debugging and verifying hardware and software systems, whose current complexity makes the traditional approaches based on testing increasingly-less adequate. One of the most promising research directions in formal verification is based on the exploitation of Satisfiability Modulo Theories (SMT) solvers. In this thesis, we present MathSAT, a modern, efficient SMT solver that provides several important functionalities, and can be used as a workhorse engine in formal verification. We develop novel algorithms for two functionalities which are

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Griggio, Alberto. "An Effective SMT Engine for Formal Verification." Doctoral thesis, University of Trento, 2009. http://eprints-phd.biblio.unitn.it/166/2/thesis.pdf.

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Formal methods are becoming increasingly important for debugging and verifying hardware and software systems, whose current complexity makes the traditional approaches based on testing increasingly-less adequate. One of the most promising research directions in formal verification is based on the exploitation of Satisfiability Modulo Theories (SMT) solvers. In this thesis, we present MathSAT, a modern, efficient SMT solver that provides several important functionalities, and can be used as a workhorse engine in formal verification. We develop novel algorithms for two functionalities which ar

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38

Ferrara, Andrea. "Formal verification: further complexity issues and applications." Doctoral thesis, La Sapienza, 2006. http://hdl.handle.net/11573/917050.

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39

Kattenbelt, Mark Alex. "Automated quantitative software verification." Thesis, University of Oxford, 2010. http://ora.ox.ac.uk/objects/uuid:62430df4-7fdf-4c4f-b3cd-97ba8912c9f5.

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Many software systems exhibit probabilistic behaviour, either added explicitly, to improve performance or to break symmetry, or implicitly, through interaction with unreliable networks or faulty hardware. When employed in safety-critical applications, it is important to rigorously analyse the behaviour of these systems. This can be done with a formal verification technique called model checking, which establishes properties of systems by algorithmically considering all execution scenarios. In the presence of probabilistic behaviour, we consider quantitative properties such as "the worst-case p

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40

Eleftherakis, George. "Formal verification of X-machine models : towards formal development of computer-based systems." Thesis, University of Sheffield, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.400012.

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41

Hossain, Mousam. "Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification." Thesis, North Dakota State University, 2019. https://hdl.handle.net/10365/31574.

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Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before commercialization. Unlike other QDI paradigms, such as NULL Convention Logic (NCL) and Pre-Charge Half Buffers (PCHB), there exists no formal verification methods for SCL. In this thesis, a unified formal verification scheme for combinational as well as sequential SCL circuits is proposed based on equivalence checking, which verifies both safety and liveness. The method is demon

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42

Mohnke, Janett. "A signature-based approach to formal logic verification." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=960520406.

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43

Traub, Johannes [Verfasser]. "Formal Verification of Concurrent Embedded Software / Johannes Traub." Kiel : Universitätsbibliothek Kiel, 2016. http://d-nb.info/1105472175/34.

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44

Argote, Garcia Gonzalo. "Formal verification and testing of software architectural models." FIU Digital Commons, 2009. http://digitalcommons.fiu.edu/etd/1308.

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Ensuring the correctness of software has been the major motivation in software research, constituting a Grand Challenge. Due to its impact in the final implementation, one critical aspect of software is its architectural design. By guaranteeing a correct architectural design, major and costly flaws can be caught early on in the development cycle. Software architecture design has received a lot of attention in the past years, with several methods, techniques and tools developed. However, there is still more to be done, such as providing adequate formal analysis of software architectures. On the

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45

Yao, Håkansson Jonathan, and Niklas Rosencrantz. "Formal Verification of Hardware Peripheral with Security Property." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-209807.

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One problem with computers is that the operating system automatically trusts any externallyconnected peripheral. This can result in abuse when a peripheral technically can violate the security model because the peripheral is trusted. Because of that the security is an important issue to look at.The aim of our project is to see in which cases hardware peripherals can be trusted. We built amodel of the universal asynchronous transmitter/receiver (UART), a model of the main memory(RAM) and a model of a DMA controller. We analysed interaction between hardware peripherals,user processes and the mai

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46

Mejri, Mohamed. "A formal automatic verification of authentication cryptographic protocols." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/mq26244.pdf.

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Negulescu, Radu. "Process spaces and formal verification of asynchronous circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ32848.pdf.

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Kong, Xiaohua 1974. "Formal verification of peephole optimization in asynchronous circuits." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=32962.

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This thesis proposes and applies novel techniques for formal verification of peephole optimizations in asynchronous circuits. Our task is to verify whether locally optimized modules can replace parts of an existing circuit under certain assumptions regarding the operation of the optimized modules in context. Two main difficulties in verifying peephole optimizations are state explosion in the implementation models and increased complexity of the interfaces of optimized modules. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode

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Sarraf, Danny. "Optimizing assertions in semi-formal assertion- based verification." Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=116927.

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Assertion-based verification (ABV) is a powerful verification approach that has been proven to help digital IC architects, designers, and verification engineers improve design quality and reduce time to market.Assertions are a very powerful, concise and precise mechanism to specify properties of logic design. They run in all verification environments: simulation, emulation/acceleration and formal. In addition, they can be used as checkers or alternatively as assumptions.Some of the major challenges of ABV are that assertions are time-consuming to debug, there's no good way to measure the quali

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Meedeniya, Dulani Apeksha. "Correct model-to-model transformation for formal verification." Thesis, University of St Andrews, 2013. http://hdl.handle.net/10023/3691.

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Modern software systems have increasingly higher expectations on their reliability, in particular if the systems are critical and real-time. The development of these complex software systems requires strong modelling and analysis methods including quantitative modelling and formal verification. Unified Modelling Language (UML) is a widely used and intuitive graphical modelling language to design complex systems, while formal models provide a theoretical support to verify system design models. However, UML models are not sufficient to guarantee correct system designs and formal models, on the o

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