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Gotowa bibliografia na temat „FPGA application in Power system”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "FPGA application in Power system"

Piróg, S., R. Stala, and Ł. Stawiarski. "Power electronic converter for photovoltaic systems with the use of FPGA-based real-time modeling of single phase grid-connected systems." Bulletin of the Polish Academy of Sciences: Technical Sciences 57, no. 4 (2009): 345–54. http://dx.doi.org/10.2478/v10175-010-0137-9.

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Power electronic converter for photovoltaic systems with the use of FPGA-based real-time modeling of single phase grid-connected systemsThe paper presents a method of investigation of grid connected systems with a renewable energy source. The method enables fast prototyping of control systems and power converters components by real-time simulation of the system. Components of the system such as energy source (PV array), converters, filters, sensors and control algorithms are modeled in FPGA IC. Testing the systems before its practical application reduces cost and time-to-market. FPGA devices are commonly used for digital control. The resources of the FPGAs used for preliminary testing can be sufficient for the complete system modelling. Debugging tools for FPGA enable observation of many signals of the analyzed power system (as a result of the control), with very advanced triggering tools. The presented method of simulation with the use of hardware model of the power system in comparison to classical simulation tools gives better possibilities for verification of control algorithms such as MPPT or anti-islanding.

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Göhringer, Diana, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos H. Llanos, and Jürgen Becker. "Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems." International Journal of Reconfigurable Computing 2011 (2011): 1–17. http://dx.doi.org/10.1155/2011/985931.

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The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and runtime to achieve an efficient system solution in terms of performance, power and energy consumption. Such parameters are, for example, the number of processors and their configurations, the clock frequencies at design time, the use of dynamic frequency scaling at runtime, the application task distribution, and the FPGA type and size. The major contribution of this paper is the exploration of all these parameters and their impact on performance, power dissipation, and energy consumption for four different application scenarios. The goal is to introduce a first approach for a developer's guideline, supporting the choice of an optimized and specific system parameterization for a target application on FPGA-based multiprocessor systems-on-chip. The FPGAs used for these explorations were Xilinx Virtex-4 and Xilinx Virtex-5. The performance results were measured on the FPGA while the power consumption was estimated using the Xilinx XPower Analyzer tool. Finally, a novel runtime adaptive multiprocessor architecture for dynamic clock frequency scaling is introduced and used for the performance, power and energy consumption evaluations.

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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>

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Ding, Dian Kuan, Li Xin Li, Yi Wan, and Qi Xue. "Studies on MPPT in the Grid-Connected Photovoltaic Power Generation System Application." Applied Mechanics and Materials 63-64 (June 2011): 377–80. http://dx.doi.org/10.4028/www.scientific.net/amm.63-64.377.

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A set of PV grid-connected controlling system basing on FPGA and MCU is designed after the study of PV grid-connected system in this paper. The function of FPGA is to control the inverter main current, and the MCU is used to realize the MPPT technology. It is very effective after testing.

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UZUN, ISA SERVAN, and ABBES AMIRA. "A FPGA-BASED PARAMETRIZABLE SYSTEM FOR HIGH-RESOLUTION FREQUENCY-DOMAIN IMAGE FILTERING." Journal of Circuits, Systems and Computers 14, no. 05 (2005): 895–921. http://dx.doi.org/10.1142/s0218126605002775.

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Signal and image processing applications require high computational power with the ability to experiment different algorithms involving matrix transforms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed to obtain high performance at an economical price. However, the users must program FPGAs at a very low level and must have a detailed knowledge of the architecture of the device being used. In trying to reconcile the dual requirements of high performance and the ease of development, this paper reports the design and realization of the Fast Fourier Transforms (FFTs) using a FPGA-based environment, which enables system designer to meet different system requirements (i.e., chip area, speed, memory, etc.) for a range of signal processing and imaging applications. The use of the proposed environment has been proven by the developing a high-level FPGA-based parametrizable image processing system for frequency-domain filtering application. The system achieves real-time image filtering performance exceeding those of currently available solutions by an order of magnitude in frame rate and input image size.

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Drozd, Oleksandr, Grzegorz Nowakowski, Anatoliy Sachenko, Viktor Antoniuk, Volodymyr Kochan, and Myroslav Drozd. "Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application." Sensors 21, no. 3 (2021): 792. http://dx.doi.org/10.3390/s21030792.

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This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements in the evaluation and measurement of corresponding energy parameters. Energy parameter orientation has proved to be a good solution for detecting a synchronization failure that blocks logic monitoring circuits. Key advantages lay in the possibility to detect a synchronization failure hidden in safety-related systems by using traditional online testing that is based on logical checkability. Two main types of power-oriented monitoring are considered: detecting a synchronization failure based on the consumption and the dissipation of power, which uses temperature and current consumption sensors, respectively. The experiments are performed on real FPGA systems with the controlled synchronization disconnection and the use of the computer-aided design (CAD) utility to estimate the decreasing values of the energy parameters. The results demonstrate the limited checkability of FPGA systems when using the thermal monitoring of clock signals and success in monitoring by the consumption current.

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Hosseinghorban, Ali, and Akash Kumar. "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications." Electronics 11, no. 7 (2022): 978. http://dx.doi.org/10.3390/electronics11070978.

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Rapid and continuous evolution in telecommunication standards and applications has increased the demand for a platform with high parallelization capability, high flexibility, and low power consumption. FPGAs are known platforms that can provide all these requirements. However, the evaluation of approaches, architectures, and scheduling policies in this era requires a suitable and open-source benchmark suite that runs on FPGA. This paper harnesses high-level synthesis tools to implement high-performance, resource-efficient, and easy-maintenance kernels for FPGAs. We provide various implementations of each kernel of PHY-Bench and WiBench, which are the most well-known benchmark suites for telecommunication applications on FPGAs. We analyze the execution time and power consumption of different kernels on ARM processors and FPGA. We have made all sources and documentation public for the benefit of the research community. The codes are flexible, and all kernels can easily be regenerated for different sizes. The results show that the FPGA can increase the speed by up to 19.4 times. Furthermore, we show that the power consumption of the FPGA can be reduced by up to 45% by partially reconfiguring a kernel that fits the size of the input data instead of using a large kernel that supports all inputs. We also show that partial reconfiguration can improve the execution time for processing a sub-frame in the uplink application by 33% compared to an FPGA-based approach without partial reconfiguration.

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Blouin, Dominique, Daniel Chillet, Eric Senn, Sébastien Bilavarn, Robin Bonamy, and Christian Samoyeau. "AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC." International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/425401.

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With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded. Current applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable logic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration. But the dimension introduced in the design of these systems requires more abstraction to manage their complexity and efficient models to provide reliable preliminary estimations. While classical multiprocessor systems can be modeled without difficulty, the use of partial run-time reconfiguration in heterogeneous flexible system-on-chips is generally not covered. The contribution of this paper is to address this with an extension of the AADL language able to model the reconfigurable logic, possibly considering dynamic reconfiguration and power consumption requirements. The proposed AADL model is divided into three levels to provide a generic and hierarchical approach separating the static and dynamic parts of current FPGAs. These levels are exposed in detail and illustrated on a concrete example of FPGA device. The design space exploration of an application deployment using this model is also presented.

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Jamieson, Peter, Donald Blank, Janelle Ghanem, Tyler McGrew, and Giancarlo Corti. "A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System." International Journal of Reconfigurable Computing 2022 (May 6, 2022): 1–10. http://dx.doi.org/10.1155/2022/8827417.

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In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board. This work presents an FPGA controlled system that takes ladder diagram (LD) control for a PLC and converts this control to Verilog HDL and programs an FPGA such that the FPGA prototyping board is used to control a real industrial application. We explore this approach since FPGA implementation of LD control could significantly reduce the cost of implementing these controllers with other potential advantages such as the improved granularity of timing control from milliseconds to nanoseconds, additional available pins for inputs and outputs far exceeding that of microprocessors, and lower power consumption for control. In this work, we provide details and descriptions of our industrial system (ALD), the LD control of this system and its implementation, our software flow to convert LDs to Verilog HDL, and our FPGA prototype board design to replace the existing electronic controller. We show how our LD-Verilog HDL converter in conjunction with FPGAs matches a PLC and demonstrate some of the benefits of using an FPGA.

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Zhu, Qi Shen. "The Application of Remote Monitoring System Based on FPGA in Power System." Advanced Materials Research 433-440 (January 2012): 4038–41. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4038.

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Modbus bus has been widely used in the power system. For the seamless integrated realization of enterprise control and management information, the remote interaction of Modbus bus meter data is needed. This design is based on the problems involved in the process of practical power system application. Using FPGA EP2C35F672 hardware platform, UART, DM9000A external chips are extended to complete remote operation and monitoring of Modbus equipment. The field bus and the Internet network interconnection can be realized, so the decentralization and open for control system are improved. The design can be used to rebuild the existing power field bus network. This design has good prospects and practical value.

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