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Data publikacji: 4 czerwca 2021

Data aktualizacji: 29 lipca 2024

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1

Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Baweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.

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Tan, Zhou. "Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing." Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29176.

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This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two w

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4

Hu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.

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Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.

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6

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.<br>Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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7

Qi, Wen-jie. "Study on high-k dielectrics as alternative gate insulators for 0.1[mu] and beyond ULSI applications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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8

Mao, Yu-lung. "Novel high-K gate dielectric engineering and thermal stability of critical interface /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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9

Lee, Jian-hung. "Strontium titanate thin films for ULSI memory and gate dielectric applications /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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10

Kucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.

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11

Lee, Byoung Hun. "Technology development and process integration of alternative gate dielectric material : hafnium oxide /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004316.

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12

Luo, Tien-ying. "Electrical and physical analysis of ultra-thin in-situ steam generated (ISSG) SiO₂ and nitride/oxide stacks for ULSI application /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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13

Yin, Chunshan. "Source/drain and gate design of advanced MOSFET devices /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20YIN.

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14

Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.

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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a cong

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15

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design

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16

Blum, Thomas. "Modular exponentiation on reconfigurable hardware." Digital WPI, 1999. http://www.wpi.edu/Pubs/ETD/Available/etd-090399-090413/unrestricted/thesis.pdf.

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17

Hooper, Mark S. "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.

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18

Fourie, Coenrad Johann. "A tool kit for the design of superconducting programmable gate arrays." Thesis, Stellenbosch : University of Stellenbosch, 2004. http://hdl.handle.net/10019.1/16048.

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Thesis (PhD)--University of Stellenbosch, 2003.<br>ENGLISH ABSTRACT: The development of a tool kit for the design of superconducting programmable gate arrays (SPGAs) is discussed. A circuit optimizer using genetic algorithms is developed and evaluated. Techniques and a program are also developed for the generation of segmentized 3D models with which to calculate inductance in circuit structures through FastHenry. The ability to add random variations to the dimensions of the models is included. These tools are then used to design novel latching elements that allow the construction of repr

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19

Coyne, Jack W. "FPGA-based co-processor for singular value array reconciliation tomography." Worcester, Mass. : Worcester Polytechnic Institute, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-090507-114502/.

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20

Schafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.

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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unat

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21

Jeon, Yongjoo. "High-k gate dielectric for 100 nm MOSFET application /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004296.

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22

Chen, Yuh-yue. "Enhanced hot-hole degradation and negative bias temperature instability (NBTI) in p⁺-poly PMOSFETs with oxynitride gate dielectrics /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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23

Mulfinger, G. Robert. "Investigation of induced charge damage on self-aligned metal-gate MOS devices /." Online version of thesis, 2006. http://hdl.handle.net/1850/2036.

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24

Lin, Limin. "A study of gate dielectrics for wide-bandgap semiconductors GaN & SiC /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/hkuto/record/B3932252X.

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25

Lin, Limin, and 林立旻. "A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B3932252X.

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26

Chawla, Ravi. "Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications." Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-01052005-144937/unrestricted/chawla%5Fravi%5F200505%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Paul Hasler, Committee Member ; Joy Laskar, Committee Chair ; Phil Allen, Committee Member ; Dave Anderson, Committee Member ; Mark T. Smith, Committee Member. Includes bibliographical references.

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27

Deng, Linfeng, and 邓林峰. "A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47244513.

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Compared with its inorganic counterpart, organic thin-film transistor (OTFT) has advantages such as low-temperature fabrication, adaptability to large-area flexible substrate, and low cost. However, they usually need high operating voltage and thus are not suitable for portable applications. Although reducing their gate–dielectric thickness can lower the operating voltage, it increases their gate leakage. A better way is making use of high-κ gate dielectric, which is the main theme of this research. Firstly, pentacene OTFTs with HfO2 gate dielectric nitrided in N2O or NH3 at 200 oC were stu

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28

Kang, Laeugu. "Study of HFO₂ as a future gate dielectric and implementation of polysilicon electrodes for HFO₂ films /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004301.

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29

Zaghloul, Yasser A. "Polarization based digital optical representation, gates, and processor." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43675.

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A complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor could be implemented, was proposed. Following the new polarization-based representation, a new Orthoparallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output once in a truth table, was developed. This representation allows for the implementation of all basic 16 logic gates, including the NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generaliz

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30

Wu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.

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The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logi

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31

Oberdorf, Michael Craig. "Power losses and thermal modeling of a voltage source inverter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Mar%5FOberdorf.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2006.<br>Thesis Advisor(s): Alexander Julian. "March 2006." Includes bibliographical references (p. 103-104). Also available online.

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32

Lodaya, Bhaveen. "On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory." Master's thesis, Universitätsbibliothek Chemnitz, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-233196.

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User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limi

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33

Blanchardon, Adrien. "Synthèse d'architectures de circuits FPGA tolérants aux défauts." Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066274/document.

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L'essor considérable de la technologie CMOS a permis l'accroissement de la densité d'intégration selon la loi de Moore. Cependant, la poursuite de cette évolution est en voie de ralentissement dû aux contraintes physiques et économiques. Le défi devient alors de pouvoir utiliser un maximum de circuits tout en tolérant des défauts physiques présents en leur sein. Les circuits reconfigurables de type FPGA (Field Programmable Gate Array) connaissent un succès croissant car leurs performances et leurs capacités d'intégrer des applications très complexes ont directement bénéficié de l'évolution tec

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Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.

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The development of cost-effective circuits is primarily a matter of economy. To achieve it, design errors and circuit flaws must be eliminated during the design process. To this end, considerable effort must be put into all phases of the design cycle. Effective CAD tools are essential for the production of high-performance digital systems. This thesis describes a CAD tool called LOVERD, which consists of ATPG, fault simulation, design verification and diagnosis. It uses test patterns, developed to detect single stuck-at faults in the gate-level implementation, to compare the results of the fun

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Blanchardon, Adrien. "Synthèse d'architectures de circuits FPGA tolérants aux défauts." Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066274.

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L'essor considérable de la technologie CMOS a permis l'accroissement de la densité d'intégration selon la loi de Moore. Cependant, la poursuite de cette évolution est en voie de ralentissement dû aux contraintes physiques et économiques. Le défi devient alors de pouvoir utiliser un maximum de circuits tout en tolérant des défauts physiques présents en leur sein. Les circuits reconfigurables de type FPGA (Field Programmable Gate Array) connaissent un succès croissant car leurs performances et leurs capacités d'intégrer des applications très complexes ont directement bénéficié de l'évolution tec

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36

Pimenta, Valdiney Alves. "Metodologia Brazil-IP : registro do metodo e analise de casos de uso e experiencias ocorridas durante os trabalhos deste consorcio." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276080.

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Orientador: Rodolfo Jardim de Azevedo<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação<br>Made available in DSpace on 2018-08-11T08:21:02Z (GMT). No. of bitstreams: 1 Pimenta_ValdineyAlves_M.pdf: 5178774 bytes, checksum: 75a2335b2db0969f79ae380d7479bff2 (MD5) Previous issue date: 2008<br>Resumo: Contrariando as projeções para crescimento da economia mundial, o mercado de semicondutores cresce de forma acelerada, a uma taxa superior a 10% ao ano, movimentando anualmente mais de 270 bilhões de dólares. Acompanhando este crescimento, a importação de compone

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37

Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.

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In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the dig

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38

Doré, Jean-Baptiste. "Optimisation conjointe de codes LDPC (Low Density Parity Check) et de leurs architectures de décodage et mise en oeuvre sur FPGA (Field Programmable Gate Array)." Rennes, INSA, 2007. https://tel.archives-ouvertes.fr/tel-00191155v2.

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La découverte dans les années 90 des Turbo-codes et, plus généralement du principe itératif appliqué au traitement du signal, a révolutionné la manière d'appréhender un système de communications numériques. Cette avancée notable a permis la re-découverte des codes correcteurs d'erreurs inventés par R. Gallager en 1963, appelés codes Low Density Parity Check (LDPC). L'intégration des techniques de codage dites avancées, telles que les Turbo-codes et les codes LDPC, se généralise dans les standards de communications. Dans ce contexte, l'objectif de cette thèse est d'étudier de nouvelles structur

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39

Foote, David W. "The Design, Realization and Testing of the ILU of the CCM2 Using FPGA Technology." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4703.

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Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing s

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40

Her, Shyang-Kuen. "Improved I/O pad positions assignment algorithm for sea-of-gates placement." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4316.

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A new heuristic method to improve the I/O pad assignment for the sea-of-gates placement algorithm "PROUD" is proposed. In PROUD, the preplaced I/O pads are used as the boundary conditions in solving sparse linear equations to obtain the optimal module placement. Due to the total wire length determined by the module positions is the strong function of the preplaced I/O pad positions, the optimization of the I/O pad circular order and their assignment to the physical locations on the chip are attempted in the thesis. The proposed I/O pad assignment program is used as a predecessor of PROUD. The

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41

Choudhary, Aarti. "A process variation tolerant self compensation sense amplifier design." Connect to this title, 2008. http://scholarworks.umass.edu/theses/166/.

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42

Choy, C. S. O. "A bipolar multilevel differential logic gate array." Thesis, University of Manchester, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.378029.

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43

Mashayekhi, Mohammad. "Inkjet-configurable gate arrays: towards application specific printed electronic circuits." Doctoral thesis, Universitat Autònoma de Barcelona, 2016. http://hdl.handle.net/10803/402272.

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Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates. Just as the first information revolution caused by integrated silicon circuits, PE is expected to cause another revolution characterized by the distribution of information systems in all aspects of life. Although the integrated circuits, based on Organic Thin Film Transistors

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44

Honoré, Francis. "Energy-aware architectures, circuits and CAD for field programmable gate arrays." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37911.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 113-117).<br>Field Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of

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45

Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.

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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application t

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46

Green, A. D. P. "A percolation model for VLSI routing processes and its application in analysis and design of channelled structures." Thesis, University of Essex, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234181.

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47

Zhang, Chengjin. "An investigation into the realisation and testing of a universal logic primitive gate array." Thesis, University of Bath, 1988. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384137.

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48

Clark, Christopher R. "A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14138.

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The objective of this dissertation is to develop a methodology for describing the functionality, analyzing the complexity, and evaluating the performance of a large class of pattern-matching circuit design approaches for field-programmable gate arrays (FPGAs). The developed methodology consists of three elements. The first is a functional model and associated nomenclature that unifies a significant portion of published circuit design approaches while also illuminating many novel approaches. The second is a set of analytical expressions that model the area and time complexity of each circuit

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49

Subramanian, Shyam. "Methods for synthesis of multiple-input translinear element networks." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22591.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley.

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MAL, PROSENJIT. "DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.

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