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Sheikhbahaei, Shahriar. "Astroglial control of respiratory rhythm generating circuits." Thesis, University College London (University of London), 2017. http://discovery.ucl.ac.uk/10037956/.
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Astrocytes, the most numerous glial cells of the central nervous system, are well known to provide neuronal circuits with essential structural and metabolic support. There is also evidence that astrocytes may modulate the activities of neuronal circuits controlling motor rhythms including those of the brainstem’s preBötzinger complex (preBötC) that generates the rhythm of breathing in mammals. However, the extent and mechanisms of active astroglial control of the respiratory rhythm-generating circuits remain unknown. The morphological features of astrocytes in this critical brainstem region are also unknown. In this dissertation, viral gene transfer approaches designed to block or activate astroglial signaling pathways were used to determine the role of preBötC astrocytes in the control of breathing using in vitro and in vivo experimental models. Computer-aided morphometric analyses were used to investigate the structural features of brainstem astrocytes potentially contributing to their functional role. The results from these complementary, multi-faceted experiments show that (i) morphologically, preBötC astrocytes are larger, have more branches, and longer processes when compared to astrocytes residing in other regions of the brainstem; (ii) in conscious adult rats, blockade of vesicular release mechanisms or ATP-mediated signaling in preBötC astrocytes by virally-induced bilateral expression of either the light chain of tetanus toxin (TeLC), the dominant-negative SNARE proteins (dnSNARE), or a potent ectonucleotidase – transmembrane prostatic acid phosphatase – results in a significant reduction of resting respiratory frequency and frequency of sighs, augmented breaths that engage preBötC circuits to increase inspiratory effort; (iii) hypoxic- and CO2-induced ventilatory responses are significantly reduced when vesicular release mechanisms in preBötC astrocytes are blocked; (iv) activation of preBötC astrocytes expressing Gq-coupled Designer Receptor Exclusively Activated by Designer Drug is associated with higher frequency of both normal inspirations and sighs; (v) blockade of vesicular release mechanisms (expression of TeLC or dnSNARE) in preBötC astrocytes is associated with a dramatic reduction of exercise capacity. These data suggest that astroglial mechanisms involving exocytotic vesicular release of signaling molecules (gliotransmitters), provides tonic excitatory drive to the inspiratory rhythm-generating circuits of the preBötC and contributes to the generation of sighs. The role of preBötC astrocytes in central nervous mechanisms controlling breathing becomes especially important in conditions of metabolic stress requiring homeostatic adjustments of breathing such as systemic hypoxia, hypercapnia, and exercise, when enhanced respiratory efforts are critical to support physiological and behavioral demands of the body.
2
Wang, Jianwei. "Generating, manipulating, distributing and analysing light's quantum states using integrated photonic circuits." Thesis, University of Bristol, 2015. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.702227.
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The emergence of integrated quantum photonics is revolutionising the field of photonic quantum information science and technology. Quantum photonic waveguide platforms, capable of integrating single photon sources, quantum optical circuits and single photon detectors on semiconductor chips by exploring mature micro- or nano-fabrication technology, greatly promise unprecedented complexity, miniaturisation, scalability and robustness for advanced quantum information applications, including quantum communication, sensing, simulation, machine learning and computing. This thesis is to continually enlarge the scope of integrated quantum photonics technology by developing new materials, devices and systems for new functionalities including generation, manipulation, transmission, distribution, interconversion and measurement of photonic quantum states. Gallium arsenide waveguide quantum circuits are first developed to manipulate photons, demonstrating two-photon quantum interference in integrated beamsplitters and manipulation of photon number entanglement in optical interferometers utilising the linear electro-optic effect of gallium arsenide. We also demonstrate a chip-to-chip quantum photonic interconnect, by demonstrating high-fidelity entanglement generation, manipulation, transmission, distribution and measurement across two separate integrated silicon quantum photonic chips. A highfidelity interconversion of path and polarisation encoding preserves coherence across the full interconnected chip-to-chip system. This would allows quantum information encoding, processing and analysing on chips and quantum information transmission and distribution across chips, towards the multi-chip and multi-core quantum systems. We report on-chip generation of high-purity orbital angular momentum states and the fast-speed reconfigurability and switch-ability using an ultra-compact integrated silicon microring resonator embedded with angular diffractive gratings. Quantitive and qualitative measurements are performed to analyse the orbital angular momentum states from the chip. This might allow a high-capacity quantum interconnectivity of free space and integrated quantum circuits for many quantum information prototypes. This thesis demonstrates the capabilities of on-chip encoding, controlling, transferring and analysing quantum states in photon's path, polarisation and spatial modes degrees of freedom, providing a new generation of integrated quantum photonics toolbox for future quantum information technology.
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McKnight, Walter Lee. "A meta system for generating software engineering environments /." The Ohio State University, 1985. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487260531958418.
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Ferraz, Rafael da Silva. "Dispositivo para medição de impedância em sistemas de aterramento elétricos em alta frequência." Universidade Federal de Goiás, 2016. http://repositorio.bc.ufg.br/tede/handle/tede/6615.
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Previous issue date: 2016-11-04<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES<br>This work presents the project and the implementation of a device that is capable of measuring the electrical effects, especially the impedance, in grounding meshes when subjected to atmospherical discharges. An analysis on the influence of the atmospheric discharges in electrical protection systems is performed and also a comparison between current and voltage impulsive circuits. The device is built of electronic circuits controlled by a microcontroller, with the possibility of parameter adjusting for shaping the generated impulse wave. The device was conceived such that it can be used for tests of soil impedance measurement and for verification of the behavior of electrical grounding systems under high frequencies. The results are presented for tests in different types of systems and there was satisfactory performance for the developed equipment when compared with a commercial device<br>Este trabalho apresenta o projeto e a implementação do dispositivo capaz de medir os efeitos elétricos, em especial, as impedâncias, em malha de aterramento, sujeito a descargas atmosféricas. Analisa-se as influências das descargas atmosféricas nos sistemas de proteção elétricos e desenvolve-se análise comparativa dos circuitos impulsivos de corrente e de tensão. Constrói-se o dispositivo que consiste de circuitos eletrônicos controlados por microcontrolador, com possibilidade de ajuste de parâmetros da onda gerada. O dispositivo produzido é utilizado para medição da impedância do solo e verificação do comportamento de sistemas de aterramento elétrico em baixas e altas frequências. São apresentados os resultados dos testes em diferentes tipos de sistemas, demonstrando o satisfatório desempenho quando comparado com instrumento comercial.
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Krishnamurthy, Smitha. "SOLAR AND FUEL CELL CIRCUIT MODELING, ANALYSIS AND INTEGRATIONS WITH POWER CONVERSION CIRCUITS FOR DISTRIBUTED GENERATION." Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3501.
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Renewable energy is considered to be one of the most promising alternatives for the growing energy demand in response to depletion of fossil fuels and undesired global warming issue. With such perspective, Solar Cells and Fuel Cells are most viable, environmentally sound, and sustainable energy sources for power generation. Solar and Fuel cells have created great interests in modern applications including distributed energy generation to provide clean energy. The purpose of this thesis was to perform a detailed analysis and modeling of Solar and Fuel cells using Cadence SPICE, and to investigate dynamic interactions between the modules and power conversion circuits. Equivalent electronic static and dynamic models for Solar and Fuel Cells, their electrical characteristics, and typical power loss mechanisms associated with them are demonstrated with simulation results. Power conversion circuits for integration with the dynamic models of these renewable low voltage sources are specifically chosen to boost and regulate the input low dc voltage from the modules. The scope of this work was to analyze and model solar and fuel cells to study their terminal characteristics, power loss mechanisms, modules and their dynamics when interfaced with power converters, which would lead to better understanding of these renewable sources in power applications.<br>M.S.<br>School of Electrical Engineering and Computer Science<br>Engineering and Computer Science<br>Electrical Engineering MSEE
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Bollinger, S. Wayne. "Hierarchical test generation for CMOS circuits." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-07282008-134708/.
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Lee, Kyung Tek. "Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Lazzari, Cristiano. "Transistor level automatic generation of radiation-hardened circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15506.
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Tecnologias submicrônicas (DSM) têm inserido novos desafios ao projeto de circuitos devido a redução de geometrias, redução na tensão de alimentação, aumento da freqüência e aumento da densidade de lógica. Estas características reduzem significativamente a confiabilidade dos circuitos integrados devido a suscetibilidade a efeitos como crosstalk e acoplamento de substrato. Ainda, os efeitos da radiação são mais significantes devido as partículas com baixa energia começam a ser um problema em tecnologias DSM. Todas essas características enfatizam a necessidade de novas ferramentas de automação. Um dos objetivos desta tese é desenvolver novas ferramentas aptas a lidar com estes desafios. Esta tese é dividida em duas grandes contribuições. A primeira está relacionada com o desenvolvimento de uma nova metodologia com o objetivo de gerar circuitos otimizados em respeito ao atraso e ao consumo de potência. Um novo fluxo de projeto é apresentado na qual o circuito é otimizado no nível de transistor. Esta metodologia permite otimizar cada transistor de acordo com as capacitâncias associadas. Diferente da metodologia tradicional, o leiaute é gerado sob demanda depois do processo de otimização de transistores. Resultados mostram melhora de 11% em relação ao atraso dos circuitos e 30% de redução no consumo de potência em comparação à metodologia tradicional. A segunda contribuição está relacionada com o desenvolvimento de técnicas de geração de circuitos tolerantes a radiação. Uma técnica CWSP é usada para aplicar redundância temporal em elementos seqüenciais. Esta técnica apresenta baixa utilização de área, mas as penalidades no atraso estão totalmente relacionadas com a duração do pulso que se planeja atenuar. Além disso, uma nova metodologia de dimensionamento de transistores para falhas transientes é apresentada. A metodologia de dimensionamento é baseada em um modelo analítico. O modelo considera independente blocos de transistores PMOS e NMOS. Então, somente transistores diretamente relacionados à atenuação são dimensionados. Resultados mostram área, atraso e consumo de potência reduzido em comparação com as técnicas CWSP e TMR, permitindo o desenvolvimento de circuitos com alta freqüência.<br>Deep submicron (DSM) technologies have increased the challenges in circuit designs due to geometry shrinking, power supply reduction, frequency increasing and high logic density. The reliability of integrated circuits is significantly reduced as a consequence of the susceptibility to crosstalk and substrate coupling. In addition, radiation effects are also more significant because particles with low energy, without importance in older technologies, start to be a problem in DSM technologies. All these characteristics emphasize the need for new Electronic Design Automation (EDA) tools. One of the goals of this thesis is to develop EDA tools able to cope with these DSM challenges. This thesis is divided in two major contributions. The first contribution is related to the development of a new methodology able to generate optimized circuits in respect to timing and power consumption. A new design flow is proposed in which the circuit is optimized at transistor level. This methodology allows the optimization of every single transistor according to the capacitances associated to it. Different from the traditional standard cell approach, the layout is generated on demand after a transistor level optimization process. Results show an average 11% delay improvement and more than 30% power saving in comparison with the traditional design flow. The second contribution of this thesis is related with the development of techniques for radiation-hardened circuits. The Code Word State Preserving (CWSP) technique is used to apply timing redundancy into latches and flipflops. This technique presents low area overhead, but timing penalties are totally related with the glitch duration is being attenuated. Further, a new transistor sizing methodology for Single Event Transient (SET) attenuation is proposed. The sizing method is based on an analytic model. The model considers independently pull-up and pull-down blocks. Thus, only transistors directly related to the SET attenuation are sized. Results show smaller area, timing and power consumption overhead in comparison with TMR and CWSP techniques allowing the development of high frequency circuits, with lower area and power overhead.
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Hutton, Michael D. "Characterization and parameterized generation of digital circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape16/PQDD_0021/NQ27666.pdf.
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Vasudevan, Dilip Prasad. "Automatic test pattern generation for asynchronous circuits." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/7670.
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The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the design process; a technique called design for test (DFT). Asynchronous circuits have a number of desirable properties making them suitable for the challenges posed by modern technologies, but are severely limited by the unavailability of EDA tools for DFT and automatic test-pattern generation (ATPG). This thesis is motivated towards developing test generation methodologies for asynchronous circuits. In total four methods were developed which are aimed at two different fault models: stuck-at faults at the basic logic gate level and transistor-level faults. The methods were evaluated using a set of benchmark circuits and compared favorably to previously published work. First, ABALLAST is a partial-scan DFT method adapting the well-known BALLAST technique for asynchronous circuits where balanced structures are used to guide the selection of the state-holding elements that will be scanned. The test inputs are automatically provided by a novel test pattern generator, which uses time frame unrolling to deal with the remaining, non-scanned sequential C-elements. The second method, called AGLOB, uses algorithms from strongly-connected components in graph graph theory as a method for finding the optimal position of breaking the loops in the asynchronous circuit and adding scan registers. The corresponding ATPG method converts cyclic circuits into acyclic for which standard tools can provide test patterns. These patterns are then automatically converted for use in the original cyclic circuits. The third method, ASCP, employs a new cycle enumeration method to find the loops present in a circuit. Enumerated cycles are then processed using an efficient set covering heuristic to select the scan elements for the circuit to be tested.Applying these methods to the benchmark circuits shows an improvement in fault coverage compared to previous work, which, for some circuits, was substantial. As no single method consistently outperforms the others in all benchmarks, they are all valuable as a designer’s suite of tools for testing. Moreover, since they are all scan-based, they are compatible and thus can be simultaneously used in different parts of a larger circuit. In the final method, ATRANTE, the main motivation of developing ATPG is supplemented by transistor level test generation. It is developed for asynchronous circuits designed using a State Transition Graph (STG) as their specification. The transistor-level circuit faults are efficiently mapped onto faults that modify the original STG. For each potential STG fault, the ATPG tool provides a sequence of test vectors that expose the difference in behavior to the output ports. The fault coverage obtained was 52-72 % higher than the coverage obtained using the gate level tests. Overall, four different design for test (DFT) methods for automatic test pattern generation (ATPG) for asynchronous circuits at both gate and transistor level were introduced in this thesis. A circuit extraction method for representing the asynchronous circuits at a higher level of abstraction was also implemented. Developing new methods for the test generation of asynchronous circuits in this thesis facilitates the test generation for asynchronous designs using the CAD tools available for testing the synchronous designs. Lessons learned and the research questions raised due to this work will impact the future work to probe the possibilities of developing robust CAD tools for testing the future asynchronous designs.
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Franco, Eduardo Vala. "Photonic integrated circuits for next generation PONs." Master's thesis, Universidade de Aveiro, 2017. http://hdl.handle.net/10773/23473.
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Mestrado em Engenharia Eletrónica e Telecomunicação<br>We are living in a time where communications became essential for most
of our lives, whether it's in the business world, or in our own homes. The
increasing need of higher bandwidth inhibits other networks other than optical
ber based ones.
Nowadays communications are responsible for a substantial percentage of
our energetic footprint, hence Passive Optical Network(PON) are a strong
contender for the next step of network implementation. These networks
present a low energy consumption because between the transmitter and the
receiver the signal stays in the optical domain.
Although the increasing needs of bandwidth is almost across the communication
world, certain services/identities need more bandwidth whether is
download or upload. It's easy to understand that di erent consumers have
unique needs. It's necessary to develop an architecture that serves all the
costumers, in other words, there is a need for a network that provides high
bitrate tra c to the users that needs it but also a network that serves the
low end user that is not interested in this increase of bandwidth and therefore
price in
ation.
There is today technologies yet to be widely implemented like NG-PON2
that were not implemented in a large scale because they dont represent a
nancial return to the telecom operators simply because there is not enough
user that requires the high bandwidth delivered by NG-PON2. It's necessary
to nd a solution that includes not only the modern technologies but also
the already implemented ones.
With the objective of nding a solution for the problems mentioned before,
this dissertation has the objective of designing a Photonic Integrated
Circuit(PIC) that aims to be a transceiver of a Multitech Network that
will be composed by the following technologies: Video-Overlay, XG-PON e
NG-PON2. This dissertation presents an approach on Passive Optical Networks(
PON) and the standards of the said technologies as well as a study
of the components needed to assemble the transceiver using the programs
ASPIC and VPI Photonics . In the end, there will be presented an architecture
for the transceiver to be used in a Optical Network Unit(ONU), and
the respective mask Layout.<br>Vivemos numa época em que as comunicações se tornaram essenciais para
grande parte da nossa vida, seja no mundo empresarial, seja nas nossas
habitações. A crescente necessidade de aumento de largura de banda inviabiliza
outras redes que não baseadas em braotica.
Actualmente as comunicações são responsáveis por uma percentagem substancial
dos nossos gastos energéticos, justamente por este facto Passive
Optical Networks(PON) sao as principais candidatas ao próximo passo no
desenvolvimento de redes. Estas apresentam menor consumo energético,
pois entre o emissor e o receptor todo o sinal permanece no domínio óptico.
Apesar da necessidade de largura de banda estar a aumentar de um modo
transversal no mundo das telecomunicações, certos serviços/entidades necessitam
de maiores velocidades tanto em termos de download como em termos
de upload. E então fácil de perceber que consumidores diferentes têm
necessidades diferentes. E necessário encontrar uma arquitectura que agrade
a quem necessita de maiores larguras de banda mas também a quem não
necessita de um aumento significativo e que, não está disposto a pagar por
este. Existem neste momento tecnologias que ainda não foram implementadas
em grandes escalas, como o caso de Next Generation Passive Optical
Network (NG-PON2), porque não simbolizam um retorno financeiro para as
grande operadores, uma vez que o número de potenciais consumidores de
tais velocidades ainda não e substancialmente grande. E necessário encontrar
uma solução que não so englobe as novas tecnologias como também
as já existentes.
Com o objectivo de se encontrar um solução para os problemas acima referidos,
este trabalho assenta na elaboração de um Circuito integrado fotonico
que visa ser um transrecetor de uma arquitetura multi-tecnologia em que
irão ser incorporadas tecnologias como Video-Overlay, 10 Gigabit-capable
Passive Optical Network (XG-PON) e NG-PON2. Esta dissertação apresenta
uma abordagem as Redes Oticas Passivas e também um estudo feito
aos componentes usados no transreceptor usando os programas Aspic e
VPI Photonics . Porém ser a apresentado o desenho final do transreceptor
que ser a usado numa Optical Network Unit(ONU).
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Tupuri, Raghuram Srinivasa. "Hierarchical sequential test generation for large circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Barradas, Henrique Molina. "Análise do impacto da inserção massiva de geração distribuída fotovoltaica nos níveis de curto-circuito em redes de distribuição de energia elétrica /." Ilha Solteira, 2018. http://hdl.handle.net/11449/157395.
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Orientador: Fábio Bertequini Leão<br>Resumo: Com a crescente utilização de fontes renováveis de geração de energia por parte dos consumidores de energia elétrica, há a necessidade de se avaliar quais serão os impactos da conexão destes geradores no sistema de distribuição. De modo geral, um sistema onde há geradores distribuídos (GDs) conectados apresentará alteração na corrente de curtocircuito devido ao aumento do nível de tensão. A mudança na corrente de curto-circuito que passa pelos dispositivos de proteção pode leva-los a atuações indesejadas, a atuações descoordenadas e a não atuarem. Para observar com maior detalhe o que ocorre no sistema quando são inseridos GDs, desenvolveu-se neste trabalho equações que descrevem principalmente a corrente de curto-circuito de um sistema para este cenário. Com isso pode-se observar qual a relação que a corrente na saída da subestação possui com as outras variáveis do sistema (correntes das cargas, das gerações e impedância das linhas do sistema), pois o local onde a GD é inserida pode causar efeitos distintos na corrente da subestação. Considerando que o maior número de GDs conectados no sistema brasileiro é do tipo solar, geradores fotovoltaicos, este trabalho traz uma análise para este tipo de gerador conectado no sistema. Este tipo de geração é interessante também pelo fato de utilizar inversores para a sua conexão com a rede. Para observar este comportamento são utilizados três sistemas testes, o primeiro apresenta 17 barras e a análise é realizada em baixa tensão, o segun... (Resumo completo, clicar acesso eletrônico abaixo)<br>Abstract: With the increasing use of renewable energy sources by electricity consumers, it is necessary to evaluate the impact of the connection of these generators to the distribution system. Generally, a system where there are connected distributed generators (GDs) will show a change in the short-circuit current due to the increased voltage level. The change in the short-circuit current that passes through the protection devices can lead them to unwanted actions, uncoordinated actions and not acting. To observe in more detail what happens in the system when GDs are inserted, we have developed in this work equations that mainly describe the short-circuit current of a system for this scenario. Thus, it is possible to observe the relation that the current in the output of the substation has with the other variables of the system (loads, generators and impedances of the system lines), because the place where the GD is inserted can cause different effects in the substation current. Considering that the largest number of GDs connected in the Brazilian system is of the solar type, photovoltaic generators, this work brings an analysis for this type of generator connected in the system. This type of generation is also interesting because it uses inverters for its connection to the network. In order to observe this behavior, three test systems are used, the first presents 17 buses and the analysis is carried out at low voltage, the second is the IEEE 13 bus system, where the influence on the m... (Complete abstract click electronic access below)<br>Mestre
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Du, Bin. "A global test generation system for sequential circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0007/NQ34670.pdf.
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Vilches, Antonio. "First generation monolithically integrated SiGe HFET micropower circuits." Thesis, Imperial College London, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.405888.
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Dezan, Catherine. "Generation automatique de circuits avec alpha du centaur." Rennes 1, 1993. http://www.theses.fr/1993REN10017.
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Alpha du centaur est un atelier de conception d'architectures regulieres. Afin de completer la chaine de conception, une extension de alpha du centaur pour la generation de circuits sous forme d'asic est proposee. La conception d'un circuit se fait par raffinements successifs de specifications initiales abstraites. Les differentes etapes de la conception sont realisees par transformations de programmes decrits en alpha. Les transformations de synthese d'architecture deja existantes sont alors completees par de nouvelles transformations. Ces dernieres permettent de generer le controle du circuit ainsi que de decomposer les calculs en fonctionnalites elementaires correspondant a des portes. Parallelement au processus de synthese, on s'interesse a la verification de circuits. On montre que la preuve d'un circuit peut se faire en utilisant une approche ascendante (synthese) et descendante (abstraction). La methodologie de preuve ainsi proposee permet de comparer la modelisation du circuit avec les specifications attendues de celui-ci. Les nouvelles transformations necessaires a la generation et a la verification ont ete validees avec alpha. Elles s'accompagnent de strategies d'application afin d'aider l'utilisateur dans sa conception
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SAMPATH, HEMANTH KUMAR. "A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882.
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Dowrick, Thomas Martin. "Biologically motivated circuits for third generation neural networks." Thesis, University of Liverpool, 2011. http://livrepository.liverpool.ac.uk/3024754/.
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Yu, Tein-Yow 1961. "Efficient backtracking strategies in test generation." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277191.
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This thesis addresses the problem of backtracking strategies in test generation. First, a methodology which uses status of absolute dominators as a means for causing backtracking during the test generation process is presented. Then, different heuristics that force the test generation to execute the backtracking procedure are investigated. Experiments which generated test patterns for over 30,000 faults have been used to evaluate these heuristics. According to the experimental results, we recommend a new backtracking strategy that has the best performance among the six strategies explored in this thesis.
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Chang, Wing Chien Christopher. "Operational characteristics of an SCR-based pulse generating circuit." Thesis, Monterey, California: Naval Postgraduate School, 2014. http://hdl.handle.net/10945/44535.
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Approved for public release; distribution is unlimited<br>A commercial off-the-shelf silicon controlled rectifier (SCR) was connected in series with a parallel RC load under DC bias to produce self-terminating voltage pulses. The physics underlying the switching mechanism of the SCR in such a circuit was investigated and the values of load resistance and capacitance varied to ascertain their role on the pulse-generating capability of the circuit. When pulsing was successfully achieved, a reverse recovery current was always present to return the SCR from its on state to its off state. In addition, the regenerative process responsible for turning the SCR is through the avalanche multiplication of charge carriers within the device. This appeared to be independent of the mode of triggering, either by increasing the DC bias or using a current at the gate. Significantly, pulsing was discovered to be sustainable for a specific range of RC values that depends on the SCR’s intrinsic turn-off time. Specifically, it was found that without making modifications to the SCR itself, the minimum dead time achievable between pulses was essentially the turn-off time of the SCR. The findings of the research will help to design optimum SCR-based circuits for pulse mode detection of light and ionizing radiation without external amplification circuitry.
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Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.
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Prabhu, Sarvesh P. "Techniques for Enhancing Test and Diagnosis of Digital Circuits." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/51181.
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Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an Automated Test Equipment (ATE) and applying test patterns to test for different faults. With shrinking feature sizes, the complexity of the circuits on chip is increasing, which in turn increases the number of test patterns needed to test the chip comprehensively. This increases the test application time which further increases the cost of test, ultimately leading to increase in the cost per device.
Furthermore, chips that fail during test need to be diagnosed to determine the cause of the failure so that the manufacturing process can be improved to increase the yield. With increase in the size and complexity of the circuits, diagnosis is becoming an even more challenging and time consuming process. Fast diagnosis of failing chips can help in reducing the ramp-up to the high volume manufacturing stage and thus reduce the time to market. To reduce the time needed for diagnosis, efficient diagnostic patterns have to be generated that can distinguish between several faults. However, in order to reduce the test application time, the total number of patterns should be minimized. We propose a technique for generating diagnostic patterns that are inherently compact. Experimental results show up to 73% reduction in the number of diagnostic patterns needed to distinguish all faults.
Logic Built-in Self-Test (LBIST) is an alternative methodology for testing, wherein all components needed to test the chip are on the chip itself. This eliminates the need of expensive ATEs and allows for at-speed testing of chips. However, there is hardware overhead incurred in storing deterministic test patterns on chip and failing chips are hard to diagnose in this LBIST architecture due to limited observability. We propose a technique to reduce the number of patterns needed to be stored on chip and thus reduce the hardware overhead. We also propose a new LBIST architecture which increases the diagnosability in LBIST with a minimal hardware overhead. These two techniques overcome the disadvantages of LBIST and can make LBIST more popular solution for testing of chips.
Modern designs may contain a large number of small embedded memories. Memory Built-in Self-Test (MBIST) is the conventional technique of testing memories, but it incurs hardware overhead. Using MBIST for small embedded memories is impractical as the hardware overhead would be significantly high. Test generation for such circuits is difficult because the fault effect needs to be propagated through the memory. We propose a new technique for testing of circuits with embedded memories. By using SMT solver, we model memory at a high level of abstraction using theory of array, while keeping the surrounding logic at gate level. This effectively converts the test generation problem into a combinational test generation problem and make test generation easier than the conventional techniques.<br>Ph. D.
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Thakar, Sarita. "On the generation of test patterns for combinational circuits." Thesis, Virginia Tech, 1993. http://hdl.handle.net/10919/41915.
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Li, Wencheng. "A test generation system for behaviorally modeled digital circuits." Diss., This resource online, 1996. http://scholar.lib.vt.edu/theses/available/etd-09232008-144806/.
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Macías, Montero José Gabriel. "VIPPIX: A readout ASIC for the next generation of human brain PET scanners." Doctoral thesis, Universitat de Barcelona, 2018. http://hdl.handle.net/10803/663182.
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Positron emission tomography (PET) is a molecular imaging technique used for several decades in nuclear medicine that provides precise physiological information of the human body, what is crucial in oncology, cardiology, and neuropsychiatry. Due to physical, the best spatial resolution of PET is approximately 1 mm for human brain scanners. Unfortunately, the minimum resolution of the best commercial PET scanners for humans is 4-5 mm due to technological limitations.
In this thesis, an application specific integrated circuit (ASIC) to readout the energy and the time stamp of a high-density and highly-granulated Cadmium Telluride detector for a novel PET scanner design is presented. The research presented here was realized within the framework of Voxel Imaging PET pathfinder ERC project to develop detector modules for positron emission tomography applications and reach their actual physical limits.
The VIP PET scanner is based on the stacking of 2-mm thickness pixelated hybrid detectors. Every CdTe detector is pixelated into an array of 10 x 10 voxels of 1 mm x 1 mm x 2 mm size and is connected to a pixelated ASIC to readout independently the energy and the time stamp of every photon interaction. The VIP PET is based on more than 6 million voxels with independent energy and timing readout to reach the physical limits of PET. The simulated performance based on the properties of CdTe detectors shows a scatter fraction of approximately 4 % due to an excellent energy resolution of 1.6 % FWHM of the CdTe detectors. By simulation, the VIP PET is able to distinguish 1 mm size radioactive point-like source.
The characterization of 2-mm thickness CdTe detectors using commercially available single-channel readout electronics is reported. Using a Sodium-22 radioactive source, the 511 keV photopeak resolution and the coincidence time resolution of back-to-back photons were measured with – 1000 V/mm detector bias voltage at -8 Celsius degree. An energy resolution of
1.6 % FWHM and a time coincidence resolution of 6 ns FWHM were obtained for photoelectric interactions.
The architecture of the VIPPIX ASIC, i.e. the ASIC developed for VIP project, is based on an array of 10 x 10 independent pixel electronics controlled by a global controller and a common time to digital converter (TDC). Additional voltage and current references are generated in the ASIC’s back-end with a temperature sensor and a chip-ID cell. Every pixel electronics composes of a programmable gain preamplifier with detector’s leakage dynamic compensation, a tuneable peak-time pulse shaper connected to a peak-and-detect circuit, a 10-bit analog-to- digital converter (ADC), a pulse discriminator with adjustable offset, and a local pixel digital controller. The measured equivalent noise charge (ENC) of the pixel is 150 e- RMS and the trigger time jitter is approximately 1 ns for energy depositions larger than 200 keV. The time resolution of the integrated TDC is 600 ps FWHM.
Twelve wafers of VIPPIX ASIC has been fabricated and characterized. Best quality ASICs have been mounted on 720 CdTe detectors and stacked in 18 detector modules with 40 hybrid detectors each to build the VIP PET prototype. Five modules have been characterized with a Sodium-22 radioactive source. The performance of approximately 18000 pixels shows a resolution of 2.2 % FWHM and a coincidence time resolution of 60 ns FWHM for 511 keV photopeak at -250 V/mm detector bias.
Therefore, the main goal of the research has been accomplished. A new PET design based on pixelated Cadmium Telluride detectors using dedicated readout ASICs has been successfully fabricated, partly characterized, and is ready for image acquisition.
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Cho, Chang H. "A formal model for behavioral test generation." Diss., This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06062008-170406/.
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Raik, Jaan. "Hierarchical test generation for digital circuits represented by decision diagrams /." Tallinn : TTU Press, 2001. http://www.loc.gov/catdir/toc/fy0611/2006530982.html.
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Gautrin, Eric. "Madmacs : un systeme d'edition et de generation pour circuits integres." Rennes 1, 1986. http://www.theses.fr/1986REN10082.
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Madmacs est un logiciel interactif de dessin de circuits integres. Outre les commandes classiques de ce type d'editeur, permettant la creation et la modification de figures, madmacs contient des mecanismes originaux qui lui donnent une grande puissance: des commandes de deplacements relatifs du curseur graphique permettent a l'utilisateur de s'affranchir dans une large mesure de la taille des objets manipules; un mecanisme de macro-commandes autorise la definition de nouvelles commandes arbitrairement complexes, (a ce titre madmacs est un systeme ouvert); des procedures d'implantation automatique (pia) peuvent etre construites pour la generation de modules (registres, memoires de taille quelconque, unites arithmetiques, etc. . . ) ou encore pour memoriser la methode de construction (le placement-routage notamment) d'un circuit en vue de sa reconstruction automatique suite a des modifications. Madmacs represente donc un intermediaire entre l'approche graphique pure (tres souple), et l'approche langage de conception de circuits (tres parametrable)
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Caron, David. "Generating a control/data-flow graph representation of a circuit from VHDL for use in circuit synthesis." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0011/MQ27011.pdf.
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Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183139647.
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Ebbutt, Ralph. "Generation of dicing damage in silicon wafers." Thesis, Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/17878.
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Huynh, Sam DuPhat. "Testability analysis for mixed analog/digital circuit test generation and design for test /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6134.
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Zhang, Yu. "Ultra-thin nanocomposite diffusion barriers for the next-generation integrated circuits /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1136093561&sid=27&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Chakrabarti, Sudip. "Test generation for fault isolation in analog and mixed-mode circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14899.
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Xia, Likun. "Automatic generation of high level fault simulation models for analogue circuits." Thesis, University of Hull, 2008. http://hydra.hull.ac.uk/resources/hull:1601.
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High level modelling (HLM) for operational amplifiers (op amps) has been previously carried out successfully using models generated by published automated model generation (AMG) approaches. Furthermore, high level fault modelling (HLFM) has been shown to work reasonably well using manually designed fault models. However, no evidence shows that published AMG approaches based on op amps have been used in HLFM.This thesis describes an investigation into the development of adaptive self-tuning algorithms for automated analogue circuit modelling suitable for HLM and HLFM applications. The algorithms and simulation packages were written in MATLAB and the hardware description language - VHDL-AMS.The properties of these self-tuning algorithms were investigated by modelling a two-stage CMOS op amp and a comparator, and comparing simulations of the macromodel against those of the original SPICE circuit utilizing transient analysis.The proposed algorithms generate multiple models to cover a wide range of input conditions by detecting nonlinearity through variations in output error, and can achieve bumpless transfer between models and handle nonlinearity.This thesis describes the design, implementation and validation of these algorithms, their performance being evaluated for HLFM for both analogue and mix mode systems.HLFM results show that the models can handle both linear and nonlinear situations with good accuracy in a low-pass filter, and model digital outputs in a flash ADC correctly. Comparing with a published fault model, better accuracy has been achieved in terms of output signals using fault coverage measurement.
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Lazzari, Cristiano. "Automatic layout generation of static CMOS circuits targeting delay and power." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/5690.
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A crescente evolução das tecnologias de fabricação de circuitos integrados demanda o desenvolvimento de novas ferramentas de CAD. O desenvolvimento tradicional de circuitos digitais a nível físico baseia-se em bibliotecas de células. Estas bibliotecas de células oferecem certa previsibilidade do comportamento elétrico do projeto devido à caracterização prévia das células. Além disto,diferentes versões para cada célula são requeridas de forma que características como atraso e consumo sejam atendidos, aumentando o número de células necessárias em uma bilioteca. A geração automática de leiautes é uma alternativa cada vez mais importante para a geracão baseada em células. Este método implementa transistores e conexões de acordo com padrões que são definidos em algoritmos sem as limitações impostas pelo uso de uma biblioteca de células. A previsibilidade em leiautes gerado automaticamente é oferecida por ferramentas de análise e estimativa. Estas ferramentas devem ser aptas a trabalhar com estimativas do leiaute e gerar informações relativas a atraso, potência e área. Este trabalho inclui a pesquisa de novos métodos de síntese física e a implementação de um gerador automático de leiautes cujas células são geradas no momento da síntese do leiaute. A pesquisa investiga diferentes estratégias de disposição dos componentes (transistores, contatos e conexões) em um leiaute e seus efeitos na ocupação de área e no atraso e de um circuito. A estratégia de leiaute utilizada aplica técnicas de otimização de atraso pela integração com uma técnicas de dimensionamento de transistores. Isto é feito de forma que o método de folding permita diferentes dimensionamentos para os transistores. As principais características da estratégia proposta neste trabalho são: linhas de alimentação entre bandas, roteamento sobre o leiaute (não são utilizados canais de roteamento) e geração de leiautes visando a redução do atraso do circuito pela aplicação da técnica de dimensionamento ao leiaute e redução do comprimento médio das conexões. O fato de permitir a implementação de qualquer combinação de equações lógicas, sem as restrições impostas pelo uso de uma biblioteca de células, permite a síntese de circuitos com uma otimização do número de transistores utilizados. Isto contribui para a diminuição de atrasos e do consumo, especialmente do consumo estático em circuitos submicrônicos. Comparações entre a estratégia proposta e outros métodos conhecidos são apresentadas de forma a validar a proposta apresentada.<br>The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.
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KANKIPATI, SUNDER RAJAN. "MACRO MODEL GENERATION FOR SYNTHESIS OF ANALOG AND MIXED SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077297705.
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Repole, Kenzo K. D. "Generation of dicing damage in passivated silion wafers." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/17126.
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Chen, Baifeng. "High-efficiency Transformerless PV Inverter Circuits." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/56686.
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With worldwide growing demand for electric energy, there has been a great interest in exploring photovoltaic (PV) sources. For the PV generation system, the power converter is the most essential part for the efficiency and function performance. In recent years, there have been quite a few new transformerless PV inverters topologies, which eliminate the traditional line frequency transformers to achieve lower cost and higher efficiency, and maintain lower leakage current as well.
With an overview of the state-of-the-art transformerless PV inverters, a new inverter technology is summarized in the Chapter 2, which is named V-NPC inverter technology. Based this V-NPC technology, a family of high efficiency transformerless inverters are proposed and detailly analyzed. The experimental results demonstrate the validity of V-NPC technology and high performance of the transformerless inverters.
For the lower power level transformerless inverters, most of the innovative topologies try to use super junction metal oxide semiconductor field effect transistor(MOSFET) to boost efficiency, but these MOSFET based inverter topologies suffer from one or more of these drawbacks: MOSFET failure risk from body diode reverse recovery, increased conduction losses due to more devices, or low magnetics utilization. By splitting the conventional MOSFET based phase leg with an optimized inductor, Chapter 3 proposes a novel MOSFET based phase leg configuration to minimize these drawbacks. Based on the proposed phase leg configuration, a high efficiency single-phase MOSFET transformerless inverter is presented for the PV micro-inverter applications. The PWM modulation and circuit operation principle are then described. The common mode and differential mode voltage model is then presented and analyzed for circuit design. Experimental results of a 250 W hardware prototype are shown to demonstrate the merits of the proposed MOSFET based phase-le and the proposed transformerless inverter.
New codes require PV inverters to provide system regulation and service to improve the distribution system stabilization. One obvious impact on PV inverters is that they now need to have reactive power generation capability. The Chapter 4 improves the MOFET based transformerless inverter in the Chapter 3 and proposed a novel pulse width modulation (PWM) method for reactive power generation. The ground loop voltage of this inverter under the proposed PWM method is also derived with common mode and differential mode circuit analyses, which indicate that high-frequency voltage component can be minimized with symmetrical design of inductors. A 250-W inverter hardware prototype has been designed and fabricated. Steady state and transient operating conditions are tested to demonstrate the validity of improved inverter and proposed PWM method for reactive power generation, high efficiency of the inverter circuit, and the high-frequency-free ground loop voltage.
Besides the high efficiency inverter circuit, the grid connection function is also the essential part of the PV system. The Chapter 5 present the overall function blocks for a grid-connected PV inverter system. The current control and voltage control loop is then analyzed, modeled, and designed. The dynamic reactive power generation is also realized in the control system. The new PLL method for the grid frequency/voltage disturbance is also realized and demonstrate the validity of the detection and protection capability for the voltage/frequency disturbance.
At last, a brief conclusion is given in the Chapter 6 about each work. After that, future works on device packaging, system integration, innovation on inverter circuit, and standard compliance are discussed.<br>Ph. D.
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Nickoloff, Jacob L. "Layout generation and its application." Online access for everyone, 2007. http://www.dissertations.wsu.edu/Thesis/Summer2007/J_Nickoloff_081407.pdf.
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Kapoor, Shekhar. "Process level test generation for VHDL behavioral models." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-05022009-040753/.
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VIJAY, VIKAS. "A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.
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Koripalli, Venkat N. "An automatic test pattern generation technique for sequential circuits using scan applications /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1203571411&sid=16&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Alani, Alaa Fadhil. "A steady-state response test generation technique for mixed-signal integrated circuits." Thesis, Brunel University, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.316941.
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Thompson, David. "DESIGN OF EMBEDDED POWER SIGNATURE GENERATION CIRCUITS FOR INTERNET OF THINGS SECURITY." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2707.
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With the wide adoption of Internet of Things (IoT) in applications that involve sensitive information, the security of IoT devices is becoming an important concern. IoT devices face many challenges in securing information due to their low cost and computation constrains. To over come such challenges, different techniques have been developed. One such technique is power analysis. However, power analysis requires equipment that is often bulky, power hungry and expensive, making them unsuitable for many IoT applications. This thesis developed two energy signature capturing circuits that can be embedded into low dropout (LDO) voltage regulators. The first design targets analog LDO circuits and the second design is suitable for the newly emerged digital LDOs. Both circuits are designed and simulated using a commercial 130nm CMOS technology. To evaluate the effectiveness of the developed circuits, power traces collected from a wireless sensor device are used in circuit simulations. The results indicate that the developed circuits can detect different model wireless transmission as well as other abnormal operations.
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YANG, WEI. "AUTOMATIC HIGH-LEVEL MODEL GENERATION FOR ANALOG RF CIRCUITS IN VHDL-AMS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1109207864.
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Lee, Hyung Ki. "Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits." Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06062008-171759/.
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Bittner, Ray Albert. "Development and VLSI implementation of a new neural net generation method." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-12042009-020129/.
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Moore, Christopher Wayne. "Microfabricated Fuel Cells To Power Integrated Circuits." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7106.
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Microfabricated fuel cells have been designed and constructed on silicon integrated circuit wafers using many processes common in integrated circuit fabrication, including sputtering, polymer spin coating, reactive ion etching, and photolithography. Fuel delivery microchannels were made through the use of sacrificial polymers. The characteristics of different sacrificial polymers were studied to find the most suitable for this work. A polypropylene carbonate solution containing a photo-acid generator could be directly patterned with ultraviolet exposure and thermal decomposition. The material that would serve as the fuel cells proton exchange membrane (PEM) encapsulated the microchannels. Silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD) at relatively low temperatures exhibited material properties that made it suitable as a thin-film PEM in these devices. By adding phosphorous to the silicon dioxide recipe during deposition, a phosphosilicate glass was formed that had an increased ionic conductivity. Various polymers were tested for use as the PEM or in combination with oxide to form a composite PEM. While it did not work well alone, using Nafion on top of the glass layer to form a dual-layer PEM greatly enhanced the fuel cell performance, including yield and long-term reliability. Platinum and platinum/ruthenium catalyst layers were sputter deposited. Experiments were performed to find a range of thicknesses that resulted in porous layers allowing contact between reactants, catalyst, and the PEM. When using the deposited glasses, multiple layers of catalyst could be deposited between thin layers of the electrolyte, resulting in higher catalyst loading while maintaining porosity. The current and power output were greatly improved with these additional catalyst layers.
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Johnston, Robert Thomas. "A traffic generation algorithm for SDH digital cross-connects." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15723.
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