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Rozprawy doktorskie na temat „Heterogeneous acceleration”

Autor: Grafiati

Data publikacji: 3 czerwca 2025

Data aktualizacji: 31 lipca 2025

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1

Conti, Francesco <1988&gt. "Heterogeneous Architectures For Parallel Acceleration." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amsdottorato.unibo.it/7406/1/phd_thesis_AMS_wFRONTESPIZIO.pdf.

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To enable a new generation of digital computing applications, the greatest challenge is to provide a better level of energy efficiency (intended as the performance that a system can provide within a certain power budget) without giving up a systems's flexibility. This constraint applies to digital system across all scales, starting from ultra-low power implanted devices up to datacenters for high-performance computing and for the "cloud". In this thesis, we show that architectural heterogeneity is the key to provide this efficiency and to respond to many of the challenges of tomorrow's compu

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Conti, Francesco <1988&gt. "Heterogeneous Architectures For Parallel Acceleration." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amsdottorato.unibo.it/7406/.

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To enable a new generation of digital computing applications, the greatest challenge is to provide a better level of energy efficiency (intended as the performance that a system can provide within a certain power budget) without giving up a systems's flexibility. This constraint applies to digital system across all scales, starting from ultra-low power implanted devices up to datacenters for high-performance computing and for the "cloud". In this thesis, we show that architectural heterogeneity is the key to provide this efficiency and to respond to many of the challenges of tomorrow's compu

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Somers, Gregory W. "Acceleration of Block-Aware Matrix Factorization on Heterogeneous Platforms." Thesis, Université d'Ottawa / University of Ottawa, 2016. http://hdl.handle.net/10393/35128.

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Block-structured matrices arise in several contexts in circuit simulation problems. These matrices typically inherit the pattern of sparsity from the circuit connectivity. However, they are also characterized by dense spots or blocks. Direct factorization of those matrices has emerged as an attractive approach if the host memory is sufficiently large to store the block-structured matrix. The approach proposed in this thesis aims to accelerate the direct factorization of general block-structured matrices by leveraging the power of multiple OpenCL accelerators such as Graphical Processing Un

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Ferhatović, Nihad. "Analyzing the latency overheads of acceleration in heterogeneous systems." Thesis, Mälardalens högskola, Inbyggda system, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-55985.

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Importance of low-latency heterogeneous systems in today’s world is immeasurable, which was proven in the last few years especially with the appearance of pandemic Covid-19 by forcing us to use online streaming technologies. By tackling more complex tasks and problems, algorithms require computational power that often exceeds the capabilities of pieces of technology used for computational tasks. In order to solve this problem, different methods are used. Hardware acceleration as a type of process acceleration is one of the most used methods in the field of AI mostly because it easily out-perfo

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Pagani, Marco. "Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA Computing Platforms." Thesis, Lille 1, 2020. http://www.theses.fr/2020LIL1I016.

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Les architectures informatiques modernes pour les systèmes intégrés évoluent vers des plateformes de plus en plus hétérogènes, comprenant différents types de processeurs et d'accélérateurs. Cette évolution est entraînée par la nécessité de répondre à la demande croissante de capacité de calcul par les systèmes cyber-physiques modernes. Ces systèmes doivent acquérir et traiter de grandes quantités de données, provenant de différents capteurs, afin d'exécuter les tâches de contrôle et de surveillance nécessaires. Ces exigences se traduisent par la nécessité d'exécuter des charges de calcul compl

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Xue, Weicheng. "CPU/GPU Code Acceleration on Heterogeneous Systems and Code Verification for CFD Applications." Diss., Virginia Tech, 2021. http://hdl.handle.net/10919/102073.

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Computational Fluid Dynamics (CFD) applications usually involve intensive computations, which can be accelerated through using open accelerators, especially GPUs due to their common use in the scientific computing community. In addition to code acceleration, it is important to ensure that the code and algorithm are implemented numerically correctly, which is called code verification. This dissertation focuses on accelerating research CFD codes on multi-CPUs/GPUs using MPI and OpenACC, as well as the code verification for turbulence model implementation using the method of manufactured solution

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Schultek, Brian Robert. "Design and Implementation of the Heterogeneous Computing Device Management Architecture." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1417801414.

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Bijanapalli, Chakri Ramakrishna. "Enabling the use of Heterogeneous Computing for Bioinformatics." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23866.

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The huge amount of information in the encoded sequence of DNA and increasing interest in uncovering new discoveries has spurred interest in accelerating the DNA sequencing and alignment processes. The use of heterogeneous systems, that use different types of computational units, has seen a new light in high performance computing in recent years; However expertise in multiple domains and skills required to program these systems is causing an hindrance to bioinformaticians in rapidly deploying their applications into these heterogeneous systems. This work attempts to make an heterogeneous system

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Chen, Chong. "Acceleration of Computer Based Simulation, Image Processing, and Data Analysis Using Computer Clusters with Heterogeneous Accelerators." University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton148036732102682.

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Winter, Frank [Verfasser], and Andreas [Akademischer Betreuer] Schaefer. "Investigation of hadron matter using lattice QCD and implementation of lattice QCD applications on heterogeneous multicore acceleration processors / Frank Winter. Betreuer: Andreas Schaefer." Regensburg : Universitätsbibliothek Regensburg, 2011. http://d-nb.info/1023361698/34.

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Newmeyer, Luke Oliver. "Efficient FPGA SoC Processing Design for a Small UAV Radar." BYU ScholarsArchive, 2018. https://scholarsarchive.byu.edu/etd/7057.

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Modern radar technology relies heavily on digital signal processing. As radar technology pushes the boundaries of miniaturization, computational systems must be developed to support the processing demand. One particular application for small radar technology is in modern drone systems. Many drone applications are currently inhibited by safety concerns of autonomous vehicles navigating shared airspace. Research in radar based Detect and Avoid (DAA) attempts to address these concerns by using radar to detect nearby aircraft and choosing an alternative flight path. Implementation of radar on smal

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Tan, Shawn Ser Ngiap. "Design and development of a heterogeneous hardware search accelerator." Thesis, University of Cambridge, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.608686.

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Uliana, David Christopher. "FPGA-Based Accelerator Development for Non-Engineers." Thesis, Virginia Tech, 2014. http://hdl.handle.net/10919/78091.

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In today's world of big-data computing, access to massive, complex data sets has reached an unprecedented level, and the task of intelligently processing such data into useful information has become a growing concern to the high-performance computing community. However, domain experts, who are the brains behind this processing, typically lack the skills required to build FPGA-based hardware accelerators ideal for their applications, as traditional development flows targeting such hardware require digital design expertise. This work proposes a usable, end-to-end accelerator development methodol

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P, Joseph Iype. "Accelerating Java on Embedded GPU." Thèse, Université d'Ottawa / University of Ottawa, 2014. http://hdl.handle.net/10393/30684.

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Multicore CPUs (Central Processing Units) and GPUs (Graphics Processing Units) are omnipresent in today’s market-leading smartphones and tablets. With CPUs and GPUs getting more complex, maximizing hardware utilization is becoming problematic. The challenges faced in GPGPU (General Purpose computing using GPU) computing on embedded platforms are different from their desktop counterparts due to their memory and computational limitations. This thesis evaluates the performance and energy efficiency achieved by offloading Java applications to an embedded GPU. The existing solutions in literature a

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15

Prasad, Rohit <1991&gt. "Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2022. http://amsdottorato.unibo.it/9983/1/PhD_thesis__20_January_2022_.pdf.

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There is an ever-increasing demand for energy efficiency (EE) in rapidly evolving Internet-of-Things end nodes. This pushes researchers and engineers to develop solutions that provide both Application-Specific Integrated Circuit-like EE and Field-Programmable Gate Array-like flexibility. One such solution is Coarse Grain Reconfigurable Array (CGRA). Over the past decades, CGRAs have evolved and are competing to become mainstream hardware accelerators, especially for accelerating Digital Signal Processing (DSP) applications. Due to the over-specialization of computing architectures, the focus i

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Chu, Ching-Hsiang. "Accelerator-enabled Communication Middleware for Large-scale Heterogeneous HPC Systems with Modern Interconnects." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1595451131152.

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Hartley, Timothy D. R. "Accelerating Component-Based Dataflow Middleware with Adaptivity and Heterogeneity." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1306839406.

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Gilbert, John Nicholas. "Accelerating a Coupled SPH-FEM Solver through Heterogeneous Computing for use in Fluid-Structure Interaction Problems." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/52924.

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This work presents a partitioned approach to simulating free-surface flow interaction with hyper-elastic structures in which a smoothed particle hydrodynamics (SPH) solver is coupled with a finite-element (FEM) solver. SPH is a mesh-free, Lagrangian numerical technique frequently employed to study physical phenomena involving large deformations, such as fragmentation or breaking waves. As a mesh-free Lagrangian method, SPH makes an attractive alternative to traditional grid-based methods for modeling free-surface flows and/or problems with rapid deformations where frequent re-meshing and addit

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Ringenson, Josefin. "Efficiency of CNN on Heterogeneous Processing Devices." Thesis, Linköpings universitet, Programvara och system, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-155034.

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In the development of advanced driver assistance systems, computer vision problemsneed to be optimized to run efficiently on embedded platforms. Convolutional neural network(CNN) accelerators have proven to be very efficient for embedded camera platforms,such as the ones used for automotive vision systems. Therefore, the focus of this thesisis to evaluate the efficiency of a CNN on a future embedded heterogeneous processingdevice. The memory size in an embedded system is often very limited, and it is necessary todivide the input into multiple tiles. In addition, there are power and speed const

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Bhatnagar, Ashish. "Accelerating a Movie Recommender System Using VirtualCL on a Heterogeneous GPU Cluster : Big Data Analysis Using Distributed Accelerators." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175775.

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Present day market offers a large number of movies which overwhelm people with choices. In order to quickly navigate through all the possible movies and find the interesting ones, the user can take advantage of recommender systems for movies. This thesis studies a movie recommender system which uses image processing and computer vision algorithms. The amount of time taken to analyze movies using these computation intensive algorithms is in the order of years. However, exploiting parallel nature of these algorithms using GPUs (Graphics Processing Unit) can help reduce the time many-folds. The p

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21

Tarakji, Ayman Verfasser], Rainer [Akademischer Betreuer] Leupers, and Gerd [Akademischer Betreuer] [Ascheid. "Design and investigation of scheduling mechanisms on accelerator-based heterogeneous computing systems / Ayman Tarakji ; Rainer Leupers, Gerd Ascheid." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/119373486X/34.

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Tarakji, Ayman [Verfasser], Rainer Akademischer Betreuer] Leupers, and Gerd [Akademischer Betreuer] [Ascheid. "Design and investigation of scheduling mechanisms on accelerator-based heterogeneous computing systems / Ayman Tarakji ; Rainer Leupers, Gerd Ascheid." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/119373486X/34.

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Öhberg, Tomas. "Auto-tuning Hybrid CPU-GPU Execution of Algorithmic Skeletons in SkePU." Thesis, Linköpings universitet, Programvara och system, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-149605.

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The trend in computer architectures has for several years been heterogeneous systems consisting of a regular CPU and at least one additional, specialized processing unit, such as a GPU.The different characteristics of the processing units and the requirement of multiple tools and programming languages makes programming of such systems a challenging task. Although there exist tools for programming each processing unit, utilizing the full potential of a heterogeneous computer still requires specialized implementations involving multiple frameworks and hand-tuning of parameters.To fully exploit t

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Solis, Vasquez Leonardo [Verfasser], Andreas [Akademischer Betreuer] Koch, and Christian [Akademischer Betreuer] Plessl. "Accelerating Molecular Docking by Parallelized Heterogeneous Computing - A Case Study of Performance, Quality of Results, and Energy-Efficiency using CPUs, GPUs, and FPGAs / Leonardo Solis Vasquez ; Andreas Koch, Christian Plessl." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2019. http://d-nb.info/1201086671/34.

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Huang, Che-Lin, and 黃則霖. "Heterogeneous Computing hardware acceleration techniques o." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/heu6hz.

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碩士<br>國立臺灣科技大學<br>高階科技研發碩士學位學程<br>106<br>Abstract Major server CPU (Central Processing Processor) processor nowadays are capable of equipping more internal processor cores, greater than ever internal cache and memory controller channels. However, with such highly integration of the micro-processor evolution, the users see only limited performance gains but much more burden of increasing processor TDP (Thermal Design Power), heat dissipation and cooling requirements. It is observed that evolution course of semiconductor process has reached to where Moore's Law called out decades ago that transi

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Huang, Taixiang, and 黃泰翔. "Acceleration of SURF Algorithm on a Heterogeneous Dual-Core Embedded Platform." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/64962221890646305879.

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碩士<br>國立臺北大學<br>電機工程研究所<br>99<br>In the field of computer vision, the feature point extraction method is a very important investigation that can be applied to image localization, such as object tracking, recognition and augmented reality, etc. The rapid development of the embedded platform is an opportunity to implement an applications of mobile image localization. The feature points can be extracted from different angles, distances, and illumination. Therefore, the feature descriptor with relatively invariant to changes in orientation, scale, brightness, and contrast is important. At first, w

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Joao, José Alberto. "Bottleneck identification and acceleration in multithreaded applications." Thesis, 2014. http://hdl.handle.net/2152/28383.

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When parallel applications do not fully utilize the cores that are available to them they are missing the opportunity to have better performance. Sometimes threads have to wait for other threads. I call the code segments that make other threads wait bottlenecks. Examples of these bottlenecks include contended critical sections, threads arriving late to barriers and the slowest stage of a pipelined program. Other times all threads are running but some of them, which I call lagging threads, are making less progress, setting the stage to become bottlenecks. My thesis proposes identifying the code

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Tseng, Tai-Hua, and 曾太華. "Adaptive Ray Tracing Acceleration on Heterogeneous Computing Architecture based on Branch Divergence Profiles." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/53243114561684733998.

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碩士<br>國立交通大學<br>資訊科學與工程研究所<br>102<br>Heterogeneous computing achieves high performance and high power efficiency by exploiting high parallelism and special type of computation (such as SIMD operations) available in applications on best fit computation devices. For example, massive and regular SIMD operations can be more efficiently computed on GPU. However, the performance of a heterogeneous program can be degraded when the portion assigned to GPU encounters high branch divergence. It is due to the fact that threads running in locksteps take different control flow paths, and the SIMD nature of

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Reese, Jill Paula. "Examining the significance of advective acceleration to single-phase flow through heterogeneous porous media." 2006. http://www.lib.ncsu.edu/theses/available/etd-11012006-133641/unrestricted/etd.pdf.

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(10971108), Yangjie Li. "REACTION ACCELERATION AT INTERFACES STUDIED BY MASS SPECTROMETRY." Thesis, 2021.

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<p>Various organic reactions, including important synthetic reactions involving C–C, C–N, and C–O bond formation as well as reactions of biomolecules, are known to be accelerated when the reagents are present in confined volumes such as sprayed or levitated microdroplets or thin films. This phenomenon of reaction acceleration and the key role of interfaces played in it are of intrinsic interest and potentially of practical value as a simple, rapid method of performing small-scale synthesis. This dissertation has three focusing subtopics in the field of reaction acceleration: (1) application of

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Madill, Christopher Andre. "A Heterogeneous, Purpose Built Computer Architecture For Accelerating Biomolecular Simulation." Thesis, 2011. http://hdl.handle.net/1807/27589.

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Molecular dynamics (MD) is a powerful computer simulation technique providing atomistic resolution across a broad range of time scales. In the past four decades, researchers have harnessed the exponential growth in computer power and applied it to the simulation of diverse molecular systems. Although MD simulations are playing an increasingly important role in biomedical research, sampling limitations imposed by both hardware and software constraints establish a \textit{de facto} upper bound on the size and length of MD trajectories. While simulations are currently approaching the hundred-thou

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Tsai, Cheng-Ming, and 蔡政銘. "On Accelerating Multi-Layered Heterogeneous Network Representation Learning via Landmark Selection." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/4fm32b.

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碩士<br>國立交通大學<br>電機工程學系<br>106<br>Network representation, embedding large information networks into low dimensional vector spaces, has been widely studied in homogeneous networks. Deriving the latent representations of the information networks can apply to data analysis methods such as visualizing the entire network, classifying nodes into their belonging classes, and detecting communities. Representation serves a crucial role in those data analyzing tasks. Heterogeneous networks, containing more hidden features not available in homogeneous networks, however, are less studied. One straightforwa

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Suleman, Muhammad Aater. "An asymmetric multi-core architecture for efficiently accelerating critical paths in multithreaded programs." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-05-1407.

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Extracting high-performance from Chip Multiprocessors (CMPs) requires that the application be parallelized i.e., divided into threads which execute concurrently on multiple cores. To save programmer effort, difficult to parallelize program portions are often left as serial. We show that common serial portions, i.e., non-parallel kernels, critical sections, and limiter stages in a pipeline, become the critical path of the program when the number of cores increases, thereby limiting performance and scalability. We propose that instead of burdening the software programmers with the task of shorte

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Pereira, André Martins. "Efficient processing of ATLAS events analysis in homogeneous and heterogeneous platforms with accelerator devices." Master's thesis, 2013. http://hdl.handle.net/1822/28042.

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Dissertação de mestrado em Engenharia Informática<br>Most event data analysis tasks in the ATLAS project require both intensive data access and processing, where some tasks are typically I/O bound while others are compute bound. This dissertation work mainly focus improving the code efficiency of the compute bound stages of the ATLAS detector data analysis, complementing a parallel dissertation work that addresses the I/O bound issues. The main goal of the work was to design, implement, validate and evaluate an improved and more robust data analysis task, originally developed by the LIP resea

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Chen, Chien-Chih, and 陳建志. "A Full-system Heterogeneous Multicore Simulation Platform and Accelerating Architecture-Level Simulation by Sampling Simulation." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/7j27pf.

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Liang, Jia-Sheng, and 梁嘉勝. "Based on Hadoop Platform-Accelerating Query to Process Big Data Combined with Heterogeneous Databases and Hive." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/222554.

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碩士<br>國立東華大學<br>資訊工程學系<br>101<br>Cloud Computing has been a topic issue in the field of research in recent years. Nowadays, the environment of Internet has become more popular and powerful. Information can be gotten on any mobile devices (e.g., smartphone, laptop and tablet) through the web services easily. Parallelization in computing and data storage increases the performance of computing and capacity of fault-tolerant. These significant features speed up the development of Cloud Computing service. Besides, more and more computing power and storage provided by cloud platforms are required to

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Solis, Vasquez Leonardo. "Accelerating Molecular Docking by Parallelized Heterogeneous Computing - A Case Study of Performance, Quality of Results, and Energy-Efficiency using CPUs, GPUs, and FPGAs." Phd thesis, 2019. https://tuprints.ulb.tu-darmstadt.de/9288/1/20191130_phdthesis_lsv.pdf.

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Molecular Docking (MD) is a key tool in computer-aided drug design that aims to predict the binding pose between a small molecule and a macromolecular target. At its core, MD calculates the strength of possible binding poses, and searches for the energetically-stronger ones among those generated during simulation. Automatic Docking (AutoDock) is a widely-used MD code that employs a physics-based scoring function to quantify the binding strength. AutoDock also uses a Lamarckian Genetic Algorithm (LGA), and in turn, the Solis-Wets method, as a local-search algorithm, in order to find strong inte

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