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Gotowe bibliografie tematyczne / Integrated circuits Very large scale integration Design and construction Data processing / Rozprawy doktorskie

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Rozprawy doktorskie na temat „Integrated circuits Very large scale integration Design and construction Data processing”

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Data publikacji: 4 czerwca 2021

Data aktualizacji: 30 stycznia 2023

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1

Ivanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.

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Kim, Kwanghyun. "An interactive design rule checker for integrated circuit layout." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/50034.

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An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name ar

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3

Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.

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Kim, Kwanghyun. "An expert system for self-testable hardware design." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.

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BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a searc

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5

Zhang, Mingyang 1981. "Macromodeling and simulation of linear components characterized by measured parameters." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=112589.

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Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distri

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6

Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.

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The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expen

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7

Tonkin, Bruce A. (Bruce Archibald). "A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin." 1990. http://hdl.handle.net/2440/19215.

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Bibliography: leaves 233-259<br>xii, 259 leaves : ill ; 30 cm.<br>Title page, contents and abstract only. The complete thesis in print form is available from the University Library.<br>Thesis (Ph.D.)--University of Adelaide, 1991

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Tonkin, Bruce A. (Bruce Archibald). "A parallel processing architecture for CAD of integrated circuits / Bruce A. Tonkin." Thesis, 1990. http://hdl.handle.net/2440/19215.

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9

Noonan, J. A. (John Anthony). "Investigations into methods and analysis of computer aided design of VLSI circuits." 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensn817.pdf.

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10

"Design and test for timing uncertainty in VLSI circuits." 2012. http://library.cuhk.edu.hk/record=b5549444.

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由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。<br>為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局

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11

"Efficient alternative wiring techniques and applications." 2001. http://library.cuhk.edu.hk/record=b5890816.

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Sze, Chin Ngai.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.<br>Includes bibliographical references (leaves 80-84) and index.<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgments --- p.iii<br>Curriculum Vitae --- p.iv<br>List of Figures --- p.ix<br>List of Tables --- p.xii<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivation and Aims --- p.1<br>Chapter 1.2 --- Contribution --- p.8<br>Chapter 1.3 --- Organization of Dissertation --- p.10<br>Chapter 2 --- Definitions and Notations --- p.11<br>Chapter 3 --- Literature Review --- p.15

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12

Merani, Lalit T. "A micro data flow (MDF) : a data flow approach to self-timed VLSI system design for DSP." Thesis, 1993. http://hdl.handle.net/1957/36301.

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Synchronization is one of the important issues in digital system design. While other approaches have been intriguing, up until now a globally clocked timing discipline has been the dominant design philosophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. VLSI promises great processing power at low cost. This increase in computation power has been obtained by scaling the digital IC process. But as this scaling continues, it is doubtful that the advantages of faster devices can be fully exploited. This is because the c

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13

"VLSI implementation of discrete cosine transform using a new asynchronous pipelined architecture." 2002. http://library.cuhk.edu.hk/record=b5891233.

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Lee Chi-wai.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.<br>Includes bibliographical references (leaves 191-196).<br>Abstracts in English and Chinese.<br>Abstract of this thesis entitled: --- p.i<br>摘要 --- p.iii<br>Acknowledgements --- p.v<br>Table of Contents --- p.vii<br>List of Tables --- p.x<br>List of Figures --- p.xi<br>Chapter Chapter1 --- Introduction --- p.1<br>Chapter 1.1 --- Synchronous Design --- p.1<br>Chapter 1.2 --- Asynchronous Design --- p.2<br>Chapter 1.3 --- Discrete Cosine Transform --- p.4<br>Chapter 1.4 --- Motivation --- p.5<br>Chapter 1.5 ---

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14

"An ICT image processing chip based on fast computation algorithm and self-timed circuit technique." 1997. http://library.cuhk.edu.hk/record=b5889190.

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by Johnson, Tin-Chak Pang.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.<br>Includes bibliographical references.<br>Acknowledgments<br>Abstract<br>List of figures<br>List of tables<br>Chapter 1. --- Introduction --- p.1-1<br>Chapter 1.1 --- Introduction --- p.1-1<br>Chapter 1.2 --- Introduction to asynchronous system --- p.1-5<br>Chapter 1.2.1 --- Motivation --- p.1-5<br>Chapter 1.2.2 --- Hazards --- p.1-7<br>Chapter 1.2.3 --- Classes of Asynchronous circuits --- p.1-8<br>Chapter 1.3 --- Introduction to Transform Coding --- p.1-9<br>Chapter 1.4 --- Organization of the Thes

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15

al-Sarʻāwī, Said Fares. "Design techniques for low power mixed analog-digital circuits with application to smart wireless systems." 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.

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Includes bibliographical references (leaves 277-284) Presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology.

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16

Nguyen, Xuan Thong 1965. "Smart VLSI micro-sensors for velocity estimation inspired by insect vision / by Xuan Thong Nguyen." 1996. http://hdl.handle.net/2440/18756.

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Bibliography: leaves 188-203.<br>xxii, 203 leaves : ill. ; 30 cm.<br>Title page, contents and abstract only. The complete thesis in print form is available from the University Library.<br>In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996

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Nguyen, Xuan Thong 1965. "Smart VLSI micro-sensors for velocity estimation inspired by insect vision / by Xuan Thong Nguyen." Thesis, 1996. http://hdl.handle.net/2440/18756.

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Bibliography: leaves 188-203.<br>xxii, 203 leaves : ill. ; 30 cm.<br>In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996

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