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Data publikacji: 4 czerwca 2021

Data aktualizacji: 30 lipca 2024

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1

Hong, Won-kook. "Single layer routing : mapping topological to geometric solutions." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66030.

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2

Matsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.

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3

Jafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.

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4

Voranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.

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5

Dagenais, Michel R. "Timing analysis for MOSFETS, an integrated approach." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75459.

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Timing and electrical verification is an essential part of the design of VLSI digital MOS circuits. It consists of determining the maximum operating frequency of a circuit, and verifying that the circuit will always produce the expected logical behavior at or under this frequency. This complex task requires considerable computer and human resources.<br>The classical simulation approach cannot be used to insure the timing and electrical correctness of the large circuits that are now being designed. The huge number of possible states in large circuits renders this method impractical. Worst-case

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6

Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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7

Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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8

Davis, Jeffrey Alan. "A hierarchy of interconnect limits and opportunities for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15803.

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9

Anbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.<br>Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.

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10

Ivanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.

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11

Zhao, Wenhui, and 趙文慧. "Efficient circuit simulation via adaptive moment matching and matrix exponential techniques." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/197488.

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This dissertation presents two efficient circuit simulation techniques for very large scale integrated (VLSI) circuits. Model order reduction (MOR) plays a significant role in VLSI circuit simulation as nowadays the system model may contain millions of equations or variables. MOR is needed to reduce the order of the original system to allow the simulation to be performed with an acceptable amount of time, reasonable storage and reliable accuracy. Multi-point moment matching is one of the state-of-the-art methods for MOR. However, the moment order and expansion points are usually selected in a

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12

Hum, Herbert Hing-Jing. "A linear unification processor /." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63790.

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13

Chu, Chung-kwan, and 朱頌君. "Computationally efficient passivity-preserving model order reduction algorithms in VLSI modeling." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B38719551.

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14

Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.

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15

Narayanan, Prakash. "Analytical modeling and simulation of bicmos for VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42199.

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Interest in BiCMOS technology has been generated recently due to the potential advantages this technology offers over conventional CMOS which enjoys widespread use in today’s semiconductor industry. However, before BiCMOS can be readily adopted by the VLSI community, an understanding of the design issues and tradeoffs involved when utilizing it, must be achieved. The principal focus of this research is to move towards such an understanding through the means of analytical modeling and circuit simulation using PSPICE [1]. The device chosen for the modeling approach is the basic BiCMOS Invertin

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16

張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.

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17

Wilson, Denise M. "Analog VLSI architecture for chemical sensing microsystems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13322.

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18

Peckel, Marcos David. "A MOS delay model for switch-level simulation /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65990.

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19

Panda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.

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20

KRISHT, MUHAMMED HUSSEIN, and MUHAMMED HUSSEIN KRISHT. "LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS." Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/187983.

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Advances in microlithography, dry etching, scaling of devices, ion-implantation, process control, and computer aid design brought the integrated circuit technology into the era of VLSI circuits. Those circuits are characterized by high packing density, improved performance, complex circuits, and large chip sizes. Interconnects and their spacing dominate the chip area of VLSI circuits and they degrade the circuit performance through the unacceptable high time delays. Multilayer metallization enables shorter interconnects, ease of design and yet higher packing density for VLSI circuits. It was s

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21

Karunaratne, Maddumage Don Gamini. "An intelligent function level backward state justification search for ATPG." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184921.

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This dissertation describes an innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process. Given the absence of a stored fault an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propogation search can be successfully guided through state space from the present sta

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22

Howells, Michael C. "A cluster-proof approach to yield enhancement of large area binary tree architectures /." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66194.

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23

Geller, Ronnie Dee. "A VLSI architecture for a neurocomputer using higher-order predicates." Full text open access at:, 1987. http://content.ohsu.edu/u?/etd,137.

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24

Al-Mahmood, Saiyid Jami Islah Ahmad. "A distributed design rule checker for VLSI layouts." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-11012008-063423/.

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25

Tyagi, Dhawal. "TENOR : an ATPG for transition faults in combinational circuits /." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06302009-040525/.

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26

Kelley, Brian T. "VLSI computing architectures for high speed seismc migration." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13919.

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27

Bragg, Julian Alexander. "A biomorphic analog VLSI implementation of a mammalian motor unit." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20693.

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28

Tan, Chong Guan. "Another approach to PLA folding." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.

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29

高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.

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30

Rasafar, Hamid 1954. "THE HIGH FREQUENCY AND TEMPERATURE DEPENDENCE OF DIELECTRIC PROPERTIES OF PRINTED CIRCUIT BOARD MATERIALS." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276509.

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New VLSI and VHSIC devices require increased performance from electronic packages. The major challenge that must be met in materials/process development for high complexity and high speed integrated circuits is the processing of even larger amounts of signals with low propagation delay. Hence, materials with low dielectric constant and low dissipation factor are being sought. In this investigation the dielectric properties of the most commonly used composite materials for printed circuit boards, Teflon-glass and Epoxy-glass, were measured in the frequency and temperature intervals of 100 HZ-1

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31

Chen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.

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This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little

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32

Holland, Kenneth Chris. "Probability of latching single event upset errors in VLSI circuits." Thesis, Virginia Tech, 1991. http://hdl.handle.net/10919/41980.

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The ability of radiation to cause transient faults in space borne as well as ground based computers is well known. with the density of VLSI circuits increasing every year, the probability of an upset by radiation is becoming more likely. However, research in this area has matured over the last decade, and the mechanisms which cause such faults are better understood. This understanding enables us to propose ideas to eliminate or lessen the effects of radiation on VLSI circuits. <p>Most of the research to date has concentrated on the effect of transient faults on flip-flops rather than combinati

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33

Liu, Yansong, and 劉岩松. "Passivity checking and enforcement in VLSI model reduction exercise." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290690.

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34

Lee, Hoi-Ming Bonny 1961. "The evaluation of the PODEM algorithm as a mechanism to generate goal states for a sequential circuit test search." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276730.

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In a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used to describe the behavior of a sequential circuit. Next, SCIRTSS is used to generate the test vectors. Several circuits are evaluated and experimental results are compared with data from a previous version of SCIRTSS which was implemented with the D-Algorithm. Depending on the number of reconvergent

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35

Tang, Maolin. "Intelligent approaches to VLSI routing." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2000. https://ro.ecu.edu.au/theses/1375.

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Very Large Scale Integrated-circuit (VLSI) routing involves many large-size and complex problems and most of them have been shown to be NP-hard or NP-complete. As a result, conventional approaches, which have been successfully used to handle relatively small-size routing problems, are not suitable to be used in tackling large-size routing problems because they lead to 'combinatorial explosion' in search space. Hence, there is a need for exploring more efficient routing approaches to be incorporated into today's VLSI routing system. This thesis strives to use intelligent approaches, including s

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36

Whipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.

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An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are

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37

Khordoc, Karim. "A MOS switch-level simulator with delay calculation /." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65461.

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38

Bishop, Gregory Raymond H. ""On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems" /." Title page, contents and abstract only, 1993. http://web4.library.adelaide.edu.au/theses/09PH/09phb6222.pdf.

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39

Kosaraju, Chakravarthy S. "A set of behavioral modeling primitives." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41989.

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<p>Modeling is an essential step in the design of digital circuits [71. The coding of behavioral models for complex devices is a labor intensive task. Even with the use of a to01like the "Modeler's Assistant" [4}, the development of behavioral models is time consuming and labor intensive. The use of re-usable code along with a tool like the Modeler's Assistant can speed up model development. This thesis defines a set of higher level primitives which can be used for this purpose. These primitives are built as a macro library into the tool. The Modeler's Assistant together with the modeling prim

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40

Cho, Chang H. "A formal model for behavioral test generation." Diss., This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06062008-170406/.

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41

Deng, Chaodan. "Process development for si-based nanostructures using pulsed UV laser induced epitaxy." Full text open access at:, 1995. http://content.ohsu.edu/u?/etd,206.

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42

Moini, Alireza. "Synthesis of biological vision models using analog VLSI /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm712.pdf.

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43

Tan, Wei-Siong. "A VLSI parallel processor structure for scientific computing." Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/13455.

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44

Patel, Girish N. "A neuromorphic architecture for modeling intersegmental coordination." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13528.

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45

Gordon, Christal. "An adaptive floating-gate network using action-potential signaling." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15683.

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46

Măndoiu, Ion I. "Approximation algorithms for VLSI routing." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/9128.

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47

梁迅中 and Shun-chung Leung. "Silicon compiler for bit-serial signal processing architecture with automatic time alignment." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1987. http://hub.hku.hk/bib/B31207741.

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48

袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.

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49

Ma, Min. "Model order reduction for efficient modeling and simulation of interconnect networks." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103269.

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As operating frequency increases and device sizes shrink, the complexity of current state-of-the-art designs has increased dramatically. One of the main contributors to this complexity is high speed interconnects. At high frequencies, interconnects become dominant contributors to signal degradation, and their effects such as delays, reflections, and crosstalk must be accurately simulated. Time domain analysis of such structures is however very difficult because, at high frequencies, they must be modeled as distributed transmission lines which, after discretization, result in very large network

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50

Shope, David Allen 1958. "Thermal characterization of VLSI packaging." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276686.

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With electronic packaging becoming more complex, simple hand methods to model the thermal performance of the package are insufficient. As computer aided modeling methods came into use, a test system was developed to verify the predictions produced by such modeling methods. The test system is evaluated for operation and performance. Further, the premise of this type of test (the accurate calibration of packaged temperature-sensitive-parameter devices can be done) is investigated using a series of comparative tests. From this information, causes of possible/probable errors in calibration are ide

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