Gotowe bibliografie tematyczne / Itanium

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  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
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Gotowa bibliografia na temat „Itanium”

Autor: Grafiati
Data publikacji: 4 czerwca 2021
Data aktualizacji: 29 stycznia 2023

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Artykuły w czasopismach na temat "Itanium"

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Šetar, Domen. "IZUM itanium workshop." Organizacija znanja 8, no. 2 (2003): 112–13. http://dx.doi.org/10.3359/oz0302112.

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Sharangpani, H., and H. Arora. "Itanium processor microarchitecture." IEEE Micro 20, no. 5 (2000): 24–43. http://dx.doi.org/10.1109/40.877948.

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Greer, Bruce, John Harrison, Greg Henry, Wei Li, and Peter Tang. "Scientific Computing on the Itanium® Processor." Scientific Programming 10, no. 4 (2002): 329–37. http://dx.doi.org/10.1155/2002/193478.

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The 64-bit Intel® Itanium® architecture is designed for high-performance scientific and enterprise computing, and the Itanium processor is its first silicon implementation. Features such as extensive arithmetic support, predication, speculation, and explicit parallelism can be used to provide a sound infrastructure for supercomputing. A large number of high-performance computer companies are offering Itanium® -based systems, some capable of peak performance exceeding 50 GFLOPS. In this paper we give an overview of the most relevant architectural features and provide illustrations of how these features are used in both low-level and high-level support for scientific and engineering computing, including transcendental functions and linear algebra kernels.
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Crawford, J. "Introducing the itanium processors." IEEE Micro 20, no. 5 (September 2000): 9–11. http://dx.doi.org/10.1109/mm.2000.877946.

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McNairy, C., and D. Soltis. "Itanium 2 processor microarchitecture." IEEE Micro 23, no. 2 (March 2003): 44–55. http://dx.doi.org/10.1109/mm.2003.1196114.

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Fumio Aono and Masayuke Kimura. "The AzusA 16-way itanium server." IEEE Micro 20, no. 5 (2000): 54–60. http://dx.doi.org/10.1109/40.877950.

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Samaras, W. A., N. Cherukuri, and S. Venkataraman. "The IA-64 Itanium processor cartridge." IEEE Micro 21, no. 1 (2001): 82–89. http://dx.doi.org/10.1109/40.903064.

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Snavely, N., S. Debray, and G. R. Andrews. "Unpredication, unscheduling, unspeculation: reverse engineering Itanium executables." IEEE Transactions on Software Engineering 31, no. 2 (February 2005): 99–115. http://dx.doi.org/10.1109/tse.2005.27.

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Naffziger, S. D., G. Colon-Bonet, T. Fischer, R. Riedlinger, T. J. Sullivan, and T. Grutkowski. "The implementation of the Itanium 2 microprocessor." IEEE Journal of Solid-State Circuits 37, no. 11 (November 2002): 1448–60. http://dx.doi.org/10.1109/jssc.2002.803943.

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Iikbahar, A., S. Venkataraman, and H. Muljono. "Itanium/sup TM/ Processor system bus design." IEEE Journal of Solid-State Circuits 36, no. 10 (2001): 1565–73. http://dx.doi.org/10.1109/4.953486.

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Rozprawy doktorskie na temat "Itanium"

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Sharma, Saurabh. "WELD FOR ITANIUM PROCESSOR." NCSU, 2002. http://www.lib.ncsu.edu/theses/available/etd-11182002-120028/.

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This dissertation extends a WELD for Itanium processors. Emre Özer presented WELD architecture in his Ph.D. thesis. WELD integrates multithreading support into an Itanium processor to hide run-time latency effects that cannot be determined by the compiler. Also, it proposes a hardware technique called operation welding that merges operations from different threads to utilize the hardware resources. Hardware contexts such as program counters and the fetch units are duplicated to support for multithreading. The experimental results show that Dual-thread WELD attains a maximum of 11% speedup as compared to single-threaded Itanium architecture while still maintaining the hardware simplicity of the EPIC architecture.
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Bjerke, Håvard K. F. "HPC Virtualization with Xen on Itanium." Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9263.

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<p>The Xen Virtual Machine Monitor has proven to achieve higher efficiency in virtualizing the x86 architecture than competing x86 virtualization technologies. This makes virtualization on the x86 platform more feasible in High-Performance and mainframe computing, where virtualization can offer attractive solutions for managing resources between users. Virtualization is also attractive on the Itanium architecture. Future x86 and Itanium computer architectures include extensions which make virtualization more efficient. Moving to virtualizing resources through Xen may ready computer centers for the possibilities offered by these extensions. The Itanium architecture is ``uncooperative'' in terms of virtualization. Privilege-sensitive instructions make full virtualization inefficient and impose the need for para-virtualization. Para-virtualizing Linux involves changing certain native operations in the guest kernel in order to adapt it to the Xen virtual architecture. Minimum para-virtualizing impact on Linux is achieved by, instead of replacing illegal instructions, trapping them by the hypervisor, which then emulates them. Transparent para-virtualization allows the same Linux kernel binary to run on top of Xen and on physical hardware. Itanium region registers allow more graceful distribution of memory between guest operating systems, while not disturbing the Translation Lookaside Buffer. The Extensible Firmware Interface provides a standardized interface to hardware functions, and is easier to virtualize than legacy hardware interfaces. The overhead of running para-virtualized Linux on Itanium is reasonably small and measured to be around 4.9 %. Also, the overhead of running transparently para-virtualized Linux on physical hardware is reasonably small compared to non-virtualized Linux.</p>
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Wienand, Ian Raymond Computer Science &amp Engineering Faculty of Engineering UNSW. "Transparent large-page support for Itanium linux." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41021.

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The abstraction provided by virtual memory is central to the operation of modern operating systems. Making the most efficient use of the available translation hardware is critical to achieving high performance. The multiple page-size support provided by almost all architectures promises considerable benefits but poses a number of implementation challenges. This thesis presents a minimally-invasive approach to transparent multiple page-size support for Itanium Linux. In particular, it examines the interaction between supporting large pages and Itanium's two inbuilt hardware page-table walkers; one being a virtual linear page-table with limited support for storing different page-size translations and the other a more flexible but higher overhead hash table based translation cache. Compared to a single-page-size kernel, a range of benchmarks show performance improvements when multiple page-sizes are available, generally large working sets that stress the TLB. However, other benchmarks are negatively impacted. Analysis shows that the increased TLB coverage, resulting from the use of large pages, frequently does not reduce TLB miss rates sufficiently to make up for the increased cost of TLB reloads. These results, which are specific to the Itanium architecture, suggest that large-page support for Itanium Linux is best enabled selectively with insight into application behaviour.
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Tayeb, Jamel. "Optimisation des performances et de la consommation de puissance électrique pour architecture Intel Itanium/EPIC." Valenciennes, 2008. http://ged.univ-valenciennes.fr/nuxeo/site/esupversions/9eed6aef-dfaf-4a17-883f-d217a1d9a000.

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Cette thèse propose, dans sa première partie, d’étendre l’architecture EPIC des processeurs de la famille Itanium par l’ajout d’une pile matérielle. L’idée principale est qu’il est possible de combler l’écart de performance entre une architecture généraliste et les circuits spécialisés pour exécuter des machines virtuelles (FORTH,. NET, Java, etc. ). Pour ce faire nous proposons de réassigner dynamiquement un sous-ensemble des ressources existantes d’EPIC pour offrir une pile d’évaluation matérielle. Deux implémentations, non-intrusives et respectant la compatibilité binaire des applications existantes, sont proposées. La principale différence entre ces piles réside dans leur gestionnaire: logiciel ou matériel. La pile d’évaluation sous le contrôle du matériel présente des fonctions avancées comme le support des piles d’évaluation typées promues par la CIL de. NET. Ainsi, nous proposons un traducteur simple-passe de binaire CIL en binaire EPIC, utilisant la pile d’évaluation matérielle. Dans la seconde partie de cette thèse, nous avons étudié l’efficacité énergétique des applications sur les architectures Intel. Nous avons ainsi défini dans un premier temps une méthodologie et des outils de mesure de l’énergie consommée et la quantité de travail utile fournie par les logiciels. Dans un second temps, nous avons entamé l’étude de transformations de code source afin de réduire / contrôler la quantité d’énergie consommée par les logiciels<br>This thesis proposes, in its first part, to extend the EPIC architecture of the Itanium processor family by providing a hardware stack. The principal idea defended here is that it is possible to close the existing performance gap between generic architectures and application specific designs to run virtual machines (FORTH,. NET, Java, etc). With this intention, we propose to reallocate dynamically a subset of the EPIC architecture’s resources to implement a hardware evaluation stack. Two implementations are proposed, both non-intrusive and compatible with existing binary codes. The fundamental difference between these stacks lies in their manager: software or hardware. The hardware controlled evaluation stack offers support for advanced functions such as the support of strongly typed evaluation stacks required by. NET’s CIL. Thus, we propose a single pass CIL binary translator into EPIC binary, using the hardware evaluation stack. In the second part of this thesis, we studied the energy efficiency of software applications. First, we defined a methodology and developed tools to measure the energy consumption and the useful work provided by the software. In a second time, we engaged the study of source code transformation rules in order to reduce/control the quantity of consumed energy by the software
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Varanavičius, Andrius. "Kompiliatorių optimizavimas IA-64 architektūroje." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2010. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20101125_190732-76081.

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Šiame darbe buvo išnagrinėtos Intel Itanium (IA-64) architektūros savybės, įtakojančios kompiliatoriaus generuojamą kodą, ir išanalizuotos kompiliatoriaus optimizacijos, kurios buvo pritaikytos IA-64 architektūrai. Buvo prieita prie išvados, kad tokias optimizacijas galima susiskirstyti į kelis tipus. Pirmiausia nuo architektūros priklausomos optimizacijos, kurių efektyvumą galima padidinti išnaudojant predikaciją ir prognozavimo savybes ar kitas IA-64 specifines savybes. Antra, nuo architektūros nepriklausomos tradicinės optimizacijos, kurių pertvarkomo kodo efektyvumą galima padidinti parenkant kitokius šias optimizacijas valdančius kompiliavimo parametrus. Tyrime buvo išnagrinėtos ciklų optimizacijos, kurių kodą galimą būtų pakeisti valdomais parametrais. Tyrimas parodė, kad iš tiesų įmanoma sugeneruoti efektyvesnį kodą Intel Itanium architektūroje, keičiant šių parametrų reikšmes nuo numatytųjų reikšmių.<br>This thesis deeply explored Intel Itanium architecture features that improve a code generated by compiler. Compiler optimizations which are tuned to this architecture are also described. Accomplished research showed that there were several types of optimizations which can be improved on IA-64 architecture. Firstly, optimizations which are dependent on architecture can be optimized using predication and speculation or other unique IA-64 features. Secondly, optimizations that are undependable from traditional architecture can be improved using more aggressive compilation controllable parameters than they are by default. Loop optimizations were chosen for final research. Research proved that changing values of these parameters from default can improve program performance.
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Carribault, Patrick. "Contribution to the compilation of irregular programs for complex architectures." Versailles-St Quentin en Yvelines, 2007. http://www.theses.fr/2007VERS0012.

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Contribution à la compilation de programmes irréguliers pour des architecturescomplexesLes architectures multicoeurs sont omniprésentes dans les processeurs généralistes et embarqués. Plusieurs flôts d'instructions (threads) sont exécutés, augmentant le parallélisme, évitant des contentions de ressources. L'execution concurrente d'un thread est déterminant pour le temps d'execution de l'application. Ainsi, l'exploitation fine d'un coeur est indispensable afin de découvrir du parallelisme d'instructions (ILP) au sein d'un flot d'instructions. Cette thèse traite de l'optimisation monocoeur de codes irréguliers comportant du parallélisme "caché". Nous avons conçus des transformations permettant d'augmenter leur ILP : Deep Jam convertissant du parallelisme à gros grain,restructuration des arbres de décisions et une plateforme d'ordonnancement d'instructions unifiant les dépendences de données et les contraintes de ressources complexes. Des accélérations par rapport à des techniques et compilateurs de pointe ont été obtenues sur Itanium 2<br>Contribution to the Compilation of Irregular Programs for Complex ArchitecturesMulticore architectures are ubiquitous in general purpose and embedded systems. Modern processors execute several instruction flows (threads) increasing the parallelism and accommodating for resource stalls. Both the execution of a thread and its interaction with the others shape the overall performance of an application. Thus, an accurate exploitation of a single core is mandatory: it leads to the necessity to discover the instruction-level parallelism (ILP) within an instruction flow. This thesis focuses on the monocore optimization of irregular codes hoseparallelism is "hidden" behind complex control flow. We designedtransformations to increase their ILP: Deep Jam converting coarse-grain parallelism, decision tree reshaping and an instruction-scheduling framework unifying data dependences and complex resource constraints. Everytransformation leads to significant speedups on a wide issue architecture(Itanium), compared to state-of-the-art techniques and compilers
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Quiñones, Moreno Eduardo. "Predicated execution and register windows for out-of-order processors." Doctoral thesis, Universitat Politècnica de Catalunya, 2008. http://hdl.handle.net/10803/6023.

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ISA extensions are a very powerful approach to implement new hardware techniques that require or benefit from compiler support: decisions made at compile time can be complemented at runtime, achieving a synergistic effect between the compiler and the processor. This thesis is focused on two ISA extensions: predicate execution and register windows. Predicate execution is exploited by the if-conversion compiler technique. If-conversion removes control dependences by transforming them to data dependences, which helps to exploit ILP beyond a single basic-block. Register windows help to reduce the amount of loads and stores required to save and restore registers across procedure calls by storing multiple contexts into a large architectural register file.<br/><br/>In-order processors specially benefit from using both ISA extensions to overcome the limitations that control dependences and memory hierarchy impose on static scheduling. Predicate execution allows to move control dependence instructions past branches. Register windows reduce the amount of memory operations across procedure calls. Although if-conversion and register windows techniques have not been exclusively developed for in-order processors, their use for out-of-order processors has been studied very little. In this thesis we show that the uses of if-conversion and register windows introduce new performance opportunities and new challenges to face in out-of-order processors.<br/><br/>The use of if-conversion in out-of-order processors helps to eliminate hard-to-predict branches, alleviating the severe performance penalties caused by branch mispredictions. However, the removal of some conditional branches by if-conversion may adversely affect the predictability of the remaining branches, because it may reduce the amount of correlation information available to the branch predictor. Moreover, predicate execution in out-of-order processors has to deal with two performance issues. First, multiple definitions of the same logical register can be merged into a single control flow, where each definition is guarded with a different predicate. Second, instructions whose guarding predicate evaluates to false consume unnecessary resources. This thesis proposes a branch prediction scheme based on predicate prediction that solves the three problems mentioned above. This scheme, which is built on top of a predicated ISA that implement a compare-and-branch model such as the one considered in this thesis, has two advantages: First, the branch accuracy is improved because the correlation information is not lost after if-conversion and the mechanism we propose permits using the computed value of the branch predicate when available, achieving 100% of accuracy. Second it avoids the predicate out-of-order execution problems.<br/><br/>Regarding register windows, we propose a mechanism that reduces physical register requirements of an out-of-order processor to the bare minimum with almost no performance loss. The mechanism is based on identifying which architectural registers are in use by current in-flight instructions. The registers which are not in use, i.e. there is no in-flight instruction that references them, can be early released.<br/><br/>In this thesis we propose a very efficient and low-cost hardware implementation of predicate execution and register windows that provide important benefits to out-of-order processors.
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Khan, Minhaj Ahmad. "Techniques de spécialisation de code pour des architectures à hautes performances." Versailles-St Quentin en Yvelines, 2008. http://www.theses.fr/2008VERS0032.

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Many applications are unable to obtain the peak performance offered by high performance architectures such as Itanium or Pentium-IV. This fact makes the code optimizations to be of utmost importance. Code specialization, which provides to the compilers, necessary information regarding important parameters in the code, is considered to be one of the most effective optimizations. Static specialization of code results in large code size, also referred to as, code explosion. Such large size of code results in cache misses and branch overhead, and also minimizes the effect of other optimizations. All these drawbacks deteriorate the performance of the application and necessitate the code to be specialized dynamically. The specialization of code is therefore performed by dynamic compilers and/or specializers by generating code at runtime, i. E. During execution of the program. The runtime specialization is not always beneficial since the runtime activities incur a large overhead during execution. This overhead can only be amortized by multiple invocations of the same code. Aimed at improving the performance of the applications, this thesis provides different strategies for specialization of code. By specializing code through static, dynamic and iterative compilation, we target the issues of code explosion and runtime overhead. Our Hybrid Specialization approach proceeds by specializing code and finding equivalent code versions. Instead of keeping all versions, any of these versions can be used as a template whose instructions are modified at runtime to adapt it to other versions. The performance is improved since the code is specialized at static compile time. The runtime specialization is therefore limited to modifying a small number of instructions. Different variants of these approaches address the issues of selection of variables for specialization, minimizing the number of compilations and reducing the frequency of runtime specialization. Our Iterative Specialization approach is able to optimize regular code by obtaining different optimization classes of some code which is specialized at static compile time. The code is iteratively transformed to benefit from these optimization classes and evaluated in order to obtain the best version. These approaches are portable and tested on high performance architectures like IA-64 and Pentium-IV using different versions of \textit{icc} and \textit{gcc} compilers. Using hybrid specialization and iterative specialization approaches, we are able to obtain a significant improvement in many complex benchmarks including SPEC, FFTW and ATLAS<br>De nombreuses applications sont incapables d'utiliser les performances crêtes offertes par des architectures modernes comme l'Itanium et Pentium-IV. Cela rend critique les optimisations de code réalisée par les compilateurs. Parmis toutes les optimisations réalisées par les compilateurs, la spécialisation de code, qui fournit aux compilateurs les valeurs des paramètres importants dans le code, est très efficace. La spécialisation statique a comme défault de produire une grande taille du code, appelée, l'explosion du code. Cette grande taille implique des défaults de caches et des coûts de branchements. Elle même impose des contraintes sur d'autres optimisations. Tous ces effets rendent nécessaire de spécialiser le code dynamiquement. La spécialisation de code est donc effectué par lescompilateurs/specialiseurs dynamiques, qui générent le code àl'exécution. Ces approches ne sont pas toujours bénéfique puisque l'exécution doit subir un grand surcoût de géneration à l'exécution qui peut détériorer la performance. De plus, afin d'être amorti, ce coût exige plusieurs invocations du même code. Visant à améliorer les performances des applications complexes, cettethèse propose différentes stratégies pour la spécialisation du code. En utilisant la compilation statique, dynamique et itérative, nous ciblons les problèmes d'explosion de la taille du code et le surcoût en temps induit par la génération du code à l'exécution. Notre "Spécialisation Hybride" génère des versions équivalentes du code après l'avoir specialisé statiquement. Au lieu de conserver toutes les versions, l'une de ces versions peut être utilisée comme un template dont les instructions sont modifiées pendant exécution afin d'être adaptée à d'autres versions. La performance est améliorée puisque le code est spécialisé au moment de la compilation statique. La spécialisation dynamique est donc limitée à la modification d'un petit nombre d'instructions. Différentes variantes de ces approches peuvent améliorer laspécialisation en choisissant des variables adéquates, en diminuant le nombre de compilations et en réduisant la fréquence de laspécialisation dynamique. Notre approche "Spécialisation Itérative" est en mesure d'optimiser les codes régulier en obtenant plusieurs classes optimales du code spécialisé au moment de la compilation statique. En suite, une transformation itérative est appliquée sur le code afin de bénéficier des classes optimales générées et obtenir la meilleure version. Les expérimentations ont été effectuées sur des architectures IA-64 et Pentium- IV, en utilisant les compilateurs gcc et icc. Les approches proposées (Spécialisation Hybride et Itérative), nous permettent d'obtenir une amélioration significative pour plusieurs benchmarks, y compris ceux de SPEC, FFTW et ATLAS
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Vieira, Mirna Lygia [UNESP]. "Imagem turística de Itanhém, litoral sul paulista." Universidade Estadual Paulista (UNESP), 1997. http://hdl.handle.net/11449/104442.

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Made available in DSpace on 2014-06-11T19:33:21Z (GMT). No. of bitstreams: 0 Previous issue date: 1997-09-15Bitstream added on 2014-06-13T19:04:04Z : No. of bitstreams: 1 vieira_ml_dr_rcla.pdf: 2869727 bytes, checksum: 22660ba98fc3d3bc487247ab504f63fe (MD5)<br>Este trabalho chama a atenção para o papel das imagens no desenvolvimento do turismo, partindo do pressuposto que, sem imagens nítidas e duradouras, as localidades não florescem, ficando restritas a um estado letárgico. Procurou-se trabalhar com os enunciados de Miossec, geógrafo tunisiano, que reconhece no turismo três imagens: global, tradicional e atual. Por imagem global entende-se a necessidade do ser humano em sair do seu mundo cotidiano e rotineiro; por imagem tradicional, aquela fixada pela cultura através dos tempos; e, finalmente, por imagem atual, aquela ditada pelos padrões de beleza contemporâneos. Dessa forma, escolheu-se a cidade de Itanhaém para desenvolver uma pesquisa que pudesse focalizar essas três imagens enunciadas. Itanhaém, localidade do litoral sul paulista que possui antecedentes históricos, é meio de atração permanente, com o mar e suas praias. Além disso, é tombada pelo Patrimônio Histórico Cultural, legitimando sua condição de cidade histórica e turística.<br>This work call attention to the role of images in tourism development, assuming that without lasting and clear images, the locations do not bloom, being restricted to a lethargic state. We attempted to work with the enunciations of Miossec, Tunisian geographer who recognizes three images in tourism: global, traditional and recent. Global image is understood as the necessity of the human being to leave his daily and ordinary world; traditional image is that fixed by culture through time; and finally, recent image is the one dictated by the contemporary beauty standards.This way, the city of Itanhaém was chosen as the site to develop a research focusing on the three images above mentioned. Itanhaém, located in the south coastal regional of the state of São Paulo, has numerous historical antecedents, it is a place of permanent touristic attraction with its beaches. Besides, it is a cultural and historic patrimony, legitimizing its condition of historic and touristic city.
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Vieira, Mirna Lygia. "Imagem turística de Itanhém, litoral sul paulista /." Rio Claro : [s.n.], 1997. http://hdl.handle.net/11449/104442.

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Orientador: Livia de Oliveira<br>Banca: Juergen Richard Langenbuch<br>Banca: Lineu Bley<br>Banca: Herbe Xavier<br>Banca: Marlene Teresinha de Muno Colesanti<br>Resumo: Este trabalho chama a atenção para o papel das imagens no desenvolvimento do turismo, partindo do pressuposto que, sem imagens nítidas e duradouras, as localidades não florescem, ficando restritas a um estado letárgico. Procurou-se trabalhar com os enunciados de Miossec, geógrafo tunisiano, que reconhece no turismo três imagens: global, tradicional e atual. Por imagem global entende-se a necessidade do ser humano em sair do seu mundo cotidiano e rotineiro; por imagem tradicional, aquela fixada pela cultura através dos tempos; e, finalmente, por imagem atual, aquela ditada pelos padrões de beleza contemporâneos. Dessa forma, escolheu-se a cidade de Itanhaém para desenvolver uma pesquisa que pudesse focalizar essas três imagens enunciadas. Itanhaém, localidade do litoral sul paulista que possui antecedentes históricos, é meio de atração permanente, com o mar e suas praias. Além disso, é tombada pelo Patrimônio Histórico Cultural, legitimando sua condição de cidade histórica e turística.<br>Abstract: This work call attention to the role of images in tourism development, assuming that without lasting and clear images, the locations do not bloom, being restricted to a lethargic state. We attempted to work with the enunciations of Miossec, Tunisian geographer who recognizes three images in tourism: global, traditional and recent. Global image is understood as the necessity of the human being to leave his daily and ordinary world; traditional image is that fixed by culture through time; and finally, recent image is the one dictated by the contemporary beauty standards.This way, the city of Itanhaém was chosen as the site to develop a research focusing on the three images above mentioned. Itanhaém, located in the south coastal regional of the state of São Paulo, has numerous historical antecedents, it is a place of permanent touristic attraction with its beaches. Besides, it is a cultural and historic patrimony, legitimizing its condition of historic and touristic city.<br>Doutor
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Książki na temat "Itanium"

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Gwennap, Linley. Intel's Itanium and IA-64: Technology and market forecast. 2nd ed. Sunnyvale, CA: MicroDesign Resources, 2000.

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Jerry, Huck, ed. Itanium rising: Breaking through Moore's second law of computing power. Upper Saddle River, N.J: Prentice Hall PTR, 2003.

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Linux on HP Integrity Servers: System administration for Itanium-based systems. Upper Saddle River, NJ: Prentice Hall PTR, 2005.

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Murādābādī, Hullaṛa. Itanī un̐cī mata choṛo. Nayī Dillī: Pustakāyana, 1996.

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Naumovsky, Yosef. ha-Regesh tamid itanu. [Israel]: Yosef Publishing, 2006.

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Māheśvarī, Baṃśī. Āvāza itanī pahacānī ki lagī apanī. Bīkānera: Vāgdevī Prakāśana, 1988.

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Sharviṭ, Elʻazar. Itanu poh: Shirim ṿe-soneṭot. Tel-Aviv: ʻEḳed, 1986.

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Sharviṭ, Elʻazar. Itanu poh: Shirim ṿe-soneṭot. Tel Aviv: ʻEḳed, 1986.

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Diasporic narratives of sexuality : identity formation among Itanian-Swedish women. Stockholm: Acta Universitatis Stockholmiensis, 2007.

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Amrami, J. ha-Devarim gedolim hem me-itanu: Pirḳe ʻavar. Tel-Aviv: Hadar, 1994.

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Części książek na temat "Itanium"

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Tan, Chih Jeng Kenneth, David Hagan, and Matthew Dixon. "A Performance Comparison of Matrix Solvers on Compaq Alpha, Intel Itanium, and Intel Itanium II Processors." In Computational Science and Its Applications — ICCSA 2003, 818–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-44839-x_86.

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Higham, Lisa, LillAnne Jackson, and Jalal Kawash. "Programmer-Centric Conditions for Itanium Memory Consistency." In Distributed Computing and Networking, 58–69. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11947950_7.

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Furukawa, Kazuyoshi, Masahiko Takenaka, and Kouichi Itoh. "A Fast RSA Implementation on Itanium 2 Processor." In Information and Communications Security, 507–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11935308_36.

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Desai, Darshan, Gerolf F. Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, and Cameron McNairy. "Performance Characterization of Itanium® 2-Based Montecito Processor." In Computer Performance Evaluation and Benchmarking, 36–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-93799-9_3.

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Li, Wenlong, Haibo Lin, Yu Chen, and Zhizhong Tang. "Increasing Software-Pipelined Loops in the Itanium-Like Architecture." In Parallel and Distributed Processing and Applications, 947–51. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30566-8_108.

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Douillet, Alban, José Nelson Amaral, and Guang R. Gao. "Fine-Grain Stacked Register Allocation for the Itanium Architecture." In Languages and Compilers for Parallel Computing, 344–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11596110_23.

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Donath, S., J. Götz, C. Feichtinger, K. Iglberger, and U. Rüde. "waLBerla: Optimization for Itanium-based Systems with Thousands of Processors." In High Performance Computing in Science and Engineering, Garching/Munich 2009, 27–38. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13872-0_3.

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Lin, Haibo, Wenlong Li, and Zhizhong Tang. "Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture." In Lecture Notes in Computer Science, 109–13. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39425-9_12.

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Yang, Yue, Ganesh Gopalakrishnan, Gary Lindstrom, and Konrad Slind. "Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT." In Lecture Notes in Computer Science, 81–95. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39724-3_9.

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Higham, Lisa, LillAnne Jackson, and Jalal Kawash. "Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture." In Lecture Notes in Computer Science, 164–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11864219_12.

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Streszczenia konferencji na temat "Itanium"

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Desai, Utpal, Simon Tam, Robert Kim, Ji Zhang, and Stefan Rusu. "Itanium processor clock design." In the 2000 international symposium. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/332357.332380.

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Greer, Bruce, John Harrison, Greg Henry, Wei Li, and Peter Tang. "Scientific computing on the Itanium#8482; processor." In the 2001 ACM/IEEE conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/582034.582075.

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Richfield, Steve. "Dealing with the "itanium effect" (abstract only)." In the 19th ACM/SIGDA international symposium. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/1950413.1950466.

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Cornea, Marius, John Harrison, and Ping Tak Peter Tang. "Intel® Itanium® floating-point architecture." In the 2003 workshop. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/1275521.1275526.

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Belady, Christian, Gary Williams, and Shaun Harris. "MX2 Processor Module: Twice the Processors in Half the Volume." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73321.

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Streszczenie:
Computer manufacturer’s are constantly trying to tweek more performance out of their existing products by using the highest performing processors. Typically, manufacturers upgrade the platforms by simply replacing the old processor with the latest speed processor. Like other manufacturers, HP generally follows this practice with the exception ot HP’s innovative mx2 module. This unique module used two Itanium-2 “Madison” processors packaged in the same physical volume as a single Itanium-2 processor. In addition, the module plugs into a standard Itanium-2 motherboard socket and requires no additional power capacity. As a result, the development team was able get 50% more performance [1] from a socket without increasing power by actively managing the power to the two processors. Thus, the performance per watt was substantially improved. This paper will provide an overview of some of the key packaging and power innovations that made the processor module a reality such as: 1) mezzanine power for space savings. The standard Itanium 2 processor has a power converter adjacent to the processor. HP engineers chose to put power on top of the processor which provided more room but made cooling the processors a challenge. 2) high performance mechnical gap filler. One of the biggest issues in the module was to develop a thermal gap filler that absorbed 0.060” of tolerance between the two processors. The thermal resistance of this technology was an order of magnitude better than anything commercially available in the industry. 3) Power Aware Architecture. This newly developed power mangement technology actively controls power to the processors. When system (thermal and power) extremes were exceeded by worst case abnormal code, the performance was throttled down until the worst case scenario had past. The combination of these advancements has delivered an innovative solution for a highly challenging design problem. This module is now shipping as the mx2 processor module in HP’s Integrity Servers and has been viewed as an engineering marvel by HP executives.
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Wunderlich, Roland E., and James C. Hoe. "In-system FPGA prototyping of an itanium microarchitecture." In Proceeding of the 2004 ACM/SIGDA 12th international symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/968280.968346.

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Stinson, Jason, and Stefan Rusu. "A 1.5GHz third generation itanium® 2 processor." In the 40th conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/775832.776011.

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Higham, Lisa, and LillAnne Jackson. "Translating between itanium and sparc memory consistency models." In the eighteenth annual ACM symposium. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1148109.1148138.

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DeLano, Eric. "Tukwila - a quad-core Intel® Itanium® processor." In 2008 IEEE Hot Chips 20 Symposium (HCS). IEEE, 2008. http://dx.doi.org/10.1109/hotchips.2008.7476561.

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Stackhouse, B., B. Cherkauer, M. Gowan, P. Gronowski, and C. Lyles. "A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor." In 2008 IEEE International Solid-State Circuits Conference. IEEE, 2008. http://dx.doi.org/10.1109/isscc.2008.4523072.

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