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Wang, Xin. "Automatically Measuring Neuromuscular Jitter." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/956.
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The analysis of electromyographic (EMG) signals detected during muscle contraction provides important information to aid in the diagnosis and characterization of neuromuscular disorders. One important analysis measures neuromuscular jitter, which is the variability of the time intervals between two muscle fibre potentials (MFPs) belonging to the same motor unit over a set of discharges. Conventionally, neuromuscular jitter is measured using single fibre (SF) EMG techniques, which can identify individual MFPs by using a SF needle electrode. However, SF electrodes are expensive, very sensitive to needle movement and not easy to operate in practise. <br /><br /> A method is studied in this thesis for automatically measuring neuromuscular jitter in motor unit potentials (MUP), it measures jitter using routine EMG techniques, which detect MUPs using a concentric needle (CN) electrode. The method is based on the detection of near MFP contributions, which correspond to individual muscle fibre contributions to MUPs, and the identification of individual MFP pairs. The method was evaluated using simulated EMG data. After an EMG signal is decomposed into MUP trains, a second-order differentiator, McGill filter, is applied to detect near MFP contributions to MUPs. Then, using nearest neighbour clustering and minimum spanning tree algorithms, the sets of available filtered MUPs can be selected and individual MFPs can be identified according to the features of their shapes. Finally, individual MFP pairs are selected and neuromuscular jitter is measured. <br /><br /> Using the McGill filter, near MFP contributions to detected CN MUPs can be consistently detected across an ensemble of successive firings of a motor unit. The method is an extension of the work Sheng Ma, compared to previous works, more efficient algorithms are used which have demonstrated acceptable performance, and which can consistently measure neuromuscular jitter in a variety of EMG signals.
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Price, Michael Ph D. (Michael R. ). Massachusetts Institute of Technology. "Asynchronous data-dependent jitter compensation." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52771.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (p. 95-96).<br>Data-dependent jitter (DDJ) caused by lossy channels is a limiting factor in the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture for DDJ compensation. The compensation circuit alters the transition times of a digital signal to cancel the expected channel-induced delays. It is designed for a 0.35 [mu]m BiCMOS process with a 240 x 140 ¹m footprint and typically consumes 3.4 mA, a small fraction of the current used in a typical transmitter. Extensive simulations demonstrate that the circuit has the potential to reduce channel-induced DDJ by at least 50% at bit rates of 6.25 Gb/s and 10 Gb/s.<br>by Michael Price.<br>M.Eng.
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Martwick, Andrew Wayne. "Clock Jitter in Communication Systems." PDXScholar, 2018. https://pdxscholar.library.pdx.edu/open_access_etds/4375.
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For reliable digital communication between devices, the sources that contribute to data sampling errors must be properly modeled and understood. Clock jitter is one such error source occurring during data transfer between integrated circuits. Clock jitter is a noise source in a communication link similar to electrical noise, but is a time domain noise variable affecting many different parts of the sampling process. Presented in this dissertation, the clock jitter effect on sampling is modeled for communication systems with the degree of accuracy needed for modern high speed data communication. The models developed and presented here have been used to develop the clocking specifications and silicon budgets for industry standards such as PCI Express, USB3.0, GDDR5 Memory, and HBM Memory interfaces.
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Oulmane, Mourad. "Integrated solutions for timing jitter measurement." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=104524.
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In this thesis we present two integrated solutions suitable for measuring the timing jitter of digital signals in SoCs and data acquisition systems (mainly sampling ADCs). The presented methods are also suitable for time measurement in a variety of timing-based metrological applications. The first method is based on the amplification of the time difference to be measured using a time amplifier (TAMP). The result of the amplification is subsequently digitized using a low resolution time-to-digital converter (TDC). The amplifier is based on the principle of virtual charge sharing that allows for continuous, monotonic and symmetric time transfer characteristics. Given its analog nature, the time amplifier has linearity issues in addition to being prone to temperature and process variations and uncertainties. To address these problems, a measurement and calibration method that consists of a dual TAMP arrangement is used to deduce the measured timing quantities without a priori knowledge of the gain of the amplifiers. Also, an empirical and more direct calibration technique suitable for a single-amplifier-based measurement system is presented. In this thesis we implement an amplifier with a measured gain of 228 s/s feeding a TDC of 78 ps of resolution resulting in a timing measurement system of 342.1 fs of nominal resolution.The second method consist of an ADC-based jitter measurement technique in which the jittery signal assumes the role of sampling clock. The novelty in this technique is that it supports arbitrary analog inputs to the ADC as measurement vehicle. The proposed measurement system comprises, in addition to the sampling ADC, an independent back-end digital system to extract jitter timing information. A very important feature of such a digital system is that the jitter-induced magnitude error in each output sample of the ADC is first measured before extracting its associated timing information. Jitter characteristics of the sampling clock are extracted with high accuracy. Indeed, as demonstrated in this thesis, even for an input signal to the ADC with a bandwidth as small as 4.61 MHz, the jitter distribution of a 12.5 MHz sampling clock is extracted with an accuracy of about 3.25 ps.<br>Dans cette thèse, nous présentons deux solutions intégrées pour mesurer les fluctuations dans le timing des signaux numériques, communément appelé “jitter”, et ce dans les systèmes sur puce et les systèmes d'acquisition de données (principalement les CANs). Ces techniques sont aussi employables dans toutes autres applications métrologiques dont le principe de fonctionnement est basé sur la mesure du temps.La première méthode est basée sur l'amplification de la différence de temps à mesurer à l'aide d'un amplificateur de temps (TAMP). Le résultat de l'amplification est ensuite numérisé en utilisant un convertisseur temps-numérique. La conception de l'amplificateur est basé sur le principe de partage virtuel de charge qui permet une courbe de transfert de temps continue, monotone et symétrique. Compte tenu de sa nature analogique, l'amplificateur est limité en termes de linéarité en plus d'être sensible aux variations de température et de processus. Pour résoudre ce problème, une méthode de mesure et d'étalonnage qui consiste en une configuration double-TAMP est utilisée pour déduire les quantités mesurées sans connaissance préalable du gain des amplificateurs utilisés. Aussi, nous présentons une technique empirique pour calibrer un système de mesure comprenant un seul amplificateur. Dans cette thèse, nous implémentons un amplificateur avec un gain mesuré de 228 s/s alimentant un convertisseur temps-numérique de 78 ps de résolution. Effectivement, ceci résulte en un système de mesure de temps d'une résolution nominale de 342,1 fs.La seconde méthode pour mesurer le jitter consiste en une technique de mesure basée sur un CAN à échantillonnage ou le signal dont le jitter est à mesurer assume le rôle d'horloge. La particularité fondamentale de cette technique est qu'elle admet des signaux analogiques arbitraires à l'entrée du CAN. Le système de mesure proposé comprend, en plus du CAN, un bloc digital entièrement indépendant du CAN pour extraire l'erreur de timing associée à chaque échantillon à la sortie du CAN. Une caractéristique très importante de ce bloc est qu'il calcule d'abords l'erreur dans le code de chaque échantillon à la sortie du CAN induite par le jitter avant d'en déduire l'erreur de timing. Dans cette étude, les caractéristiques du jitter de l'horloge d'échantillonnage sont extraites avec une grande précision. Expérimentalement parlant, même pour une bande d'entrée aussi basse que 4,61 MHz, la distribution du jitter d'une horloge d'échantillonnage de 12,5 MHz est extraite avec une précision de l'ordre de 3.25 ps.
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Helal, Belal M. 1971. "Techniques for low jitter clock multiplication." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/44417.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>Includes bibliographical references (p. 115-121).<br>Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.<br>by Belal Moheedin Helal.<br>Ph.D.
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Lee, Li-Min. "Low-jitter multi-phase clock distribution." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1610045471&sid=14&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Onunkwo, Uzoma Anaso. "Timing Jitter in Ultra-Wideband (UWB) Systems." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/10465.
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Timing offsets result from the use of real clocks that are non-ideal in sampling intervals. These offsets also known as timing jitter were shown to degrade the performance of the two forms of UWB systems impulse radio and orthogonal frequency division multiplexing (OFDM)-based UWB. It was shown that for impulse radio, timing jitter distorts the correlation property of the transmitted signal and the resulting performance loss is proportional to the root-mean-square (RMS) value of the timing jitter. For the OFDM-based UWB, timing jitter introduced inter-channel interference (ICI) and the performance loss was dependent on the product of the bandwidth and the RMS of the timing jitter. A number of techniques were proposed for mitigating the performance degradation in each form of UWB. Specifically, for impulse radio, the methods of pulse shaping and sample averaging were provided, whereas for OFDM-based UWB, oversampling and adaptive modulation were given. Through analysis and simulation, it was shown that substantial gain in signal power-to-noise ratio can be achieved using these jitter-reduction methods.
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Zhang, Peng Frank. "Jitter buffer management algorithms for voice communication." Thesis, University of Ottawa (Canada), 2002. http://hdl.handle.net/10393/6345.
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This thesis studies some jitter management algorithms for real-time applications. These algorithms are executed at a destination node, and assume no knowledge of the source characteristic or the impact of the network path characteristic. The work mainly focuses on prediction algorithms that make use of the information of the packets received in the past, and adjust buffer parameters in order to maintain certain level of quality of service (QoS). Two algorithms are proposed, first, to apply the least mean square method to predict the future packet interarrival time so that the buffer parameters can be dynamically changed in order to adapt to the bursty network traffic; second, to apply the fuzzy logic method on the buffer management to maintain the gap probability within acceptable level while keep the latency as low as possible. These two new algorithms have been evaluated using OPNET simulation and compared with some other algorithms such as the I-policy and the E-policy. We studied and discussed the tradeoff among the gap probability, average display latency, and packet loss probability. Towards the end, we have also made some design recommendations.
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Lazar, Mihai. "Empirical modeling of end-to-end jitter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0019/MQ58472.pdf.
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Moradi, Hamid. "State-of-the-art within jitter measurement." Thesis, Högskolan i Gävle, Akademin för teknik och miljö, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-16148.
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The aim of this thesis is to study different types of jitter measurement methods and to make comparison between them. With this purpose, a literature study was performed by searching in different databases. The explored databases include: a) Recent research articles in jitter measurements appearing in IEEE xplorer with published date posterior to 1998, b) Application notes and white papers from leading companies as Agilent and Anritsu. In this study it is shown that the research method presented in [20] has more accuracy compared to ITU standard method due to that an specific signal from PDH is measured directly while no specification to test equipment is need it. In case of the measurement of aperture uncertainty on ADC it is shown that the research method in [21] has more accuracy compare to IEEE standard methods because it removes quantization error and amplitude noise from measurement while does not need any frequency information
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Sickler, Jason William 1978. "Timing jitter studies in modelocked fiber lasers." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87855.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Also issued in pages.<br>Includes bibliographical references (p. 107-109).<br>by Jason William Sickler.<br>S.M.
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Lee, Leonard T. "Jitter Sampling of Deterministic Signals and Noise." International Foundation for Telemetering, 1989. http://hdl.handle.net/10150/614730.
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International Telemetering Conference Proceedings / October 30-November 02, 1989 / Town & Country Hotel & Convention Center, San Diego, California<br>In the implementation of any digital signal processing system, noise can be introduced due to hardware limitations. Some examples of noise are aliasing and amplitude quantization noise. Another noise source that is often ignored is the result of jitter, or random fluctuations of the sample period. Since clock jitter is present in almost all oscillators, a digital signal processing system rarely has perfectly timed samples. In this paper, an approximate autocorrelation function of the noise introduced by jitter sampling a deterministic function is derived. The results are applied to the specific case when the sampled function is periodic. In addition, closed-form expressions for the signal-to-noise ratio of the jittered samples are obtained. These expressions can be used to determine how stable the system clock has to be to reduce jitter noise to acceptable levels. Computer simulation was used to check the validity of the results.
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Fitzpatrick, Justin Jennings. "Analysis and Design of Low-Jitter Oscillators." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd369.pdf.
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Watkins, R. Joseph. "The adaptive control of optical beam jitter." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Dec%5FWatkins%5FPhD.pdf.
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Thesis (Ph. D. in Mechanical Engineering)--Naval Postgraduate School, December 2004.<br>Thesis advisor(s): Brij N. Agrawal, Young S. Shin. Includes bibliographical references (p. 163-165). Also available online.
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Walker, Jacqueline. "Frame synchronization techniques and jitter generation : analysis, modelling and enhancement." Thesis, Curtin University, 1997. http://hdl.handle.net/20.500.11937/1715.
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Synchronization means the aligning of the significant instants of one signal to the significant instants of another. In digital systems, where timing transfer between systems is required, synchronization is an important function. In this thesis new results on the performance and design of synchronization processes are presented. An inescapable consequence of the synchronization of external autonomous inputs in digital systems is the possibility of failure of digital devices used to capture the external signal. The anomalous behaviour of these devices is referred to as metastability. The most commonly used approach to controlling the problem of metastability is the use of synchronizers. A synchronizer can be designed to reduce the probability of metastable: failure but cannot eliminate it altogether. New high performance synchronizer designs are presented and analysed in this thesis. Another consequence of synchronization is the resulting disturbance of the significant epochs of timing signals. This disturbance is referred to as jitter. The characterization of jitter produced in synchronization processes is important in the design of digital systems. In this thesis, jitter characteristics are derived for two important applications that arise in digital communications systems. The characterization provides new insight into the dependence of the jitter on system parameters.
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Brockmann-Bauser, Meike. "Improving jitter and shimmer measurements in normal voices." Thesis, University of Newcastle Upon Tyne, 2012. http://hdl.handle.net/10443/1472.
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Instrumental acoustic voice analysis is a widely used clinical assessment technique to assist differential diagnosis, documentation and evaluation of treatment for voice disorders. However recent reports criticise an unsatisfactory reliability and validity of acoustic assessments. The present work examines confounding factors associated with the usual clinical measurement procedure and how their influence might be reduced. Further, it was investigated what jitter and shimmer indicate, and how this could be applied in voice clinics. In a routine clinical voice assessment the individuals` speaking voice SPL and F0, gender and the vowel significantly influence both jitter and shimmer. Differences in habitual voice SPL have by far the strongest influence, which may even underlie gender effects. It was shown for the first time, that clinical jitter and shimmer measurements might be considerably improved when patients phonate at a predefined level of 85dBA (10cm distance) without control of F0, and always use the vowel /a/. In healthy adults jitter and shimmer were not associated with perceptual voice irregularity. However clinical measurements in a variety of voice tasks showed that jitter and shimmer were always lower in higher voice intensities. Also in vocally healthy teachers increased voice SPL and F0 after a working day were associated with lower jitter and shimmer. Higher voice SPL is accompanied by increased vocal fold tone, which might result in more regular voice vibration patterns and thereby in lower jitter and shimmer values. From a clinical perspective this would be highly relevant information, especially in patients with impaired vocal fold tone regulation such as in functional or neurogenic voice disorders. Future research should clarify sources of jitter and shimmer and revise current normative values considering the proposed assessment protocol and gender. This might establish the clinical potential of instrumental acoustic voice analysis.
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Neilson, Hilding, and Richard Ignace. "Convection, Granulation, and Period Jitter in Classical Cepheids." Digital Commons @ East Tennessee State University, 2014. https://dc.etsu.edu/etsu-works/6243.
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Analyses of recent observations of the sole classical Cepheid in the Kepler field, V1154 Cygni, found random changes of about 30 min in the pulsation period. These period changes challenge standard theories of pulsation and evolution because the period change is non-secular, and explaining this period jitter is necessary for understanding stellar evolution and the role of Cepheids as precise standard candles. We suggest that convection and convective hot spots can explain the observed period jitter. Convective hot spots alter the timing of flux maximum and minimum in the Cepheid light curve, hence change the measured pulsation period. We present a model of random hot spots that generate a localized flux excess that perturbs the Cepheid light curve and consequently the pulsation period, which is consistent with the observed jitter. This result demonstrates how important understanding convection is for modeling Cepheid stellar structure and evolution, how convection determines the red edge of the instability strip, and just how sensitive Cepheid light curves are to atmospheric physics.
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Mittal, Rishabh. "A sampling jitter tolerant continuous-time pipeline ADC." Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/128343.
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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2020<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 43-45).<br>A sampling jitter tolerant continuous-time (CT) pipeline ADC has been presented in this thesis. In conventional discrete-time (DT) pipeline ADCs, the input is sampled upfront. The improvements in the bandwidth and sampling speed due to CMOS scaling have brought the deleterious effects of sampling clock jitter to the forefront. Any jitter in the sampling clock edge adds a random error to the input signal thereby limiting the maximum achievable signal-to-noise ratio (SNR), and hence the effective resolution of the ADC. The effect of sampling clock jitter has been considered fundamental. In the proposed ADC, we do not sample the input upfront. Rather, we sample the residue from the first stage. Since the residue is bandlimited and has a small magnitude, therefore it will have a smaller derivative. Hence, the sensitivity to the clock jitter will be greatly reduced.<br>by Rishabh Mittal.<br>S.M.<br>S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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Mesgarzadeh, Behzad. "Low-Power Low-Jitter Clock Generation and Distribution." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-14896.
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Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded. The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz. In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz.<br>Mikroprocessorer till dagens datorer innehåller hundratals miljoner transistorersom utför åtskilliga miljarder komplexa databeräkningar per sekund. I stort settalla operationer i dagens mikroprocessorer ordnas genom att synkronisera demmed en eller flera klocksignaler. Dessa signaler behöver ofta distribueras överhela chippet och driva alla synkroniseringskretsar med klockfrekvenser pååtskilliga miljarder svängningar per sekund. Detta utgör en stor utmaning förkretsdesigners på grund av att klocksignalerna behöver ha en extremt högtidsnoggranhet, vilket blir svårare och svårare att uppnå då chippen blir större.Idealt ska samma klocksignal nå alla synkroniseringskretsar exakt samtidigt föratt uppnå optimal prestanda, avvikelser ifrån denna ideala funktionalitet innebärlägre prestanda. Ytterliggare utmaningar inom klockning av digitala chip, är atten betydande andel av processorns totala effekt förbrukas i klockdistributionen.Därför krävs nya innovativa kretslösningar för att lösa problemen med bådeonoggrannheten och den växande effektförbrukningen i klockdistributionen. att lösa de problem som finns i dagens konventionella kretslösningar förklocksignaler på chip. I den första delen av denna avhandling presenterasforskningsresultat på oscillatorer vilka utgör mycket viktiga komponenter igeneringen av klocksignalerna på chippen. Teoretiska studier avfaslåsningsfenomen i integrerade klockoscillatorer har presenterats. Studiernahar visat att det finns stor potential för reducering av tidsonoggrannhet iklocksignalerna med hjälp av faslåsning till en annan signal. I avhandlingensförsta del presenteras även en diskussion om klockgeneratorer baserade påfördröjningslåsta element. Dessa fördröjningslåsta elementen, kända som DLLkretsar, har egenskapen att de kan fördröja en klocksignal med en bestämdfördröjning, vilket möjliggör skapandet av multipla klockfaser. En nykretsteknik har introducerats för klockgenerering av multipla klockfaser vilken reducerar effektförbrukningen och onoggranheten i DLL-baseradeklockgeneratorer. I denna teknik används en övervakningskrets vilken ser till attalla delar i klockgeneratorn utnyttjas effektivt och att oanvända kretsarinaktiveras. Baserat på experimentalla mätresultat från tillverkade testkretsar ikisel har en effektbesparing på mer än 10% uppvisats vid klockfrekvenser påupp till 2.5 GHz tillsammans med en betydande ökning av klocknoggranheten. I avhandlingens andra del diskuteras en klockdistributionsteknik som baseraspå resonans, vilken har visat sig vara ett lovande alternativ till konventionllabufferdrivna klockningstekniker när det gäller minskande effektförbrukning.Principen bakom tekniken är att återanvända den energi som utnyttjas till attladda upp klocklasten. Teoretiska resonemang har visat att storaenergibesparingar är möjliga, och praktiska mätningar på tillverkadeexperimentchip har visat att effektförbrukingen kan mer än halveras. Ettproblem med den föreslagna klockningstekniken är att data som används iberäkningarna kretsen direkt påverkar klocklasten, vilket även påverkarnoggranheten på klocksignalen. För att komma till rätta med detta problemetpresenteras en teknik, baserad på forskning inom ovan nämndafaslåsningsfenomen, som kan minska onoggrannheten på klocksignalen medöver 50%. Både effektbesparingen och förbättringen av tidsnoggranheten harverifierats med hjälp av mätningar på tillverkade chip vid frekvenser upp mot1.8 GHz.
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Renneflott, Anette Cathrine. "Spatial and Temporal Aspects of the Jitter Aftereffect." Thesis, Griffith University, 2014. http://hdl.handle.net/10072/366835.
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The spatial and temporal parameters determining the duration of the jitter aftereffect (JAE) were examined. Experiment one showed the JAE is a luminance-based effect. Experiment two showed that element sizes 0.084 square (≈7 cpd) and temporal frequencies above 18 Hz were optimal. Experiment three showed that the JAE is dependent on the rate of change during adaptation, not the number of changes. Experiment four compared directional noise: linear, circular, and radial to adirectional dynamic random noise (DRN). Linear noise was better than circular or radial, but random noise was best. Experiment five tested horizontal and vertical oscillation of various peak-to-peak amplitudes, frequencies and velocities. Velocity had a significant effect on JAE duration; amplitude did not. Murakami and Cavanagh’s (1998) proposal that the region of least instantaneous motion becomes the new baseline for perceived zero motion was tested. A motion energy difference between regions is necessary for the JAE. A difference in motion directions between regions at the same energy level is not sufficient. The JAE required one region above 18 Hz, and one below it. Experiment six compared Brownian motion to DRN of identical energy levels. DRN always produced a stronger JAE. Contrast was tested and found to be effective only during adaptation. A dynamic theory where miniature eye movements facilitate relative motion perception was proposed to account for the JAE.<br>Thesis (PhD Doctorate)<br>Doctor of Philosophy in Clinical Psychology (PhD ClinPsych)<br>School of Applied Psychology<br>Griffith Health<br>Full Text
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Tomlin, Toby-Daniel. "Analysis and modelling of jitter and phase noise in electronic systems : phase noise in RF amplifiers and jitter in timing recovery circuits." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2004. http://theses.library.uwa.edu.au/adt-WU2004.0021.
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Timing jitter and phase noise are important design considerations in most electronic systems, particularly communication systems. The desire for faster transmission speeds and higher levels of integration, combined with lower signal levels and denser circuit boards has placed greater emphasis on managing problems related to phase noise, timing jitter, and timing distribution. This thesis reports original work on phase noise modelling in electronic systems. A new model is proposed which predicts the up-conversion of baseband noise to the carrier frequency in RF amplifiers. The new model is validated by comparing the predicted phase noise performance to experimental measurements as it applies to a common emitter (CE), bipolar junction transistor (BJT) amplifier. The results show that the proposed model correctly predicts the measured phase noise, including the shaping of the noise about the carrier frequency, and the dependence of phase noise on the amplifier parameters. In addition, new work relating to timing transfer in digital communication systems is presented. A new clock recovery algorithm is proposed for decoding timing information encoded using the synchronous residual time-stamp (SRTS) method. Again, theoretical analysis is verified by comparison with an experimental implementation. The results show that the new algorithm correctly recovers the source clock at the destination, and satisfies the jitter specification set out by the ITU-T for G.702 signals.
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Channe, Gowda Anushree. "Latency and Jitter Control in 5G Ethernet Fronthaul Network." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019. http://amslaurea.unibo.it/17651/.
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With 5G technology, networks are expected to offer high speed with ultra-low latency among different users. Maintaining the current network architecture will lead to an unsustainable transport delay and jitters increase. Limiting the transport delay and the jitters have become a necessity for mobile network operators. The main requirement in 5G networks is the demand of limiting the transport delay. This, thesis proposes a novel mechanism to minimize packet delay and delay variation in 5G Ethernet fronthaul network. The goal is to achieve bounded delay aggregation of traffic ,suitable for application in fronthaul transport. Hybrid switching technology can be adopted to provide efficient fronthaul in 5G. Hybrid switches allows to multiplex traffics with different characteristics over the same wavelengths, thus increasing the network resource utilization. This thesis proposes a scheduling mechanism for hybrid switches to aggregate streams from the network, the Bypass traffic (BP), and the traffic from the fronthaul links, the ADD traffic, using an algorithm which looks for the time gaps in the BP stream for the insertion of the ADD traffic. The proposed strategy minimizes the delay of packets by making use of the available gaps during the transmission to limit the network latency. The size of the required time gaps, the time window, is suitably reduced by dividing the timeout time duration with number of intervals (N) with the Window reduction mechanism so that the delay variation or jitter of both aggregated streams are bounded. The results demonstrate that the aforementioned requirements are can be achieved by suitably tuning the parameters of the algorithm inputs, mainly the window reduction factor, timeout time duration and the number of intervals, resulting in values of packet delay and delay variation bounded at 10 microseconds or even lower up to 85-90percent carried load of aggregated flows. Hence, we show their suitability for delay sensitive future applications in 5G networking.
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Chan, Antonio. "Circuits for time and frequency domain characterization of jitter." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29532.
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Jitter characterization has become significantly more important for systems running at multi-gigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with sub-gate timing resolution can be achieved using two delay chains feeding into the clock and data lines of a series of D-latches known as a Vernier Delay Line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layout techniques can help to minimize these mismatches, it cannot eliminate them completely. As well, due to the nature of the design, a relatively large silicon area is required for silicon implementation. In this work, a novel technique is developed which reduces the silicon area requirements by two orders of magnitude, as well enables the measurement device to be synthesized from a register transfer level (RTL) description. A custom IC was designed and fabricated in a 0.18 mum CMOS process as a first proof of concept. The design requires a silicon area of 0.12 mm2 and measured results indicate a timing resolution of 19 ps. The synthesizable nature of the design is demonstrated using a FPGA implementation. In addition, another custom IC was designed and fabricated in a 0.35 mum CMOS process as a frequency characterization circuit to process and extract information from the data obtained from the VDL. This design occupies a silicon area of 1.83 mm2. As test time is an important consideration for a production test, an extension to this component-invariant VDL technique is provided that reduces test time at the expense of more hardware. Finally, a method for obtaining the frequency domain characteristics of the jitter using the VDL will also be given.
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Fudoli, Tania Regina Tronco. "Redução de "jitter" de justificação na hierarquia digital sincrona." [s.n.], 1992. http://repositorio.unicamp.br/jspui/handle/REPOSIP/261589.
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Orientador : Rege Romeu Scarabucci<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica<br>Made available in DSpace on 2018-07-18T08:54:07Z (GMT). No. of bitstreams: 1
Fudoli_TaniaReginaTronco_M.pdf: 7393732 bytes, checksum: 998040acdd2f6b617d9e2cc0903c00c8 (MD5)
Previous issue date: 1992<br>Resumo: A evolução das redes de comunicações digitais fez surgir novos tipos de multiplexadores que são otimizados para o transporte de sinais de dados s{ncronos. A padronização destes novos tipos de multiplexadores vem sendo feita pelo CCITT ("Intemational Telegraph and Telephone Consultative Committee"), através da Hierarquia Digital Síncrona
(HDS). Com o desenvolvimento dos multiplexadores da HDS surgiu a necessidade de analisar as principais fontes de "jitter" nessa hierarquia. Também tomou-se necessário desenvolver métodos de redução de "jitter". O processo de justificação de bit e justificação de byte utilizado na HDS introduz "jitter" de baixa freqüência - "jitter" de justificação -, que pode afetar o sinal recuperado após a operação de demultiplexagem. Este trabalho analisa a origem do "jitter" de justificação na HDS e os métodos existentes para redução desse "jitter", sendo que um novo método é sugerido. Além disso, são descritos os princípios básicos da multiplexagem síncrona<br>Abstract: Not informed.<br>Mestrado<br>Mestre em Engenharia Elétrica
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Hutsel, Brian T. Kovaleski Scott D. "Runtime and jitter of a laser triggered gas switch." Diss., Columbia, Mo. : University of Missouri--Columbia, 2008. http://hdl.handle.net/10355/5783.
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The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Title from PDF of title page (University of Missouri--Columbia, viewed on September 24, 2009). Thesis advisor: Dr. Scott Kovaleski. Includes bibliographical references.
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Chastang, Cyril. "Techniques et méthodologies de validation par la simulation des liens multi-gigahertz des cartes électroniques haute densité." Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2013. http://tel.archives-ouvertes.fr/tel-00846476.
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La tendance dans la conception de cartes électroniques imprimées est de remplacer les traditionnels bus parallèles par des liens série rapides dont le débit peut atteindre plusieurs dizaines de Gigabit par seconde (Gbps). Cette thèse proposée par THALES Communications & Security en collaboration avec le laboratoire SATIE de l'ENS de Cachan a pour objectif de définir une approche adaptée au traitement des problèmes de liens multi-gigahertz, de manière à garantir le fonctionnement d'une carte numérique complexe (multicouches, haute densité d'intégration, ...) sans qu'une phase de prototypage ne soit nécessaire. Après un état de l'art, ce travail s'est organisé en trois parties : La première partie porte sur l'étude du canal de propagation. La décomposition spectrale des liens multi-gigabits couvrant plusieurs gigahertz voir plusieurs dizaines de gigahertz montre la nécessité d'employer des logiciels de simulations spécifiques au domaine des hyperfréquences. Une évaluation de certains solveurs électromagnétiques 3D parmi les plus récents a été réalisée afin d'extraire les paramètres S du canal de propagation de façon précise et rapide a partir des informations issues des logiciels de CAO utilisés à THALES. La seconde partie traite de la prise en compte des émetteurs, des récepteurs et des traitements numériques associés dans la simulation afin de réaliser des calculs de diagrammes de l'œil, de taux d'erreurs binaires (BER) et de jitter. L'utilisation de la norme IBIS-AMI, très récente, et la comparaison des performances aves d'autres outils, tel que HSPICE, a demandé l'évaluation de simulateurs circuit de dernière génération. Cette étape a été réalisée en étroite collaboration avec les éditeurs des logiciels car certains outils ne sont pas suffisamment matures pour s'inscrire dans un flot global de conception. Enfin, la chaîne de simulation complète ayant été validée par la mesure, nous avons effectué une analyse approfondie des différentes composantes du jitter en fonction des phénomènes physiques plus ou moins destructeurs pour la qualité du signal. Cela nous a ensuite permis d'établir les règles et la méthodologie de conception, en tenant compte des marges allouées à partir des résultats de l'analyse du jitter.
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Walker, Jacqueline. "Frame synchronization techniques and jitter generation : analysis, modelling and enhancement." Curtin University of Technology, Co-operative Research Centre for Broadband Telecommunications and Networking Telecommunications, 1997. http://espace.library.curtin.edu.au:80/R/?func=dbin-jump-full&object_id=10841.
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Synchronization means the aligning of the significant instants of one signal to the significant instants of another. In digital systems, where timing transfer between systems is required, synchronization is an important function. In this thesis new results on the performance and design of synchronization processes are presented.An inescapable consequence of the synchronization of external autonomous inputs in digital systems is the possibility of failure of digital devices used to capture the external signal. The anomalous behaviour of these devices is referred to as metastability. The most commonly used approach to controlling the problem of metastability is the use of synchronizers. A synchronizer can be designed to reduce the probability of metastable: failure but cannot eliminate it altogether. New high performance synchronizer designs are presented and analysed in this thesis.Another consequence of synchronization is the resulting disturbance of the significant epochs of timing signals. This disturbance is referred to as jitter. The characterization of jitter produced in synchronization processes is important in the design of digital systems. In this thesis, jitter characteristics are derived for two important applications that arise in digital communications systems. The characterization provides new insight into the dependence of the jitter on system parameters.
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Sholander, Peter Edward. "Characterization and minimization of jitter and wander in SDH networks." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13461.
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Zare-Hoseini, Hashem. "Continuous-Time Delta-Sigma Modulators with Immunity to Clock-Jitter." Thesis, University of Westminster, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.500545.
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詹益豪. "Jitter Analysis and Implementation of Periodic Jitter Identification." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/94730014210495678058.
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碩士<br>中華大學<br>電機工程學系碩士班<br>91<br>In this thesis, we present a time-domain jitter separation method to estimate the random and deterministic jitter components. And, we structure a periodic jitter model to generate the periodic jitter clock. Then, using accumulated time analysis to determine the presence of periodic jitter and analyze the frequency of periodic jitter.
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Seifi, Seyed Mohammad Ehsan. "Sampling Time Jitter." Thesis, 2013. http://hdl.handle.net/10012/7237.
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Electrical systems which use voltage transitions to represent timing information suffer from a degrading phenomenon called timing jitter. Sampling time jitter is the deviation of sampling clock from its ideal position. As transmission rates raise above couple of GHz, deviations become significant comparing to signalling interval, jitter becomes a fundamental performance bottleneck. Especially in band-limited communication systems that imperfect sampling times result in Inter-Symbol Interference (ISI) jitter is a very limiting factor to decode correct transmitted data. In this case, jitter timing error translates into amplitude error.
At first, the effect of sampling time jitter at the received signal is modelled as an additive noise .This additive noise signal which we call it jitter noise is a coloured noise that also depends on input signal. Expressions for jitter noise correlation factors, its cross- correlation with input signal are derived. These correlations depend on input spectral density, timing jitter characteristic function (Fourier transform of jitter probability density function) and whether timing jitter is white or coloured. In case of first order Gauss-Markov process for sampling time jitter it is observed that in high memory regime (highly correlated timing jitter) the spectral density of additive jitter noise is concentrated around higher frequencies. Exploiting this quality, a spectral shaping scheme is used to improve the performance in terms of Bit Error Rate (BER) for an AWGN channel with discrete input corrupted by sampling time jitter. Simulation results comparing the proposed scheme performance with a minimum distance decoder are provided.
As another approach the well-known Viterbi Algorithm is used for decoding same AWGN channel suffering from ISI terms due to sampling jitter. The Viterbi algorithm, which basically is a dynamic programming algorithm, finds the most likely input data and jitter times based on observed output sequence. A quantized version of jitter times is used to be able to work with a finite state trellis and to find likelihoods along the paths of the diagram. Then Bit Error Rate curves for different jitter quantization levels and different impulse response lengths of channel are presented.
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Buckwalter, James Franklin. "Deterministic Jitter in Broadband Communication." Thesis, 2006. https://thesis.library.caltech.edu/407/1/Buckwalter_Thesis01_06.pdf.
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<p>The past decade has witnessed a drastic change in the design of high-speed serial links. While Silicon fabrication technology has produced smaller, faster transistors, transmission line interconnects between chips and through backplanes have not substantially improved and have a practical bandwidth of around 3GHz. As serial link speeds increase, new techniques must be introduced to overcome the bandwidth limitation and maintain digital signal integrity. This thesis studies timing issues pertaining to bandwidth-limited interconnects. Jitter is defined as the timing uncertainty at a threshold used to detect the digital signal. Reliable digital communication requires minimizing jitter.</p>
<p>The analysis and modeling presented here focuses on two types of deterministic jitter. First, dispersion of the digital signal in a bandwidth-limited channel creates data-dependent jitter. Our analysis links data sequences to unique timing deviations through the channel response and is shown for general linear time-invariant systems. A Markov model is constructed to study the impact of jitter on the operation of the serial link and provide insight in circuit performance. Second, an analysis of bounded-uncorrected jitter resulting from crosstalk induced in parallel serial links is presented.</p>
<p>Timing equalization is introduced to improve the signal integrity of high-speed links. The analysis of deterministic jitter leads to novel techniques for compensating the timing ambiguity in the received data. Data-dependent jitter equalization is discussed at both the receiver, where it complements the operation of clock and data recovery circuits, and as a phase pre-emphasis technique. Crosstalk-induced, bounded-uncorrected jitter can also be compensated. By detecting electromagnetic modes between neighboring serial links, a transmitter or receiver anticipates the timing deviation that has occurred along the transmission line.</p>
<p>Finally, we discuss a new circuit technique for submillimeter integrated circuits. Demands of wireless communication and the high speed of Silicon Germanium transistors provide opportunities for unique radio architectures for submillimeter integrated circuits. Scalable, fully-integrated phased arrays control a radiated beam pattern electronically through tiling multiple chips. Coupled-oscillator arrays are used for the first time to subharmonically injection-lock across a chip or between multiple chips to provide phase coherence across an array.</p>
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Wang, Jian-Ren, and 王健任. "Jitter-based SCTP: Improving SCTP performance by jitter-based congestion control over wired-wireless networks." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/w488gs.
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碩士<br>國立中央大學<br>資訊工程研究所<br>94<br>With the evolution of communication networks, wireless networks gradually become the most adaptive communication networks in next generation internet. Desktops and mobile devices may be equipped with multiple wired and/or wireless network interfaces. Stream Control Transmission Protocol (SCTP) has been proposed for reliable data transport and its multihoming feature makes use of network interfaces effectively to improve performance and reliability. However, like TCP, SCTP suffers unnecessary performance degradation over wired-wireless heterogeneous networks. The main reason is that original congestion control scheme of SCTP cannot differentiate loss events so that SCTP reduces the congestion window inappropriately. In order to solve this problem and improve performance, we propose a jitter-based congestion control scheme with end-to-end semantics over wired-wireless networks. Besides, we amend decision policy of jitter ratio loss distinction to make it more correctness and robustness. Available bandwidth estimation scheme will be integrated into our congestion control mechanism to make the bottleneck more stabilized. Simulation experiments reveal that our scheme (JSCTP) gives prominence to improve performance effectively over wired-wireless networks.
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Chi-Chang, Liu, and 劉吉昌. "A New Methodology to Reduce Jitter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/57374350754595925209.
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碩士<br>逢甲大學<br>資訊電機工程碩士在職專班<br>94<br>Signal jitter is an important factor that has no way to ignore many circuit. Solving signal jitter becomes the essential work when facing the mechanism requirement of precision and speed from users. Researches in this field are devoted to the measurement of clock jitter and its influence on circuits, so far. Fewer of them are focused on the analysis and the corresponding effect of data jitter, which can be the unstablization factor of a mechanism, on circuits; even the researches of concerning both of these two kinds of jitters. This research focuses on processing these two kinds of jitters simultaneously and synchronizing the outputs of both.
First of all, a mono-stable pulse is generated based on a fixed clock cycle for the integration computing with integrator. The intersection occurred when comparing the output sawtooth wave with the reference fixed voltage from the comparator. And the trigger signal referred to the intersection help to return the jitter removed of pulse signals to cycles of the original clock signals. T flip-flop treats the correct clock signals as its pluses and tunes the time lags from signals for lightly overtaking signals. It allows each of the rising edge and the falling edge of signals generates a mono-stable pulse, and input them to T flip-flop for removing jitters and synchronizing outputs. Experiments conducted with simulated data show our proposed circuit decreases effectively random jitters, period jitters, cycle-to-cycle jitter and long-term jitters.
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"Jitter reduction techniques for digital audio." 1997. http://library.cuhk.edu.hk/record=b5889216.
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by Tsang Yick Man, Steven.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.<br>Includes bibliographical references (leaves 94-99).<br>ABSTRACT --- p.i<br>ACKNOWLEDGMENT --- p.ii<br>LIST OF GLOSSARY --- p.iii<br>Chapter 1 --- INTRODUCTION --- p.1<br>Chapter 1.1 --- What is the jitter ？ --- p.3<br>Chapter 2 --- WHY DOES JITTER OCCUR IN DIGITAL AUDIO ？ --- p.4<br>Chapter 2.1 --- Poorly-designed Phase Locked Loop ( PLL ) --- p.4<br>Chapter 2.1.1 --- Digital data problem --- p.7<br>Chapter 2.2 --- Sampling jitter or clock jitter ( Δti) --- p.9<br>Chapter 2.3 --- Waveform distortion --- p.12<br>Chapter 2.4 --- Logic induced jitter --- p.17<br>Chapter 2.4.1 --- Digital noise mechanisms --- p.20<br>Chapter 2.4.2 --- Different types of D-type flop-flip chips are linked below for ease of comparison --- p.21<br>Chapter 2.4.3 --- Ground bounce --- p.22<br>Chapter 2.5 --- Power supply high frequency noise --- p.23<br>Chapter 2.6 --- Interface Jitter --- p.25<br>Chapter 2.7 --- Cross-talk --- p.28<br>Chapter 2.8 --- Inter-Symbol-Interference (ISI) --- p.28<br>Chapter 2.9 --- Baseline wander --- p.29<br>Chapter 2.10 --- Noise jitter --- p.30<br>Chapter 2.11 --- FIFO jitter reduction chips --- p.31<br>Chapter 3 --- JITTER REDUCTION TECHNIQUES --- p.33<br>Chapter 3.1 --- Why using two-stage phase-locked loop (PLL ) ？<br>Chapter 3.1.1 --- The PLL circuit components --- p.35<br>Chapter 3.1.2 --- The PLL timing specifications --- p.36<br>Chapter 3.2 --- Analog phase-locked loop (APLL ) circuit usedin second stage --- p.38<br>Chapter 3.3 --- All digital phase-locked loop (ADPLL ) circuit used in second stage --- p.40<br>Chapter 3.4 --- ADPLL design --- p.42<br>Chapter 3.4.1 --- "Different of K counter value of ADPLL are listed for comparison with M=512, N=256, Kd=2" --- p.46<br>Chapter 3.4.2 --- Computer simulated results and experimental results of the ADPLL --- p.47<br>Chapter 3.4.3 --- PLL design notes --- p.58<br>Chapter 3.5 --- Different of the all digital Phase-Locked Loop (ADPLL ) and the analogue Phase-Locked Loop (APLL ) are listed for comparison --- p.65<br>Chapter 3.6 --- Discrete transistor oscillator --- p.68<br>Chapter 3.7 --- Discrete transistor oscillator circuit operation --- p.69<br>Chapter 3.8 --- The advantage and disadvantage of using external discrete oscillator --- p.71<br>Chapter 3.9 --- Background of using high-precision oscillators --- p.72<br>Chapter 3.9.1 --- The temperature compensated crystal circuit operation --- p.73<br>Chapter 3.9.2 --- The temperature compensated circuit design notes --- p.75<br>Chapter 3.10 --- The discrete voltage reference circuit operation --- p.76<br>Chapter 3.10.1 --- Comparing the different types of Op-amps that can be used as a voltage comparator --- p.79<br>Chapter 3.10.2 --- Precaution of separate CMOS chips Vdd and Vcc --- p.80<br>Chapter 3.11 --- Board level jitter reduction method --- p.81<br>Chapter 3.12 --- Digital audio interface chips --- p.82<br>Chapter 3.12.1 --- Different brand of the digital interface receiver (DIR) chips and clock modular are listed for comparison --- p.84<br>Chapter 4. --- APPLICATION CIRCUIT BLOCK DIAGRAMS OF JITTER REDUCTION AND CLOCK RECOVERY --- p.85<br>Chapter 5 --- CONCLUSIONS --- p.90<br>Chapter 5.1 --- Summary of the research --- p.90<br>Chapter 5.2 --- Suggestions for further development --- p.92<br>Chapter 5.3 --- Instrument listing that used in this thesis --- p.93<br>Chapter 6 --- REFERENCES --- p.94<br>Chapter 7 --- APPENDICES --- p.100<br>Chapter 7.1.1 --- Phase instability in frequency dividers<br>Chapter 7.1.2 --- The effect of clock tree on Tskew on ASIC chip<br>Chapter 7.1.3 --- Digital audio transmission----Why jitter is important?<br>Chapter 7.1.4 --- Overview of digital audio interface data structures<br>Chapter 7.1.5 --- Typical frequency Vs temperature variations curve of Quartz crystals<br>Chapter 7.2 --- IC specification used in these research project
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Chen, Jun-Jia, and 陳俊嘉. "PLL with On-Chip Jitter Measurement." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/71915360853316686796.
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Cheng, Nai-Chen, and 鄭乃禎. "On-Chip Low Jitter Clock Generation." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/73032553756572761821.
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碩士<br>國立成功大學<br>電機工程學系專班<br>93<br>Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks in high-performance digital systems. Any timing jitter or phase noise significantly degrades the performance of these systems, especially as operating frequency increases. Switching activity in large digital systems introduces power supply or substrate noise which perturb the more sensitive blocks in a PLL, especially the voltage-controlled oscillators (VCOs),
At system level, this work investigates the effects of PLL design parameters, such as bandwidth and peaking in frequency response, on timing jitter of PLL output clock. The analysis includes several common noise sources in a PLL and develops an intuition for selection design parameters to obtain minimum output jitter based on the dominant noise source.
At circuit level, two different architectures of VCOs are realized. One employs simple V-I but with noise-canceling techniques. And the other VCO using an operational amplifier, which is self-biased, to maintain good linearity and sensitivity of VCO. The self-biased VCO is used for designing a wide frequency range PLL, with a proposed charge pump. Also, the loop parameters of the PLL are well chosen in the design process.
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黃名宏. "Jitter Tolerant Differential Non-linearity Measurement." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/59830491459141580458.
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碩士<br>國立交通大學<br>電機學院碩士在職專班電機與控制組<br>96<br>As the prosperity of technology, circuit becomes more complicated and scale is going to be smaller. Thus, there’re many problems which are used to be treated as bias and can be ignored originally become much difficulty to overcome at present , jitter for example .Differential non-linearity measurement (Linear Ramp histogram method) introduced in IEEE 1057 can’t measure Differential non-linearity precisely within reasonable time frame in the case of turbulent jitter.
To have accurate measurement of Differential non-linearity under the influence of jitter, we propose a method called “Cumulative Differential non-linearity” in this paper. It can measure Differential non-linearity with jitter allowed. We use the characteristic of jitter to analyze Differential non-linearity. Compared with the method of Linear Ramp histogram method, we can get more precise Differential non-linearity by less time of sampling in the same test environment with jitter effect.
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Thomas, Linson. "Power Integrity Analysis For Jitter Characterization." Thesis, 2016. http://ethesis.nitrkl.ac.in/8271/1/2016_MT_214EC2185_Power.pdf.
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Continuous improvements in the VLSI domain have enabled the integration of billions of transistors on the same die operating at frequencies in the gigahertz range. These advancements have brought upon the era of system-on-chip (SoC). Traditionally, analog ICs has been prone to device noise while digital ICs have typically not been the prime concern being considered as relatively immune to noise. With faster transition times and denser integration, the scenario wherein digital ICs were considered to be immune to noise has changed significantly. Drastic changes in the physical design of an IC and increase in the operating frequencies has immensely changed the classical understanding of noise in the new age complex ICs. Switching noise specifically has become a dominating criteria for high performance digital and mixed signal ICs. Voltage variations on the power/ground nodes of a circuit is a type of switching noise affecting digital and mixed-signal ICs. Therefore, power integrity (PI) has become a critical challenge that must be addressed at the system level considering the parasitic effects of package and board. In this work, a die, package and board modeling and co-simulation methodology is presented which can be easily integrated into a standard VLSI design flow. This methodology involves breaking down the system in multiple components and generating models for each component to observe individual performance. System level response can be seen by combining them together. This approach has been successfully exploited to guarantee the power integrity on an industrial design. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins.
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CHIANG, HU-CHENG, and 江虎城. "Design of High Resolution, Low Measured Jitter Errorand Variation Resilient On-Chip Jitter Sensor for DDR4-3200." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/m36b79.
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碩士<br>國立中正大學<br>電機工程研究所<br>106<br>As the technology node progresses and the operating frequency of circuit and system increases, variation’s affection becomes more and more critical, and jitter effect is one of the most severe variations.
However, jitter effect is difficult to be measured and quantified in most on chip systems. In the past, jitter had to be measured via external equipment, but as the operating frequency rise, the equipment which is able to conduct high frequency jitter measurement are costly, and the probe-caused noise will affect the measurement results. To measure jitter more effective, on-chip jitter sensor is a better choice than external equipment. However, if the variation occurs during measurement phase, the results will have great chance being flaw. This paper proposed design of high resolution, low measured jitter error and variation resilient on-chip jitter sensor for DDR4-3200 [1]. Compare to conventional jitter sensors, we propose run-time automatic resolution calibration circuit. Resolution calibration will be done before every measurement phase, after calibration our jitter sensor can detect active variation occurrence and dynamically adjust resolution.
This work is done in UMC 28nm process, 0.9V operating voltage, and the operating frequency is same as DDR4-3200 circuit, 1.6GHz, with 1ps resolution, 2.13mW power consumption and approximate 167nm×98um die area, worst case measurement error improve from 331% to -148%.
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Lee, Jae Wook. "A BIST circuit for random jitter measurement." Thesis, 2012. http://hdl.handle.net/2152/ETD-UT-2012-05-5513.
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Jitter is a dominant factor contributing to a high bit error rate (BER) in high speed I/O circuitry, and it aggravates the quality of a clock signal from a phase-locked loop (PLL), subsequently impacting a given timing budget. The recent proliferation of systems-on-a-chip (SoCs) with help of technology scaling makes jitter measurement more challenging as the SoCs integrate more I/O circuitry and PLLs within a chip. Jitter has been, however, one of the most difficult parameters to measure accurately when validating the high speed serial I/O circuitry or PLLs, mostly due to its small value.
External instruments with full-fledged high precision measurement hardware, along with comprehensive analysis tools, have been used for jitter measurement, but increased test cost from long test time, signal integrity, and human intervention prevent this approach from being used for high volume manufacturing testing. Built-in self-test (BIST) solutions have recently become attractive to overcome these drawbacks, but complicated analog circuit designs that are sensitive to ever increasing process variations, and associated complex analysis methods impede their adoption in the SoCs.
This dissertation studies practical random jitter measurement methods that achieve measurement accuracy by exploiting a differential approach and make the proposed methods tester-friendly solutions for an automatic test equipment (ATE). We first propose a method of measuring the average value of the random jitter, rather than measuring the jitter at every clock cycle, that can be converted to the root-mean-square (RMS) value of the random jitter, which is the key indicator of the quantity of the random jitter. Then, we propose a simple but accurate delay measurement method which uses the proposed jitter measurement method for random jitter measurement when a reference signal, such as a golden PLL output in high speed I/O validation, is not available. The validity of the proposed random jitter measurement method is supported by measurement results from a test chip. The impact of substrate noise on the signal of interest is also shown with measurements using a test chip. To address the random jitter of a clock signal when the clock is operating in its functional mode, we demonstrate a novel method for random jitter measurement that explores the shmoo capability of a low-cost production tester without relying on any BIST circuitry.<br>text
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Yang, Wang-Ru, and 楊旺儒. "Real Time Process Scheduling with Jitter Control." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/38383162441198813976.
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HSIAO, MING-FU, and 蕭明富. "Minimizing Coupling Jitter in Multiple Clock Networks." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/94422126303274728418.
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博士<br>國立臺灣大學<br>電機工程學研究所<br>91<br>Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase coupling jitter, which may degrade significantly the system performance. Besides, in modern chip designs, there is usually more than one clock net, and sometimes even tens of them. It is therefore imperative to design clock topologies to prevent possible coupling jitter among them. In this Dissertation, we address the coupling jitter problem. We propose algorithms to design clock topology, perform routing minimizing effective coupling length, and size buffers to minimize jitter effect. The experimental results show a significant reduction of coupling jitter compared to the conventional clock tree synthesis which does not take into account the inter-clock coupling jitter effects.
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Chiang, Yu-Chen, and 江宇晟. "Jitter Performance Study For Phase-Lock Loop." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/70476321354403064487.
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碩士<br>國立清華大學<br>電機工程學系<br>93<br>In many circuits, PLL must provide an output clock to follow the input clock closely.
Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch.
This thesis proposes the prediction method of jitter performance, for estimate the output jitter comes from each noise source. Initially, Hspice and Spectre are used to estimate the output phase noise of each noise source in coordinate with phase-noise-to-jitter transfer function and noise transfer function (NTF) to estimate the PLL output jitter.
This thesis primary considered the noise created by phase-locked loop. Include thermal analysis and the phase noise created by each block in PLL.
Thermal Analysis:
This part primarily analysis the phase noise created by each block in PLL. Then use the phase noise to jitter equation to estimate the PLL output jitter.
PLL Each Block Phase Noise:
This park primarily consider VCO phase noise、current mismatch created by PFD/CP and input clock phase noise.
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Zhao, Ann-Shen, and 趙安生. "Built-in Self Test for jitter measurement." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/30296290427134359925.
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碩士<br>國立成功大學<br>電機工程學系碩博士班<br>93<br>Phase-locked loops (PLLs) are often served as clock generators and/or frequency synthesizers in a system on a chip (SoC). Since it is usually built inside the chip deeply, it is hard to test PLL directly by using automatic test equipments (ATEs). For a clock signal generated by a PLL, jitter is one of the specifications which are hardest to be test.
At the beginning of this thesis, we survey and investigate several built-in self-test (BIST) schemes used for jitter measurement in recent years. We also summarize pros, cons and challenges in practical implementation for these BIST schemes.
To accomplish the jitter measurement, it often needs a golden (jitter free) reference signal in many conventional BIST methods. However, it is hard to provide such ideal signal. Hence, we propose a BIST method which does not need an ideal reference clock. In this BIST method, we measure jitter and employ statistical analysis techniques to calibrate the measured data to achieve higher accuracy results.
Besides, we propose a BIST circuit based on the method developed previously. The BIST circuit mainly contains two building blocks: jitter amplifier and ring oscillator based jitter calculating circuit. Jitter amplifier is used to linearly amplify tiny time intervals to enhance the measuring resolution. Ring oscillator based jitter calculating circuit is used to collect the timing data and build the histogram of jitter to estimate the amount of jitter. In contrast to conventional BIST methods, the proposed BIST scheme can remove the extra jitter generated by the built-in ring oscillator itself to obtain more accurate measuring results by using linear jitter amplifier and simple statistical techniques. All main function blocks proposed in this thesis are all verified and simulated with TSMC 0.18 �慆 process.
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Yang, Cheng-Han, and 楊承翰. "Area-Efficient One-Period Delay Jitter Measurement." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/55031029915294714988.
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碩士<br>國立彰化師範大學<br>電子工程學系<br>97<br>In this thesis, a true one-period delay circuit is proved to be actually a synchronous mirror delay. An area-efficient all-digital synchronous mirror delay is thus developed as a true one-period delayline for cycle-to-cycle jitter measurement. In our preliminary work we develop an area-efficient SMD. The power dissipation can thus be also reduced. A VDL is designed for the testability of the SMD [11].
In the comparison pervious work, the author in [10] first develop a one period delay circuit. They add some control gates to a long VDL and generate the postponed signal and a one-period delayed signal with the same latency TD. It seems that they expected to measure the ith jitter T(i+1)-Ti via the second VERNIER DELAYLINE, however they actually capture the jitters, that is not the jitter compared to the previous period but the intrinsic jitter generated by their ONE PERIOD DELAY itself. In this thesis, the SMD is implanted to be a True One Period delayline.
From measured results of implementation, the proposed true one-period delay jitter measurement circuit suffers low resolution but saves 75% of area overhead and the associated power dissipation.
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Chen, Jyh Ming, and 陳志銘. "Jitter Analysis in Asynchronous and Synchronous Networks." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/08680229559803567960.
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Chen, Chien Hung, and 陳建宏. "An Auto Jitter Calibration Dealy-Locked Loop." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/28450179770886339855.
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碩士<br>國立臺灣師範大學<br>應用電子科技研究所<br>99<br>With a first order system and the noise would not accumulate in the voltage controlled delay line (VCDL), delay-locked loop has advamtages such as: easy to design, having small aarea and good jitter performance for clock generator.So it is becoming a popular architecture used in memory intergface, LCD, wireless communication system... etc. However, the locking time and the jitter caused by non-ideal effect are important topics for delaylocked loop. In this paper, we proposed an auto jitter calibration delay-locked loop with fast locking feature to overcome these two problems.
The proposed delay-locked loop, causing the voltage controlled delay line, VCDL's "A fixed latency of one clock cycle,"[9], we design a frequency estimator circuit to change the initial voltage at the almost locking level to accelerate the locking time before the DLL's feedback system of charge pump's fine tuning until the DLL is locked. In addition, the proposed DLL using an auto jitter calibration to produce a little delay that is combining two phase frequency detectors to suppress the jitter area, and the output jitter is smaller.
The proposed DLL is fabricated in CMOS 0.18μm 1P6M technology. The core area is 0.77x0.84mm2 and the power dissipation is 29m at 400MHz. The locking range is 150MHz~550MHz and the locking time is &lt;9 cycles. The Peak-to-Peak Jitter is 2.9ps at 400MHz.
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Liao, Xin-Sheng, and 廖信勝. "Design of Low Jitter Phase-Locked Loop." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/f28e8d.
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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>96<br>Each device has been employed in PLL would contribute the unavoidable noise to degrade the jitter performance. In addition, the power/ground and substrate noise injected to PLL which integrated in a chip also aggravates jitter heavily. This thesis proposed some improvements for the essential issue of low jitter. We consequently improve the circuit architecture of each device and described it as following. One of that is to add self-adjusted mechanism into a charge pump to eliminate whose output current mismatch; furthermore, the mechanism is capable to extend the control voltage range of Voltage-controlled oscillator (VCO). On the other hand, because of the third-order loop filter with smaller bandwidth, it performs better noise suppression ability than the second-order loop filter does; nonetheless, the third-order presents longer acquisition time. In order to obtain the advantages of both two types of loop filters, a proposed switching mechanism has been utilized to select them appropriately. To accommodate the switching mechanism, we design the loop filter for monolithic integration; as a result, both saving silicon area and isolating noise are main concerns while designing it. By using capacitor multiplier to avoid large amount silicon occupation and utilizing an additive low dropout voltage regulator (LDO), the noise injection can be isolated and a stable supply voltage is also provided for the loop filter. The VCO plays an important role in the whole system whereas it is an extremely sensitive device. Therefore, coarse and fine tuning mechanisms are employed in current-starved elements for delay cells that can lead to the VCO gain (KVCO) tunable and then mitigate the disturbance of external noise.
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Brooks, Anna. "The neural correlates of the jitter illusion." Thesis, 2004. https://researchonline.jcu.edu.au/1034/1/01front.pdf.
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The work that follows introduces a new visual illusion. The ‘jitter’ illusion arises in response to single brief presentations of stationary Glass patterns composed of decrement- and increment-defined dot-pairs. Remarkably, the perceptions that arise are of coherent global motion in trajectories that are consistent with the spatial configuration of the Glass patterns; patterns configured according to concentric functions give rise to perceptions of motion in concentric trajectories, those configured according to radial functions give rise to perceptions of motion in radial trajectories, and so on. The aim of the work that follows was to develop a model of the neural correlates of this illusion. An additional aim was to explore the implications of such a model for developing a broader understanding of the means by which coherent visual perceptions arise.
Experiments were conducted under the working hypothesis that the jitter illusion is mediated by activity that arises within the magno-cellular (M-), and not the parvo-cellular (P-) pathway of the visual system. It is argued that a model based entirely on M-pathway activity can effectively account for the illusion if two critical conditions are met. The first is that the model must propose the mechanism by which presentations of stationary Glass patterns stimulate activity in the motion-sensitive cells of the M-pathway. The second is that it must propose plausible mechanism(s) by which the ensuing M-pathway activity gives rise to perceptions of coherent global motion. Experiments reported in chapters 3 and 4 address the first of these conditions. Data from these experiments suggest that abrupt changes in luminance introduced at the onset and offset of stationary Glass patterns (and not eye-movements) mediate the M-pathway activity on which the illusion is based. Experiments reported in chapters 5 through to 8 address the second condition. In chapters 5 and 6, the data suggest that the patterns of Off- and On-channel responses elicited by individual Glass pattern dot-pairs somehow stimulates cells that act as ‘local’ motion detectors. In chapters 7 and 8, models of the means by this occurs were tested. The resulting data rule out the possibility that the stimulation is a product of a processing asynchrony in the M-pathway Off- and On-channels. Instead, they are consistent with a model based on the diphasic temporal impulse-response functions attributed to cells that make up the M-pathway. Based on its ability to satisfy each of the stated conditions, the so-called diphasic TIRF model is presented as a plausible account of some of the neural correlates of the jitter illusion.
The implications of the diphasic TIRF model are discussed in relation to both the jitter illusion and to visual processing more generally. One of the critical (and novel) implications of the model is that under some circumstances, M-pathway mechanisms ‘extract’ structural information from static visual images that P-pathway mechanisms cannot. On this basis, it is argued that both the jitter illusion and the diphasic TIRF model offer valuable insights into some of the means by which light-induced activity within the human visual system gives rise to coherent global perceptions.