Gotowe bibliografie tematyczne / Low-density parity-check Decoders

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Gotowa bibliografia na temat „Low-density parity-check Decoders”

Autor: Grafiati
Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "Low-density parity-check Decoders"

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Mao, Yun, Ying Guo, Jun Peng, Xueqin Jiang, and Moon Ho Lee. "Double-Layer Low-Density Parity-Check Codes over Multiple-Input Multiple-Output Channels." International Journal of Antennas and Propagation 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/716313.

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We introduce a double-layer code based on the combination of a low-density parity-check (LDPC) code with the multiple-input multiple-output (MIMO) system, where the decoding can be done in both inner-iteration and outer-iteration manners. The present code, called low-density MIMO code (LDMC), has a double-layer structure, that is, one layer defines subcodes that are embedded in each transmission vector and another glues these subcodes together. It supports inner iterations inside the LDPC decoder and outeriterations between detectors and decoders, simultaneously. It can also achieve the desire
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Xia, Tian, Hsiao-Chun Wu, and Hong Jiang. "New Stopping Criterion for Fast Low-Density Parity-Check Decoders." IEEE Communications Letters 18, no. 10 (2014): 1679–82. http://dx.doi.org/10.1109/lcomm.2014.2349988.

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Djordjevic, Ivan B. "Photonic entanglement-assisted quantum low-density parity-check encoders and decoders." Optics Letters 35, no. 9 (2010): 1464. http://dx.doi.org/10.1364/ol.35.001464.

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Perez-Pascual, Asun, Alex Hamilton, Robert G. Maunder, and Lajos Hanzo. "Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders." IEEE Access 6 (2018): 55741–53. http://dx.doi.org/10.1109/access.2018.2872113.

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Mohsenin, Tinoosh, and Bevan M. Baas. "A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders." Journal of Signal Processing Systems 61, no. 3 (2010): 329–45. http://dx.doi.org/10.1007/s11265-010-0456-y.

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Psota, Eric, and Lance C. Pérez. "The Manifestation of Stopping Sets and Absorbing Sets as Deviations on the Computation Trees of LDPC Codes." Journal of Electrical and Computer Engineering 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/432495.

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The error mechanisms of iterative message-passing decoders for low-density parity-check codes are studied. A tutorial review is given of the various graphical structures, including trapping sets, stopping sets, and absorbing sets that are frequently used to characterize the errors observed in simulations of iterative decoding of low-density parity-check codes. The connections between trapping sets and deviations on computation trees are explored in depth using the notion ofproblematictrapping sets in order to bridge the experimental and analytic approaches to these error mechanisms. A new iter
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Ismail, Mohamed, Imran Ahmed, and Justin Coon. "Low Power Decoding of LDPC Codes." ISRN Sensor Networks 2013 (January 17, 2013): 1–12. http://dx.doi.org/10.1155/2013/650740.

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Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging
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Wang, Biao. "Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT." Security and Communication Networks 2022 (October 14, 2022): 1–13. http://dx.doi.org/10.1155/2022/4599105.

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As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low s
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Stark, Maximilian, Jan Lewandowsky, and Gerhard Bauch. "Information-Bottleneck Decoding of High-Rate Irregular LDPC Codes for Optical Communication Using Message Alignment." Applied Sciences 8, no. 10 (2018): 1884. http://dx.doi.org/10.3390/app8101884.

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In high-throughput applications, low-complexity and low-latency channel decoders are inevitable. Hence, for low-density parity-check (LDPC) codes, message passing decoding has to be implemented with coarse quantization—that is, the exchanged beliefs are quantized with a small number of bits. This can result in a significant performance degradation with respect to decoding with high-precision messages. Recently, so-called information-bottleneck decoders were proposed which leverage a machine learning framework (i.e., the information bottleneck method) to design coarse-precision decoders with er
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Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-B
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Rozprawy doktorskie na temat "Low-density parity-check Decoders"

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Planjery, Shiva Kumar. "Low-Complexity Finite Precision Decoders for Low-Density Parity-Check Codes." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/605947.

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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California<br>We present a new class of finite-precision decoders for low-density parity-check (LDPC) codes. These decoders are much lower in complexity compared to conventional floating-point decoders such as the belief propagation (BP) decoder, but they have the potential to outperform BP. The messages utilized by the decoders assume values (or levels) from a finite discrete set. We discuss
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Vijayakumar, Suresh Mikler Armin. "FPGA implementation of low density parity check codes decoder." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11003.

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Yang, Lei. "VLSI implementation of low-error-floor multi-rate capacity-approaching low-density parity-check code decoder /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5966.

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Blad, Anton. "Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-69432.

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Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, with uncomplicated arithmetic operations and low accuracy requirements, the random st
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Gunnam, Kiran Kumar. "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1049.

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Selvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.

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A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the sca
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Zhang, Kai. "High-Performance Decoder Architectures For Low-Density Parity-Check Codes." Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-dissertations/17.

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The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted
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Kopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes." Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.

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Hussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes." Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.

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Cai, Fang. "Efficient VLSI Architectures for Non-binary Low Density Parity Check Decoding." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300821245.

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Streszczenia konferencji na temat "Low-density parity-check Decoders"

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Zhang, Z., L. Dolecek, M. Wainwright, V. Anantharam, and B. Nikolic. "Quantization Effects in Low-Density Parity-Check Decoders." In 2007 IEEE International Conference on Communications. IEEE, 2007. http://dx.doi.org/10.1109/icc.2007.1032.

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Chung, Cha-Hao, Yeong-Luh Ueng, Ming-Che Lu, and Mao-Chao Lin. "Adaptive quantization for low-density-parity-check decoders." In Its Applications (Isita2010). IEEE, 2010. http://dx.doi.org/10.1109/isita.2010.5649830.

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Balatsoukas-Stimming, Alexios, Pascal Giard, and Andreas Burg. "Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders." In 2017 IEEE Wireless Communications and Networking Conference Workshops (WCNCW). IEEE, 2017. http://dx.doi.org/10.1109/wcncw.2017.7919106.

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Li, Bohua, Yukui Pei, and Ning Ge. "Area-Efficient Fault-Tolerant Design for Low-Density Parity-Check Decoders." In 2016 IEEE 84th Vehicular Technology Conference (VTC-Fall). IEEE, 2016. http://dx.doi.org/10.1109/vtcfall.2016.7880909.

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Tian Xia, Hsiao-Chun Wu, and Scott C.-H. Huang. "A new stopping criterion for fast low-density parity-check decoders." In 2013 IEEE Global Communications Conference (GLOBECOM 2013). IEEE, 2013. http://dx.doi.org/10.1109/glocom.2013.6831642.

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Ratnayake, Ruwan N. S., Erich F. Haratsch, and Gu-Yeon Wei. "A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders." In IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference. IEEE, 2007. http://dx.doi.org/10.1109/glocom.2007.57.

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Porcello, John C. "Designing and implementing Low Density Parity Check (LDPC) Decoders using FPGAs." In 2014 IEEE Aerospace Conference. IEEE, 2014. http://dx.doi.org/10.1109/aero.2014.6836261.

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Djordjevic, Ivan B. "Cavity quantum electrodynamics based quantum low-density parity-check encoders and decoders." In SPIE OPTO, edited by Zameer U. Hasan, Philip R. Hemmer, Hwang Lee, and Charles M. Santori. SPIE, 2011. http://dx.doi.org/10.1117/12.873975.

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Yin, Dawei, Yuan Liy, Xianbin Wang, et al. "On the Message Passing Efficiency of Polar and Low-Density Parity-Check Decoders." In 2022 IEEE Globecom Workshops (GC Wkshps). IEEE, 2022. http://dx.doi.org/10.1109/gcwkshps56602.2022.10008677.

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Aziz, Syed Mahfuzul, and Sunil Sharma. "New methodologies for high level modeling and synthesis of low density parity check decoders." In 2008 11th International Conference on Computer and Information Technology (ICCIT). IEEE, 2008. http://dx.doi.org/10.1109/iccitechn.2008.4803046.

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