Rozprawy doktorskie na temat „Low latitude current systems”

In spite of being the subject of intense research, several key but complex questions on the nonequilibrium physics of correlated quantum systems remain controversial. For example, the nature of particle and energy transport in different interacting regimes, the relevance of integrability and the impact of environmental coupling are still under active debate. These problems can now be approached numerically, due to the development of powerful algorithms which allow the efficient simulation of the dynamics of correlated systems. In the present thesis we study numerically and analytically the transport properties of low-dimensional quantum systems. In particular, we consider the steady-state spin and energy conduction through XXZ boundary-driven spin-1/2 chains. In the first part, we analyse the transport through chains with only coherent processes in the bulk. For spin transport induced by a magnetisation imbalance between the boundaries, previously identified ballistic, diffusive and negative differential conductivity regimes are reproduced. We provide a comprehensive explanation of the latter. The energy conduction induced by this driving scheme features the same properties as spin transport. For thermally-driven chains, we discuss the nature of energy transport and the emergence of local thermal states when the integrability of the Hamiltonian is broken. In the second part of the thesis we analyse the effect of bulk incoherent effects on the transport properties previously discussed. First we find that for weak particle-particle interactions, pure dephasing degrades spin and energy conduction. In contrast, for strong interactions dephasing induces a significant transport enhancement. We identify the underlying mechanism and discuss its generality. Finally, motivated by the lattice structure of several organic conductors, we study the interplay between coherent and incoherent processes in systems of weakly-coupled chains. We find an enhancement effect due to incoherent interchain hopping, stronger than that by dephasing, which increases with the chain length and relates to superdiffusive transport.

MOS current mode logic (MCML) offers low noise digital circuits that reduce noise that can cripple analog components in mixed-signal integrated circuits, when compared to CMOS digital circuits. An MCML standard cell library was developed for the Cadence Virtuoso Integrated Circuit (IC) design software that gives IC designers the ability to design complex, low noise digital circuits for use in mixed-signal and noise sensitive systems at a high level of abstraction, allowing them to get superior products to market faster than competitors. The MCML standard cell library developed and presented here allows for fast development of mixed signal circuits by providing quiet digital building block gates that reduce the simultaneous switching noise (SSN) by an order of magnitude over conventional CMOS based designs [3]. This thesis project developed the following digital gates in MCML as a standard cell library for general-purpose low noise and very low noise applications: inverter, buffer, NAND, AND, NOR, OR, XOR, NXOR, 2:1 MUX, CMOS to MCML, MCML to CMOS, and double edge triggered flip-flop (DETFF).

The increasing penetration of distributed energy resources, in particular Photovoltaic (PV) production units, and the ever-growing use of power electronics-based equipment has led to specific concern about Power Quality (PQ) in the Low-Voltage (LV) grid. These include high- and low-order current harmonics as well as voltage distortion at the point of common coupling. Solutions to overcome these issues, meeting international grid codes, are being proposed in the context of smart energy management schemes.This work proposes a novel three-phase topology for a PV system with enhanced PQ mitigation functionality, tackling the corresponding control challenges.First, a single-stage current-source inverter PV system with active filtering capability is preferred to the more common two-stage voltage-source inverter topology with additional voltage-step-up converter. The system also guarantees a nearly unitary displacement power factor in the connection to the grid and allows for Maximum Power Point Tracking (MPPT) with direct control of the PV array power. The grid-synchronised dq-axis grid current references are generated for the mitigation of nonlinear load low-order current harmonics, without the need for additional measurements. Active damping is used to minimise grid-side filter losses and reduce high-order harmonics resulting from the converter switching.Results on a 500W laboratory prototype confirm that active damping reduces the switching harmonics in the grid currents and active filtering properly mitigates the low-order current harmonics. The MPPT algorithm works effectively for various irradiance variations. Second, a PV system with a novel Indirect Matrix Converter (IMC)-based unified power quality conditioner topology is developed for enhanced current and voltage compensation capability, with compactness and reliability advantages. PQ issues such as current harmonics, and voltage sags, swells, undervoltage and overvoltage are mitigated by the shunt and series converters, respectively.The more common Space Vector Modulation (SVM) method used in IMCs is developed for this specific topology. In particular, a new shunt converter modulation method is proposed to additionally control the PV array current with zero switching vectors, resulting in a specific switching sequence.A direct sliding mode control method is also studied separately for the shunt and series converters, so that the zero-vector modulation method of the shunt converter can be used, with no sensitive synchronisation of the switching signals; this contrasts with the SVM method. A new dc link voltage modulation method with 12 voltage zones, instead of 6, is proposed to help overcome the limitation in the choice of shunt converter switching vectors due to the positive dc link voltage constraint.Results are obtained for the direct method on a 1 kW laboratory prototype with optimised IMC dc link connection and alternative shunt converter switching transitions to guarantee a positive dc link voltage. Current and voltage compensation capabilities are confirmed by tests in various operating conditions.<br>Doctorat en Sciences de l'ingénieur et technologie<br>info:eu-repo/semantics/nonPublished

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.<br>Dr. Chang-Ho Lee, Committee Member ; Dr . Kevin T Kornegay, Committee Member ; Dr. Emmanouil M Tentzeris, Committee Member ; Dr. Joy Laskar, Committee Chair ; Dr. Oliver Brand, Committee Member.

Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp. The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters. The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.

ABSTRACT Federal regulations have recognized that arc flash hazards are a critical source of potential injury. As a consequence, in order to work on some electrical equipment, the energy source must be completely shut-down. However, power distribution systems in mission critical facilities such as hospitals and data centers must sometimes remain energized while being maintained. In recent years the Arc Flash Hazard Analysis has emerged as a power system tool that informs the qualified technician of the incident energy at the equipment to be maintained and recommends the proper protective equipment to wear. Due to codes, standards and historically acceptable design methods, the Arc Flash Hazard is often higher and more dangerous than necessary. This dissertation presents detailed methodology and proposes alternative strategies to be implemented at the design stage of 600 volt facility power distribution systems which will decrease the Arc Flash Hazard Exposure when compared to widely used code acceptable design strategies. Software models have been developed for different locations throughout a power system. These software model simulations will analyze the Arc Flash Hazard in a system designed with typical mainstream code acceptable methods. The model will be changed to show implementation of arc flash mitigation techniques at the system design level. The computer simulations after the mitigation techniques will show significant lowering of the Arc Flash Hazard Exposure.

In low power, battery-operated, portable applications, like cell phones, PDAs, digital cameras, etc., miniaturization at a low cost is a prominent driving factor behind product development and marketing efforts. As such, power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because, in catering to all combinations of the output capacitor, its equivalent series resistance Resr, and the power inductor resulting from tolerance and modal design targets, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios. Sigma-delta control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide LC-Resr compliance in boost (step-up) converters. This thesis investigates and presents techniques to achieve sigma-delta control in boost converters by essentially using explicit current and voltage control loops. The proposed techniques are developed conceptually and analytical expressions for stability range and transient response are derived. The proposed concepts are validated and quantified through PCB and IC prototypes to yield 1.41 to 6 times faster transient response than the state of the art in current-mode boost supplies, and this without any compromise in LC-Resr compliance range.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.

Eine angemessene Qualität der Elektroenergie ist Grundvoraussetzung für den störungsfreien Betrieb aller angeschlossenen Geräte und Anlagen und spielt in den Verteilungsnetzen moderner Industriegesellschaften wie Deutschland eine zentrale Rolle. Die Elektroenergiequalität (EEQ) wird in Strom- und Spannungsqualität unterteilt. Während die Stromqualität maßgeblich im Verantwortungsbereich der Hersteller von Geräten und Anlagen liegt, sind für die Sicherung einer angemessenen Spannungsqualität im Wesentlichen die Netzbetreiber verantwortlich. Durch die technische Weiterentwicklung bspw. neuer Gerätetechnologien und die zunehmende Integration dezentraler Erzeugungsanlagen wie Photovoltaikanlagen ist zu erwarten, dass die EEQ auch künftig weiter an Bedeutung gewinnt. Die EEQ im Niederspannungsverteilungsnetz ist abhängig von Ort und Zeit und wird durch verschiedene Qualitätskenngrößen beschrieben. Die örtliche und zeitliche Abhängigkeit resultieren aus einer Vielzahl verschiedener Einflussfaktoren, welche sich entweder der elektrischen oder der nicht-elektrischen Umgebung des betrachteten Verteilungsnetzes zuordnen lassen. Die elektrische Umgebung wird durch die Art und Anzahl angeschlossener Verbraucher bzw. Erzeuger (Abnehmer- bzw. Erzeugerstruktur) sowie Struktur und technische Parameter des Verteilungsnetzes (Netzstruktur) bestimmt. Die nicht-elektrische Umgebung umfasst u.a. Einflüsse der klimatischen Umgebung wie bspw. Temperatur oder Globalstrahlung. Ziel dieser Arbeit ist die systematische Identifikation korrelativer Zusammenhänge zwischen den genannten Umgebungseinflüssen und der EEQ sowie deren Quantifizierung auf Basis geeigneter Indizes und Kenngrößen. Die Ergebnisse der Arbeit helfen grundlegende Prinzipien der Ausprägung der Elektroenergiequalität im öffentlichen Verteilungsnetz besser zu verstehen sowie die Verteilungsnetze im Hinblick auf die Elektroenergiequalität zu charakterisieren und zu klassifizieren. Analog zu den Standard-Lastprofilen erfolgt die Definition von Standard-Qualitätsprofilen<br>Power quality levels in public low voltage grids are influenced by many factors which can either be assigned to the electrical environment (connected consumers, connected genera-tion, network characteristics) or to the non-electrical environment (e.g. climatic conditions) at the measurement site. Type and amount of connected consumers (consumer topology) are expected to have a very high impact on power quality (PQ) levels. The generation topology is characterized by number and kind of equipment and generating installations like photovoltaic systems which are connected to the LV grid. The electrical parameters of the grid define the network topology. The parameters which are most suitable to describe each of the three topologies and the climatic environment will be identified. Voltage and current quality in public low voltage (LV) grids vary depending on location and time. They are quantified by a set of different parameters which either belong to events (e.g. dips) or to variations (e.g. harmonics). This thesis exclusively addresses continuous parameters describing variations. Continuous phenomena like harmonics are closely linked to an one-day-cycle which implies a more or less periodic behavior of the continuous power quality parameters. Consumer topologies such as office buildings or residential areas differ in their use of equipment. Time series analysis is used to distinguish between different consumer topologies and to identify characteristic weeks. The clustering of one-day time series is applied to identify characteristic days within the weeks of certain topologies. Based on the results, emission profiles for certain current quality parameters of different consumer topologies will be defined. Due to the characteristic harmonic current emission of certain consumer topologies which represents the typical user behaviour a classification system is developed. It is used to automatically classify the emission profiles of harmonic currents for unknown measurements and to estimate a likely consumer topology. A classification measure is introduced in order to identify unusual or false classified emission profiles. The usage behaviour of equipment by customers usually varies over the year. Subsequently, the levels of PQ parameters like harmonics may show seasonal variations which are identified by using newly defined parameters. The introduction of new device technologies on a large scale like the transition from incandescent to LED lamps might result in long-term changes to the levels of PQ parameters (e.g. harmonics). The analysis of the long-term behavior (trend) will be applied in order to quantify global trends (looking on the measurement duration as a whole) and local trends (looking on individual segments of the whole time series)

碩士<br>雲林科技大學<br>電子與資訊工程研究所<br>97<br>In this thesis, we design two broadband low noise amplifiers (LNAs) for ultra-wideband (UWB) communication systems, which are implemented in TSMC 0.18 μm CMOS technology. The design of the amplifiers concentrates on low power-consumption and low costs as well. The first design utilizes a current topology to save the power and the second design is used two stage cascade topology with a inter-stage network to achieve the high gain performance. In the first section, the measurement of the first LNA shows that the maximum gain is 13.2 dB, 3-dB bandwidth is from 3.1 GHz to 10.6 GHz, the minimum noise figure is 3.33 dB, S11 is less than -10.3dB, IIP3 is better than -3.3 dBm, and the total power consumption is 9.2 mW. The chip size is 0.91 mm2. In the second section, the simulated maximum gain is 13.2 dB, 3-dB bandwidth is from 3.1 GHz to 10.6 GHz, the minimum noise figure is 3.6 dB, S11 is less than -12.4 dB, IIP3 is better than -17 dBm, and the total power consumption is 14.2 mW. The chip size is 1.05 mm2.

碩士<br>國立交通大學<br>資訊科學與工程研究所<br>101<br>In recent years, multiple-input multiple-output (MIMO) technology has been used widely in various communication systems. The main reason is that it can provide the efficiency and quality of data transmission. In addition, the orthogonal-frequency division multiplexing (OFDM) technology provides high-speed data transmission, as well as for operating in multipath over frequency selective fading channels, which has been adopted by many transmission systems. Therefore, the combination of these two technologies in next-generation wireless communication systems, MIMO-OFDM has become one of the most crucial technologies. There are some topics in wireless communication development. First issue is algorithm verification platform development. Second issue is application-specific integrated circuit (ASIC) implementation for low-power design. MIMO-OFDM system is very sensitive to the non-ideal front-end effects so need develop algorithms to solve them. However, only the development of algorithms without hardware to verify the algorithm is not valuable enough. In thesis we integrated a set of self-developed algorithm verification platform. This experimental platform integrated with field programmable gate array (FPGA), digital-to-analog converters (DAC), analog-to-digital converters (ADC), universal serial bus (USB) and radio frequency (RF) hardware module, combined with software graphical user interface (GUI), USB firmware, and comprises of MATLAB algorithms for solving non-ideal channel effects. The 4x4 MIMO-OFDM wireless communication system platforms are realized by combined with software and hardware co-design. Using this prototype platform makes the developed algorithms can accurate analysis and evaluate performance and verification. On the other hand, power consumption is more and more important issue on ASIC implementation. Another part of thesis we propose a dynamic current scaling (DCS) mechanism to achieve low-power design. For example the DCS mechanism is applied to fast Fourier transform (FFT) processor to achieve the 40% power saving.

Or, Pui Ying.<br>"July 2010."<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.<br>Includes bibliographical references.<br>Abstracts in English and Chinese.<br>Acknowledgments<br>Table of Content<br>List of Figures<br>List of Tables<br>List of Publications<br>Chapter Chapter 1 - --- Background of LDO Research<br>Chapter 1.1 --- Structure of a LDO --- p.1-1<br>Chapter 1.2 --- Principle of Operation of LDO --- p.1-2<br>Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3<br>Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3<br>Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4<br>Chapter 1.6 --- An Advanced LDO Structure --- p.1-4<br>Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5<br>References --- p.1-6<br>Chapter Chapter 2 - --- PSRR Analysis<br>Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3<br>Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6<br>Chapter 2.3 --- Conclusion of Chapter --- p.2-12<br>References --- p.2-13<br>Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection<br>Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5<br>Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7<br>Chapter 3.3 --- Experimental Results --- p.3-15<br>Chapter 3.4 --- Conclusion of Chapter --- p.3-21<br>References --- p.3-22<br>Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique<br>Chapter 4.1 --- Proposed LDO --- p.4-3<br>Chapter 4.2 --- Experimental Results --- p.4-7<br>Chapter 4.3 --- Comparison --- p.4-11<br>Chapter 4.4 --- Conclusion of Chapter --- p.4-12<br>Reference --- p.4-13<br>Chapter Chapter 5 - --- Conclusion and Future Work

Finally, the PSRR performance of LDO is studied. An energy-efficient embedded ripple feed-forward path is proposed to improve the PSRR of LDO. Comparing with some state-of-the-art techniques for PSRR improvement, the proposed LDO features very simple structure thus low-power consumption. A LDO implemented in 0.18-mum CMOS technology with 0.042-mm2 active area has been designed to verify the idea. With an external 4.7-muF output capacitor, in the maximum load condition (i.e. at 25 mA), the PSRR is -77 dB at 1 MHz, -85 dB at 2.5 MHz and -55 dB at 5 MHz, respectively. The quiescent current is 15 muA only, while the transient voltage overshoot or undershoot is less than 40 mV when load current changes between 1 mA and 25 mA with 40-ns step time. The LDO achieves good line and load regulations of 3 mV/V and 50 muV/mA, respectively.<br>Remotely- or battery-powered wireless system-on-a-chip (SoC) needs energy-efficient and high-integration power-management solutions due to their energy-aware characteristics. Low-dropout regulator (LDO) is a good solution because of its excellent performances such as low power consumption, fast load-transient response and high power-supply ripple rejection (PSRR). Moreover, it is easy to be fully integrated since no inductor is needed to be the energy-storage element. Recent development of output-capacitorless LDO (OCL-LDO) realizes on-chip, local voltage regulation to enable more effective integrated power management for SoC. In this thesis, OCL-LDOs with low power consumption and fast load-transient response are investigated and presented in this thesis. LDO with output capacitor for high-PSRR operation to provide clean power supply to RF circuits is also reported. Three LDOs are developed and fabricated to verify the proposed ideas.<br>The first design is an ultra low-power voltage regulator for remotely powered energy-autonomous devices. It has been fabricated in a commercial 0.18-mum CMOS technology and applied to a passive UHF RFID tag IC. With the low-power voltage reference circuit and sub-threshold operations, the total quiescent current is 700 nA under a 1.8-V power supply. The output voltage of the regulator is 1.45 V with load capability of 50 muA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/&deg;C, respectively. A POR signal with 150-ns-width pulse is also generated to reset the digital processing part in the tag IC.<br>The second design is a fast-transient OCL-LDO, which has been implemented in a commercial 90-nm CMOS technology. Experimental result verifies that it is stable for a capacitive load from 0 to 50 pF and with load capability of 100 rnA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the power transistor promptly. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 mus. While the measured power consumption is only 6 muW under a 0.75-V supply.<br>Guo, Jianping.<br>Adviser: Ka Nang Leung.<br>Source: Dissertation Abstracts International, Volume: 73-06, Section: B, page: .<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.<br>Includes bibliographical references.<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Abstract also in Chinese.

Eine angemessene Qualität der Elektroenergie ist Grundvoraussetzung für den störungsfreien Betrieb aller angeschlossenen Geräte und Anlagen und spielt in den Verteilungsnetzen moderner Industriegesellschaften wie Deutschland eine zentrale Rolle. Die Elektroenergiequalität (EEQ) wird in Strom- und Spannungsqualität unterteilt. Während die Stromqualität maßgeblich im Verantwortungsbereich der Hersteller von Geräten und Anlagen liegt, sind für die Sicherung einer angemessenen Spannungsqualität im Wesentlichen die Netzbetreiber verantwortlich. Durch die technische Weiterentwicklung bspw. neuer Gerätetechnologien und die zunehmende Integration dezentraler Erzeugungsanlagen wie Photovoltaikanlagen ist zu erwarten, dass die EEQ auch künftig weiter an Bedeutung gewinnt. Die EEQ im Niederspannungsverteilungsnetz ist abhängig von Ort und Zeit und wird durch verschiedene Qualitätskenngrößen beschrieben. Die örtliche und zeitliche Abhängigkeit resultieren aus einer Vielzahl verschiedener Einflussfaktoren, welche sich entweder der elektrischen oder der nicht-elektrischen Umgebung des betrachteten Verteilungsnetzes zuordnen lassen. Die elektrische Umgebung wird durch die Art und Anzahl angeschlossener Verbraucher bzw. Erzeuger (Abnehmer- bzw. Erzeugerstruktur) sowie Struktur und technische Parameter des Verteilungsnetzes (Netzstruktur) bestimmt. Die nicht-elektrische Umgebung umfasst u.a. Einflüsse der klimatischen Umgebung wie bspw. Temperatur oder Globalstrahlung. Ziel dieser Arbeit ist die systematische Identifikation korrelativer Zusammenhänge zwischen den genannten Umgebungseinflüssen und der EEQ sowie deren Quantifizierung auf Basis geeigneter Indizes und Kenngrößen. Die Ergebnisse der Arbeit helfen grundlegende Prinzipien der Ausprägung der Elektroenergiequalität im öffentlichen Verteilungsnetz besser zu verstehen sowie die Verteilungsnetze im Hinblick auf die Elektroenergiequalität zu charakterisieren und zu klassifizieren. Analog zu den Standard-Lastprofilen erfolgt die Definition von Standard-Qualitätsprofilen.<br>Power quality levels in public low voltage grids are influenced by many factors which can either be assigned to the electrical environment (connected consumers, connected genera-tion, network characteristics) or to the non-electrical environment (e.g. climatic conditions) at the measurement site. Type and amount of connected consumers (consumer topology) are expected to have a very high impact on power quality (PQ) levels. The generation topology is characterized by number and kind of equipment and generating installations like photovoltaic systems which are connected to the LV grid. The electrical parameters of the grid define the network topology. The parameters which are most suitable to describe each of the three topologies and the climatic environment will be identified. Voltage and current quality in public low voltage (LV) grids vary depending on location and time. They are quantified by a set of different parameters which either belong to events (e.g. dips) or to variations (e.g. harmonics). This thesis exclusively addresses continuous parameters describing variations. Continuous phenomena like harmonics are closely linked to an one-day-cycle which implies a more or less periodic behavior of the continuous power quality parameters. Consumer topologies such as office buildings or residential areas differ in their use of equipment. Time series analysis is used to distinguish between different consumer topologies and to identify characteristic weeks. The clustering of one-day time series is applied to identify characteristic days within the weeks of certain topologies. Based on the results, emission profiles for certain current quality parameters of different consumer topologies will be defined. Due to the characteristic harmonic current emission of certain consumer topologies which represents the typical user behaviour a classification system is developed. It is used to automatically classify the emission profiles of harmonic currents for unknown measurements and to estimate a likely consumer topology. A classification measure is introduced in order to identify unusual or false classified emission profiles. The usage behaviour of equipment by customers usually varies over the year. Subsequently, the levels of PQ parameters like harmonics may show seasonal variations which are identified by using newly defined parameters. The introduction of new device technologies on a large scale like the transition from incandescent to LED lamps might result in long-term changes to the levels of PQ parameters (e.g. harmonics). The analysis of the long-term behavior (trend) will be applied in order to quantify global trends (looking on the measurement duration as a whole) and local trends (looking on individual segments of the whole time series).