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Gotowe bibliografie tematyczne / Memory and power applications / Artykuły w czasopismach

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Artykuły w czasopismach na temat „Memory and power applications”

Autor: Grafiati

Data publikacji: 7 lipca 2024

Data aktualizacji: 31 lipca 2025

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1

Zhang, Kaiqiang, Dongyang Ou, Congfeng Jiang, Yeliang Qiu, and Longchuan Yan. "Power and Performance Evaluation of Memory-Intensive Applications." Energies 14, no. 14 (2021): 4089. http://dx.doi.org/10.3390/en14144089.

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In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memor

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Kumar, S., M. Santhanalakshmi, and R. Navaneethakrishnan. "Content addressable memory for energy efficient computing applications." Scientific Temper 14, no. 02 (2023): 430–36. http://dx.doi.org/10.58414/scientifictemper.2023.14.2.30.

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Content Addressable Memory (CAM) also known as associate memory isa special kind of semiconductor memory device that works differently from conventional Random Access Memory (RAM). A Content Addressable Memory is a memory unit that matches content over a single clock rather than using addresses. Its inherent parallel search mechanism makes it more advantageous than RAM in terms of speed of search operation. Designers aim to reduce two design characteristics: increasing silicon size and power consumption. As the need for CAM increases, the problem of power consumption also increases. Recent res

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Zuo, Ze Yu, Wei Hu, Rui Xin Hu, Heng Xiong, Wen Bin Du, and Xiu Cai. "Efficient Scratchpad Memory Management for Mobile Multimedia Application." Advanced Materials Research 748 (August 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amr.748.932.

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Mobile devices have been popular in recent years and the proliferation of mobile devices inspires the interest in mobile multimedia applications. However, memory is always the bottleneck in the traditional memory hierarchy. Scratchpad memory (SPM) is a promising on-chip SRAM to solve such problem. It has faster access time and less power-consumption compared to cache and off-chip memory. In this paper, we propose the efficient scratchpad memory management approach for mobile multimedia applications. SPM is partitioned for the assignment of the slices of the applications based on the profiling

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Kumar Lamba, Anil, and Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.

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The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less powe

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Tyler, Neil. "Tempo Targets Low-Power Chips for AI Applications." New Electronics 52, no. 13 (2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61557-8.

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Tatas, K., D. Soudris, and A. Thanailakis. "Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms." Journal of Embedded Computing 1, no. 3 (2005): 353–62. https://doi.org/10.3233/emc-2005-00038.

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An optimization methodology that combines high-level exploration with Register Transfer Level (RTL) design for the power-efficient estimation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. A case study of three popular multimedia kernels is performed for a number of different FPGA devices. Comparisons among implementations w

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Fang, Juan, Jiajia Lu, Mengxuan Wang, and Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.

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With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia an

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Birla, Shilpi. "Variability aware FinFET SRAM cell with improved stability and power for low power applications." Circuit World 45, no. 4 (2019): 196–207. http://dx.doi.org/10.1108/cw-12-2018-0098.

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Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered t

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9

Marchal, P., J. I. Gomez, D. Atienza, S. Mamagkakis, and F. Catthoor. "Power aware data and memory management for dynamic applications." IEE Proceedings - Computers and Digital Techniques 152, no. 2 (2005): 224. http://dx.doi.org/10.1049/ip-cdt:20045077.

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K, Bharathi, and Vijayakumar S. "QCA Design of Encoder for Low Power Memory Applications." International Journal of Electronics and Communication Engineering 3, no. 11 (2016): 13–15. http://dx.doi.org/10.14445/23488549/ijece-v3i11p114.

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Pradeep, Singh Yadav, and Jain Harsha. "Review of 6T SRAM for Embedded Memory Applications." Indian Journal of VLSI Design (IJVLSID) 3, no. 1 (2023): 24–30. https://doi.org/10.54105/ijvlsid.A1217.033123.

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<strong>Abstract:</strong> Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Wri

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Yadav, Pradeep Singh, and Harsha Jain. "Review of 6T SRAM for Embedded Memory Applications." Indian Journal of VLSI Design 3, no. 1 (2023): 24–30. http://dx.doi.org/10.54105/ijvlsid.a1217.033123.

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Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read

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Santoro, Giulia, Giovanna Turvani, and Mariagrazia Graziano. "New Logic-In-Memory Paradigms: An Architectural and Technological Perspective." Micromachines 10, no. 6 (2019): 368. http://dx.doi.org/10.3390/mi10060368.

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Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a

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Kumar, Anurag, and Sheo Kumar. "Memory Architecture: Low-Power Single-Bit Cache." Journal of Futuristic Sciences and Applications 3, no. 2 (2020): 64–72. http://dx.doi.org/10.51976/jfsa.322007.

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Researchers investigated the functionality and efficiency of the single-bit cache memory architecture in terms of numbers. There are three different memory locations in a single-bit cache. A write driver, an SRAM cell, and a sensing amplifier are a few of these parts. SRAM blocks and sensing amplifiers are extensively used in constructing single-bit cache memory to reduce power usage. Both process corner simulation and circuit Monte Carlo simulation have researched their potential applications. It was subsequently determined that a forced stack design was more energy-efficient than a single-bi

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15

Pal, Srijani, Divya S. Salimath, Banusha Chandran, A. Anita Angeline, and V. S. Kanchana Bhaaskaran. "Low Power Memory System Design Using Power Gated SRAM Cell." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (2021): 012008. http://dx.doi.org/10.1088/1757-899x/1187/1/012008.

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Abstract Static Random-Access Memory (SRAM) is widely used in cache memory, microprocessors, general computing applications and electronic circuits involving ASIC, FPGA and CPLD. The most commonly used SRAM is the 6T SRAM. However, it incurs higher power consumption and degraded signal to noise margin (SNM) during write and read operations. To overcome these shortcomings, a single ended power gated 11T SRAM for low power operation is proposed. The power consumption reduction is achieved using power gating through virtual VSS (VVSS) signal and transmission gates. Due to the introduction of tran

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Akdemir, Bayram, and Hasan Üzülmez. "Providing Security of Vital Data for Conventional Microcontroller Applications." Applied Mechanics and Materials 789-790 (September 2015): 1059–66. http://dx.doi.org/10.4028/www.scientific.net/amm.789-790.1059.

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Microcontrollers are widely used in industrial world, and almost all kind of devices were based on microcontroller to achieve high flexibility and abilities. All microcontrollers have nonvolatile and volatile memories to execute the software. During the running, microcontroller calculates many variables and records them to any non-volatile memory to use later. After re-energizing, microcontroller takes the data calculated before the power off and executes the program. In case of any electrical writing error or any power loss during the writing procedure, un-written memory blocks or any un-writ

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Tabbassum, Kavita, Shahnawaz Talpur, and Noor-u.-Zaman Laghari. "Managing Scratchpad Memory Architecture for Lower Power Consumption Using Programming Techniques." Asian Journal of Applied Science and Engineering 9, no. 1 (2020): 79–86. http://dx.doi.org/10.18034/ajase.v9i1.31.

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In embedded systems Scratch memory is generally used as an addition to caches or as a substitute of cache, but due to their comprehensive ease of programmability cache containing architectures are still to be chosen in numerous applications. Power consumption of ported applications can be significantly lowered as well as the portability of scratchpad architectures will be advanced with our suggested language-agnostic software management method. To enhance the memory configuration on relevant architectures, a variety of present methods is reviewed for finding the chances of optimizations and us

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Xue, Xingsi, Aruru Sai Kumar, Osamah Ibrahim Khalaf, et al. "Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications." Electronics 12, no. 4 (2023): 834. http://dx.doi.org/10.3390/electronics12040834.

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Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for both reading and writing operations. There has been a vast technological improvement, which has led to tremendous information on the amount of complexity that can be designed on a single chip. Small feature sizes, low power requirements, low costs, and great performance have emerged as the essential attributes of any electronic component. Designers h

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Datti, VenkataRamana, and Dr P. V. Sridevi. "A Novel Ternary Content Addressable Memory Cell." International Journal of Engineering & Technology 7, no. 4.24 (2018): 67. http://dx.doi.org/10.14419/ijet.v7i4.24.21857.

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Ternary content addressable memories (TCAM) are used for parallel searching. The parallel searching, results high speed but consumes more power. For higher search speed applications, NOR type matchline TCAMs are useful. The NOR type matchline TCAM needs high power; therefore, the power reduction is the major objective of many reported designs. Here, a novel TCAM cell is proposed. The proposed Ternary CAM cell power consumption is 32% lesser than the NOR type matchline TCAM cell. Simulations are performed using cadence 45-nm technology.

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L, Saranya, Abinaya Inbamani, Nivedita A, and Arulanantham D. "Power Reduction in 4T DRAM Cell Using Low Power Topologies." ECS Transactions 107, no. 1 (2022): 5569–75. http://dx.doi.org/10.1149/10701.5569ecst.

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In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic

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Salamy, Hassan, and Semih Aslan. "Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750042. http://dx.doi.org/10.1142/s0218126617500426.

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Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC sys

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Farrahi, Amir H., Gustavo E. Téllez, and Majid Sarrafzadeh. "Exploiting Sleep Mode for Memory Partitioning and Other Applications." VLSI Design 7, no. 3 (1998): 271–87. http://dx.doi.org/10.1155/1998/50491.

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Sleep mode operation and exploiting it to minimize the average power consumption are of great importance in modern VLSI circuits. In general, sleep mode refers to the mode in which part(s) of the system are idle. In this paper, we study the problem of partitioning a circuit according to the activity patterns of its elements such that circuit elements with similar activity patterns are packed into the same partition. Then a partition can be placed in sleep mode during the time intervals all elements contained in that partition are idle. We formulate the partitioning problem to exploit sleep mod

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Kachman, Ondrej, Peter Malík, Marcel Baláž, Libor Majer, and Gábor Gyepes. "A Lightweight and Configurable Flash Filesystem for Low-Power Devices." Journal of Low Power Electronics and Applications 15, no. 2 (2025): 22. https://doi.org/10.3390/jlpea15020022.

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Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient memory utilization essential. This article presents key design concepts for developing an efficient, lightweight, and reliable embedded filesystem. It introduces an improved version of the configurable flash filesystem (CFFS), designed to maximize memory utilization,

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Lai, Chun Sing, Zhekang Dong, and Donglian Qi. "Memristive Devices and Systems: Modeling, Properties and Applications." Electronics 12, no. 3 (2023): 765. http://dx.doi.org/10.3390/electronics12030765.

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The memristor is considered to be a promising candidate for next-generation computing systems due to its nonvolatility, high density, low power, nanoscale geometry, nonlinearity, binary/multiple memory capacity, and negative differential resistance. [...]

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Raghav, Sharma, and B. Ramesh K. "Low Power D Flip-Flop for VLSI Applications." Journal of Optoelectronics and Communication 4, no. 1 (2022): 1–11. https://doi.org/10.5281/zenodo.6387532.

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<em>FF are elementary memory principles and are used to store information. They're used in construction of RAMs, latches, shift registers, counters and other digital circuits. This paper proposes new and innovative designs for D -FF. The designs have power dispersal significantly lower than the former FF designs.</em> <em>In the first proposed design two gated leakage transistors were introduced in the output gate using GALEOR approach. Design is tested for varied substrate bias voltages in sub-threshold region to conclude for better design. Relative simulation results show that area and p

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KOUGIA, STAMATIKI, ALEXANDER CHATZIGEORGIOU, and SPIRIDON NIKOLAIDIS. "EVALUATING POWER EFFICIENT DATA-REUSE DECISIONS FOR EMBEDDED MULTIMEDIA APPLICATIONS: AN ANALYTICAL APPROACH." Journal of Circuits, Systems and Computers 13, no. 01 (2004): 151–80. http://dx.doi.org/10.1142/s0218126604001313.

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Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. The purpose of this paper is to extend an existing power optimizing methodology based on data-reuse decisions, in order to determine the optimal solution in a rapid and reliable way. An analytical approach is proposed by extracting expressions for the number of accesses to each memory layer. Moreover, the design space is further reduced since these analytical expressions are calculated only for a subset of all transformations. The results c

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Konig, R., U. Maurer, and R. Renner. "On the Power of Quantum Memory." IEEE Transactions on Information Theory 51, no. 7 (2005): 2391–401. http://dx.doi.org/10.1109/tit.2005.850087.

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Zhan, Ming, Zhibo Pang, Kan Yu, and Hong Wen. "Reverse Calculation-Based Low Memory Turbo Decoder for Power Constrained Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 6 (2021): 2688–701. http://dx.doi.org/10.1109/tcsi.2021.3068623.

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Singh, Pooran, B. S. Reniwal, V. Vijayvargiya, V. Sharma, and S. K. Vishvakarma. "Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications." Journal of Low Power Electronics 13, no. 1 (2017): 47–59. http://dx.doi.org/10.1166/jolpe.2017.1470.

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Guchang, Han, Huang Jiancheng, Sim Cheow Hin, Michael Tran, and Lim Sze Ter. "Switching methods in magnetic random access memory for low power applications." Journal of Physics D: Applied Physics 48, no. 22 (2015): 225001. http://dx.doi.org/10.1088/0022-3727/48/22/225001.

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Krishna, R., and Punithavathi Duraiswamy. "Low leakage decoder using dual-threshold technique for static random-access memory applications." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 3 (2023): 1420. http://dx.doi.org/10.11591/ijeecs.v30.i3.pp1420-1427.

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Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate bia

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R., Krishna, and Duraiswamy Punithavathi. "Low leakage decoder using dual-threshold technique for static random-access memory applications." Low leakage decoder using dual-threshold technique for static random-access memory applications 30, no. 3 (2023): 1420–27. https://doi.org/10.11591/ijeecs.v30.i3.pp1420-1427.

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Decoders are one of the significant peripheral components of static randomaccess memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate bias

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Yook, Chan-Gi, Jung Nam Kim, Yoon Kim, and Wonbo Shim. "Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications." Micromachines 14, no. 9 (2023): 1753. http://dx.doi.org/10.3390/mi14091753.

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The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages such as a high density and low on-state current, enabling low-power operation, and benefiting from a high level of technological maturity. To achieve high energy efficiency and high accuracy in CIM inference chips, it is necessary to optimize device design by targeting low power consumption at the dev

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Chang, Meng-Fan, Mary Jane Irwin, and Robert Michael Owens. "Power-Area Trade-Offs in Divided Word Line Memory Arrays." Journal of Circuits, Systems and Computers 07, no. 01 (1997): 49–67. http://dx.doi.org/10.1142/s021812669700005x.

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Since on-chip caches account for a significant portion of the power budget of modern microprocessors, low power caches are needed in microprocessors destined for portable electronic applications. A significant portion of the power consumption of caches comes from accessing the cache memory array and most of the power consumption of the memory array comes from driving the bit line pairs (i.e., the column current). Various memory array architectures have been proposed to improve the word line delay and the column current. For example, in a divided word line memory array memory cells in each row

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Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (2020): 1029. http://dx.doi.org/10.3390/electronics9061029.

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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alte

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Tripathi, Tripti, D. S. Chauhan, and S. K. Singh. "Low leakage SRAM cell for ULP applications." International Journal of Engineering & Technology 7, no. 4 (2018): 2521. http://dx.doi.org/10.14419/ijet.v7i4.14028.

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Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed usin

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Rhee, Chae Eun, Seung-Won Park, Jungwoo Choi, Hyunmin Jung, and Hyuk-Jae Lee. "Power-Time Exploration Tools for NMP-Enabled Systems." Electronics 8, no. 10 (2019): 1096. http://dx.doi.org/10.3390/electronics8101096.

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Recently, dramatic improvements in memory performance have been highly required for data demanding application services such as deep learning, big data, and immersive videos. To this end, the throughput-oriented memory such as high bandwidth memory (HBM) and hybrid memory cube (HMC) has been introduced to provide a high bandwidth. For its effective use, various research efforts have been conducted. Among them, the near-memory-processing (NMP) is a concept that utilizes bandwidth and power consumption by placing computation logic near the memory. In the NMP-enabled system, a processor hierarchy

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Gnawali, Krishna Prasad, Seyed Nima Mozaffari, and Spyros Tragoudas. "Low Power Spintronic Ternary Content Addressable Memory." IEEE Transactions on Nanotechnology 17, no. 6 (2018): 1206–16. http://dx.doi.org/10.1109/tnano.2018.2869734.

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Birla, Shilpi. "FinFET SRAM cell with improved stability and power for low power applications." Journal of Integrated Circuits and Systems 14, no. 2 (2019): 1–8. http://dx.doi.org/10.29292/jics.v14i2.57.

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In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage

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Fanariotis, Anastasios, Theofanis Orphanoudakis, and Vassilis Fotopoulos. "Reducing the Power Consumption of Edge Devices Supporting Ambient Intelligence Applications." Information 15, no. 3 (2024): 161. http://dx.doi.org/10.3390/info15030161.

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Having as a main objective the exploration of power efficiency of microcontrollers running machine learning models, this manuscript contrasts the performance of two types of state-of-the-art microcontrollers, namely ESP32 with an LX6 core and ESP32-S3 with an LX7 core, focusing on the impact of process acceleration technologies like cache memory and vectoring. The research employs experimental methods, where identical machine learning models are run on both microcontrollers under varying conditions, with particular attention to cache optimization and vector instruction utilization. Results ind

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ZHAO, WEISHENG, RAPHAEL MARTINS BRUM, LIONEL TORRES, et al. "SPINTRONIC MEMORY-BASED RECONFIGURABLE COMPUTING." SPIN 03, no. 04 (2013): 1340010. http://dx.doi.org/10.1142/s2010324713400109.

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Reconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memor

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Dawwd, Shefa, and Suha Nori. "Reduced Area and Low Power Implementation of FFT/IFFT Processor." Iraqi Journal for Electrical and Electronic Engineering 14, no. 2 (2018): 108–19. http://dx.doi.org/10.37917/ijeee.14.2.3.

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The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors a

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Chen, Ying-Chen, Szu-Tung Hu, Chih-Yang Lin, et al. "Graphite-based selectorless RRAM: improvable intrinsic nonlinearity for array applications." Nanoscale 10, no. 33 (2018): 15608–14. http://dx.doi.org/10.1039/c8nr04766a.

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Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application.

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Maciel, Nilson, Elaine Marques, Lírida Naviner, Yongliang Zhou, and Hao Cai. "Magnetic Tunnel Junction Applications." Sensors 20, no. 1 (2019): 121. http://dx.doi.org/10.3390/s20010121.

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Spin-based devices can reduce energy leakage and thus increase energy efficiency. They have been seen as an approach to overcoming the constraints of CMOS downscaling, specifically, the Magnetic Tunnel Junction (MTJ) which has been the focus of much research in recent years. Its nonvolatility, scalability and low power consumption are highly attractive when applied in several components. This paper aims at providing a survey of a selection of MTJ applications such as memory and analog to digital converter, among others.

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Struharik, Rastislav, and Vuk Vranjković. "Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators." Telfor Journal 12, no. 2 (2020): 116–21. http://dx.doi.org/10.5937/telfor2002116s.

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Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications. Specific CNN computes patterns offer a possibility of significant data reuse, leading to the idea of using specialized on-chip cache memories which enable a significant improvement in power consumption. However, due to the unique caching pattern present within CNNs, standard cache memories would not be efficient. In this paper, a novel on-chip cache memory a

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Rao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, et al. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications." Journal of Electrical and Computer Engineering 2023 (June 7, 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.

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Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory c

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Kotb, Youssef, Islam Elgamal, and Mohamed Serry. "Shape Memory Alloy Capsule Micropump for Drug Delivery Applications." Micromachines 12, no. 5 (2021): 520. http://dx.doi.org/10.3390/mi12050520.

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We introduce a shape memory alloy (SMA) actuated micropump optimized for drug delivery applications. The proposed novel design integrates a built-in replaceable drug reservoir within the pump package forming a self-contained preloaded capsule pump with an overall pump volume of 424.7 μL. The new design results in a compact, simple, and inexpensive micropump and reduces the probability of contamination with attained almost zero dead volume values. The pump consists of NiTi-alloy SMA wires coiled on a flexible polymeric enclosure and actuated by joule heating. Unlike diaphragm and peristaltic SM

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Wang, Chen, Xiuli Zhao, Hao Liu, Xin Chao, Hao Zhu, and Qingqing Sun. "A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application." Electronics 10, no. 16 (2021): 1954. http://dx.doi.org/10.3390/electronics10161954.

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Despite the continuous downscaling of complementary metal–oxide–semiconductor (CMOS) devices, various scenarios of technology have also been proposed toward the shrinking of semiconductor memory. In this paper, a high-density memory (HDM) has been proposed on the basis of band-to-band tunneling (BTBT) for low-power, high density, and high-speed memory applications. The geometric structure and electrical properties have been demonstrated by using TCAD tools. Typical memory operations including read, program, and erase have been designed and performed. High operation speed, lower power consumpti

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Arora, Sneha, and Suman Lata Tripathi. "High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology." Journal of Physics: Conference Series 2327, no. 1 (2022): 012011. http://dx.doi.org/10.1088/1742-6596/2327/1/012011.

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Abstract Graphene nano ribbon field effect transistor is an emerging field of research in VLSI technology beyond 32nm. VLSI main motive is to reduce power consumption and other parameters such as delay, PDP (power delay product) to improve the efficiency. This article discusses the requirement for high-performance applications that use little power. However, employing low-power devices for high-rank applications such as microprocessors, digital signal processors, and static random-access memory (SRAM) is very challenging. In the field of memory design and logical circuit design, it is well rec

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Velichko, Andrei, Dmitry Korzun, and Alexander Meigal. "Artificial Neural Networks for IoT-Enabled Smart Applications: Recent Trends." Sensors 23, no. 10 (2023): 4853. http://dx.doi.org/10.3390/s23104853.

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In the age of neural networks and the Internet of Things (IoT), the search for new neural network architectures capable of operating on devices with limited computing power and small memory size is becoming an urgent agenda [...]

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