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Artykuły w czasopismach na temat „Multiplier Block”

Autor: Grafiati

Data publikacji: 3 czerwca 2025

Data aktualizacji: 31 lipca 2025

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1

Kumar Patel, Beerendra, and Jitendra Kanung. "Diminished-1 multiplier using modulo adder." International Journal of Engineering & Technology 7, no. 4.20 (2018): 31. http://dx.doi.org/10.14419/ijet.v7i4.20.22117.

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In this work Modulo multiplier offers higher computational speed than a normal multiplier. It is frequently used in data security and residue number system. The modulo 122n+1"> has three basic blocks-partial product generation block, inverted end around carry adder tree block and diminished-1 modulo 122n+1"> adder block. The result and an operand use weighted representation and others uses the diminished-1 for the modulo multiplier. The multipliers receive full inputs and avoid (n+1) bits circuits due to diminished-1 number representation. In this work, proposed modulo 122n+1"> multip

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P., Anjali, and Navya Jyothi G. "Design and Performance Analysis of FIR Filter for VLSI Applications." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 530–33. https://doi.org/10.35940/ijeat.B4661.029320.

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The Primary essential basis for planning and realization of Digital signal processor is space improvement and decrease in power utilization. The basic part for arranging and acknowledgment of processor is the FIR Filter. This Filter contains three basic blocks that area unit Adder blocks, memory block and number blocks. The execution of this Filter is basically subjective by the wide assortment that is the moderate block out of all. In this paper, the Filter has been planned using two completely different multipliers particularly Array multiplier and Booth multiplier. An upgrade has been finis

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Pinto, Rohan, and Kumara Shama. "Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder." Journal of Circuits, Systems and Computers 28, no. 02 (2018): 1950019. http://dx.doi.org/10.1142/s0218126619500191.

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Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier “bypass zero feed multiplicand directly,” based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed para

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Savin, Daniela, Sabah Alkass, and Paul Fazio. "Construction resource leveling using neural networks." Canadian Journal of Civil Engineering 23, no. 4 (1996): 917–25. http://dx.doi.org/10.1139/l96-898.

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A neural network model for construction resource leveling is developed and discussed. The model is derived by mapping an augmented Lagrangian multiplier optimization formulation of a resource leveling problem onto a discrete-time Hopfield net. The resulting neural network model consists of two main blocks. Specifically, it consists of a discrete-time Hopfield neural network block, and a control block for the adjustment of Lagrange multipliers in the augmented Lagrangian multiplier optimization, and for the computation of the new set of weights of the neural network block. An experimental verif

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Khubnani, Rashi, Tarunika Sharma, and Chitirala Subramanyam. "Applications of Vedic multiplier - A Review." Journal of Physics: Conference Series 2225, no. 1 (2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.

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Abstract Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison

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Nadibaidze, G. "On the Absolute Summability of Series with Respect to Block-Orthonormal Systems." gmj 6, no. 1 (1999): 83–90. http://dx.doi.org/10.1515/gmj.1999.83.

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Abstract Theorems determining Weyl's multipliers for the summability almost everywhere by the |c, 1| method of the series with respect to block-orthonormal systems are proved. In particular, it is stated that if the sequence {ω(n)} is the Weyl multiplier for the summability almost everywhere by the |c, 1| method of all orthogonal series, then there exists a sequence {Nk } such that {ω(n)} will be the Weyl multiplier for the summability almost everywhere by the |c, 1| method of all series with respect to the Δ k -orthonormal systems.

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Dempster, A. G. "Graphical Design Techniques for Fixed-point Multiplication." VLSI Design 11, no. 4 (2000): 363–79. http://dx.doi.org/10.1155/2000/30196.

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This is a tutorial paper that examines the problem of performing fixed-point constant integer multiplications using as few adders as possible. The driving application is the design of digital filters, where it is often required that several products of a single multiplicand are produced. Thus two specific problems are examined in detail, i.e., the one-input/one-output case and the one-input/several-output case. The latter is of interest because it can take advantage of redundancy in the different coefficient multipliers. Graphical methods can be used to design multipliers in both cases.For the

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8

Shaik, Maznu. "Design and Performance Evaluation of Brent Kung Adder based 8-Bit Vedic Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 825–30. https://doi.org/10.22214/ijraset.2024.65922.

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Multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, design of fast and low power binary multiplier is very important particularly for Digital Signal Processors. Vedic mathematics has improved the performance of multiplier. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably comp

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9

Yan, Aibin, Xuehua Li, Runqi Liu, Zhengfeng Huang, Patrick Girard, and Xiaoqing Wen. "Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata." Electronics 12, no. 14 (2023): 3189. http://dx.doi.org/10.3390/electronics12143189.

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Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the

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10

Belostotskaya, S. O., A. A. Lukyanov, A. S. Roslyakov, A. N. Semenov, and R. A. Fedorov. "Implementation Features of an Analog Multiplier Based on 5529 Series Structured ASIC." Proceedings of Universities. Electronics 26, no. 2 (2021): 154–61. http://dx.doi.org/10.24151/1561-5405-2021-26-2-154-161.

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During the analog signals processing one of the key factors is the reduction of power consumption with high accuracy of signal processing. One way of solving this problem is the implementation of analog IP-blocks. PLLs, AGC, modulators often include the analog signal multipliers. In the paper, the principle of quadratic function cell operation has been described in detail. The analog signal multiplier has been constructed on the basis of the difference of squares arithmetic formula and the considered cell of the quadratic current function. On the basis of the elements of 5529 series structured

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11

Safoev, Nuriddin, and Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata." Electronics 9, no. 6 (2020): 1036. http://dx.doi.org/10.3390/electronics9061036.

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A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed

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Madaka, Venkata Subbaiah, and Umamaheswara Reddy Galiveeti. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1367–78. https://doi.org/10.11591/ijece.v13i2.pp1367-1378.

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In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and sy

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Subbaiah, Madaka Venkata, and Galiveeti Umamaheswara Reddy. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (2023): 1367. http://dx.doi.org/10.11591/ijece.v13i2.pp1367-1378.

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<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circ

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14

Berezin, N. M., I. E. Chernetskaya, V. S. Panishchev, and A. M. Shabarov. "Development of a device for multiplying numbers by means of FPGA." Journal of Physics: Conference Series 2142, no. 1 (2021): 012001. http://dx.doi.org/10.1088/1742-6596/2142/1/012001.

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Abstract The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and developme

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15

Kalimoldayev, M., S. Tynymbayev, M. Ibraimov, M. Magzom, Y. Kozhagulov, and T. Namazbayev. "PIPELINE MULTIPLIER OF POLYNOMIALS MODULO WITH ANALYSIS OF HIGH-ORDER BITS OF THE MULTIPLIER." BULLETIN 386, no. 4 (2020): 13–20. http://dx.doi.org/10.32014/2020.2518-1467.98.

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Among public-key cryptosystems, cryptosystems built on the basis of a polynomial system of residual classes are special. Because in these systems, arithmetic operations are performed at high speed. There are many algorithms for encrypting and decrypting data presented in the form of polynomials. The paper considers data encryption based on the multiplication of polynomials modulo irreducible polynomials. In such a multiplier, the binary image of a multiply polynomial can serve as a fragment of encrypted text. The binary image of the multiplier polynomial is the secret key and the binary repres

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16

Rayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low

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Kurada Verra Bhoga Vasantha Rayudu, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.pp1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low

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Kurada, Verra Bhoga Vasantha Rayudu, Ramachandra Jahagirdar Dhananjay, and Srihari Rao Patri. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (2022): 1–9. https://doi.org/10.11591/csit.v3i1.pp1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low

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19

sundhar, shyam. "Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures." International Scientific Journal of Engineering and Management 03, no. 04 (2024): 1–9. http://dx.doi.org/10.55041/isjem01526.

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The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulatio

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Paradhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan, and Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2." International Journal of Engineering & Technology 7, no. 2.7 (2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.

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Convolution is an algorithm which is mainly used in video, audio and image processing. Convolution calculation is simple in steps however it consumes a lot of memory as well as power in the computational process. It is a mathematical algorithm which is also used in the applications like filtering, edge detection, de-noising, compression etc., as it can be exploit computational power. In this paper, we implemented the speed of discrete linear convolution using robust Vedic multiplier which is one of the fastest multipliers with two finite-length sequences. By implementing convolution with Vedic

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Singamsetti, Mrudula, Sadulla Shaik, and T. Pitchaiah. "Merged Floating Point Multipliers." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 178–82. http://dx.doi.org/10.35940/ijeat.a1042.1291s519.

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Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recogn

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Dattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar, and V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier." Journal of Circuits, Systems and Computers 25, no. 04 (2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.

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Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of parti

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Glushechenko, E. N. "Microstrip doubler microwave with non-traditional implementation." Технология и конструирование в электронной аппаратуре, no. 1-2 (2019): 20–26. http://dx.doi.org/10.15222/tkea2019.1-2.20.

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Frequency multipliers are used in electronic devices to generate spectrally pure sinusoidal signals in the frequency range from a few to tens of GHz. The multipliers are used to multiply the frequency of highly stable but more low-frequency devices with the subsequent extraction of the necessary harmonics from the frequency spectrum of the received microwave range. The frequencies selected after multiplication (set) have significantly higher energy, spectral and range characteristics, which allows them to be used as local oscillators and synthesizers in receiving and transmitting systems. The

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BIEDOVA, OLGA, and VICTORIA STEBLOVSKAYA. "MULTIPLIER OPTIMIZATION FOR CONSTANT PROPORTION PORTFOLIO INSURANCE (CPPI) STRATEGY." International Journal of Theoretical and Applied Finance 23, no. 02 (2020): 2050011. http://dx.doi.org/10.1142/s0219024920500119.

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Constant proportion portfolio insurance (CPPI) strategy is a very popular investment solution which provides an investor with a capital protection as well as allows for an equity market participation. In this paper, we propose a two-step approach to the numerical optimization of the CPPI main parameter, multiplier. First, we identify an admissible range of the multiplier values by controlling the shortfall probability (chosen as a measure of the gap risk). Second, within the admissible range, we choose the optimal multiplier value with respect to the omega ratio (chosen as a performance measur

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Priyanka, C., N. Manoj Kumar, L. Sai Priya, B. Vaishnavi, and M. Rama Krishna. "Low power and high speed GDI based convolution using Vedic multiplier." International Journal of Engineering & Technology 7, no. 2.7 (2018): 733. http://dx.doi.org/10.14419/ijet.v7i2.7.10934.

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Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system. Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of th

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Rodríguez-Villegas, E., M. J. Avedillo, J. M. Quintana, G. Huertas та A. Rueda. "νMOS-based Sorter for Arithmetic Applications". VLSI Design 11, № 2 (2000): 129–36. http://dx.doi.org/10.1155/2000/57240.

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The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8 × 8)-multiplier and a (15, 4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implement

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Guo, Chuliang, Li Zhang, Xian Zhou, et al. "A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (2021): 1–16. http://dx.doi.org/10.1145/3446213.

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Multiplications have been commonly conducted in quantized CNNs, filters, and reconfigurable cores, and so on, which are widely deployed in mobile and embedded applications. Most multipliers are designed to perform multiplications with symmetric bit-widths, i.e., n - by n -bit multiplication. Such features would cause extra area overhead and performance loss when m - by n -bit multiplications ( m > n ) are deployed in the same hardware design, resulting in inefficient multiplication operations. It is highly desired and challenging to propose a reconfigurable multiplier design to accommodate

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Ushanandhini and S. Shivkumar Dr. "Designing of IIR Filter using Radix 4 Multiplier by Precharging Technique." International Journal of Trend in Scientific Research and Development 2, no. 4 (2019): 1100–1107. https://doi.org/10.31142/ijtsrd14208.

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Infinite impulse response IIR filter designs mainly aims on either low area cost or high speed or reduced power consumption. Infinite Impulse Response filters are the most important element in signal processing and communication. IIR filters can achieve a given filtering characteristic using less memory and calculations than a similar FIR filter. Multipliers are the basic building block in DSP, microprocessors and other applications. The system's performance is entirely dependent upon the multipliers because they have large area, long latency and consume considerable power hence there is a

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Masupe, S., and T. Arslan. "Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors." VLSI Design 11, no. 4 (2000): 397–403. http://dx.doi.org/10.1155/2000/34760.

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A generic multiplication scheme for the low power VLSI implementation of the DCT is described in this paper. The scheme concurrently processes blocks of cosine coefficient and pixel values during the multiplication procedure, with the aim of reducing the total switched capacitance within the multiplier circuit. The cosine coefficients, within each block, are manipulated such that some are processed using shift operations only. The remaining coefficients are presented to the multiplier inputs as a sequence, ordered according to bit correlation between successive cosine coefficients. The paper d

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Fan, Quan Run, and Feng Pan. "Technology Mapping for Heterogeneous FPGA in Different EDA Stages." Applied Mechanics and Materials 229-231 (November 2012): 1866–69. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1866.

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In traditional EDA flow, Technology mapping is performed after logic synthesis. Besides programmable logic blocks, heterogeneous FPGAs also have some hard blocks, such as memory block and multiplier, built in it. After logic synthesis, it will be difficult for technology mapping to find sub-circuits that can be implemented in hard blocks. In this paper, a systematic technology mapping approach is proposed. In the design phase, with the support of CAD tools, a module based design approach is used to map some design block to large hard blocks. During register transfer level synthesis, some funct

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Erdogan, A. T., and T. Arslan. "A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters." VLSI Design 15, no. 2 (2002): 529–35. http://dx.doi.org/10.1080/1065514021000012147.

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A combined coefficient segmentation and block processing algorithm for low power implementation of FIR digital filters is described in this paper. The algorithm processes data and coefficients in blocks of fixed sizes. During the manipulation of each block, coefficients are segmented into two primitive components. The accumulative effect of processing a sequence of blocks and segmentation results in up to 80% reduction in power consumption in the multiplier circuit compared to conventional filtering. The paper describes the implementation of the algorithm, its constituent components, and the p

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Bojjawar, Satish, and Prabhu G. Benakop. "VLSI Implementation of Low Power FIR Filter using Variable Precision Two-Dimensional Pipeline Gating Multiplier." YMER Digital 21, no. 08 (2022): 66–75. http://dx.doi.org/10.37896/ymer21.08/08.

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The low-power FIR filter is required for many DSP applications. The crucial and powerhungry block in the filter is a multiplier. To implement the low power FIR filter a twodimensional variable precision fine-grain pipeline gating technique is introduced in the multiplier. The optimized multiplier is used to implement the transposed form-based FIR filter for the order N = 8 in ASIC design tools from Cadence in CMOS 45nm Technology. The designed FIR filter is compared with the existing multiplier-based FIR filters. The power-saving is achieved by the proposed filter is 22% without any degradatio

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Sambale, Benjamin. "Isotypies for the quasisimple groups with exceptional Schur multiplier." Journal of Algebra and Its Applications 16, no. 04 (2017): 1750078. http://dx.doi.org/10.1142/s0219498817500785.

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Let [Formula: see text] be a block with abelian defect group [Formula: see text] of a quasisimple group [Formula: see text], such that [Formula: see text] has exceptional Schur multiplier. We show that, [Formula: see text] is isotypic to its Brauer correspondent in [Formula: see text] in the sense of Broué. The proof uses methods from a previous paper [B. Sambale, Broué’s isotypy conjecture for the sporadic groups and their covers and automorphism groups, Internat. J. Algebra Comput. 25 (2015) 951–976], and relies ultimately on computer calculations. Moreover, we verify the Alperin–McKay conje

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Mohammad, Nasiruddin, S. Sharma Prashant, and S. Chourasia Vijay. "Implementation of Optimized 64x64-bit Vedic Multiplier." Journal of Switching Hub 4, no. 3 (2019): 31–38. https://doi.org/10.5281/zenodo.3582202.

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<em>The need of high speed multiplier is increasing day by day because of high speed computer applications. The multiplication process consumes significantly more time for calculation. This computation time must be reducing in order to increase the speed of the system. In this paper, we have proposed a high speed 64x64-bit Vedic Multiplier by making use of Urdhava Tiryakbhyam Sutra of Vedic mathematics. Urdhva-Tiryagbhyam is the most efficient algorithm which provides high speed multiplication of numbers of any size. Multiplier is one of the important hardware block in most Digital Signal Proc

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Pavlidis, Archimedes, and Dimitris Gizopoulos. "Fast quantum modular exponentiation architecture for Shor's factoring alogrithm." Quantum Information and Computation 14, no. 7&8 (2014): 649–82. http://dx.doi.org/10.26421/qic14.7-8-8.

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We present a novel and efficient, in terms of circuit depth, design for Shor's quantum factorization algorithm. The circuit effectively utilizes a diverse set of adders based on the Quantum Fourier transform (QFT) Draper's adders to build more complex arithmetic blocks: quantum multiplier/accumulators by constants and quantum dividers by constants. These arithmetic blocks are effectively architected into a quantum modular multiplier which is the fundamental block for the modular exponentiation circuit, the most computational intensive part of Shor's algorithm. The proposed modular exponentiati

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Nadibaidze, G. "On the Rearranged Block-Orthonormal Systems." Georgian Mathematical Journal 7, no. 1 (2000): 169–77. http://dx.doi.org/10.1515/gmj.2000.169.

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Abstract A condition is established for the sequence {Nk } when there exists a rearrangement of functions of the block-orthonormal system {φn } such that the sequence {log2 n} ({(log log n)2}) is a Weyl multiplier for the convergence (for the summability by the methods (C, α) (α > 0)) almost everywhere of series with respect to the rearranged system {φνn }.

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Aaron D’costa, Mr, Dr Abdul Razak, and Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters." International Journal of Engineering & Technology 7, no. 3 (2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.

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Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so

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Singh, Gurpadam, and Neelam R. Prakash. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of

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Gurpadam, Singh, and R. Prakash Neelam. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1874–81. https://doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of

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Vikash, Pawar, and Shukla Seema. "Enhancing Speed by Optimizing Power and Delay in 4 Bit RALU Utilizing TSG GATE." Research and Applications: Emerging Technologies 3, no. 2 (2021): 11–15. https://doi.org/10.5281/zenodo.5375858.

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<em>In today's world, the Reversible arithmetic logic unit (RALU) is one of the very important parts of any system with multiple uses in computers, mobile devices, pocket calculators, etc. Reversible logic is useful in mechanical applications of nanotechnology, by eliminating sliding contact, particles in a limited volume can be significantly reduced.</em><em> Adders and multipliers are the basic building blocks of many computing units. We have implemented a reversible arithmetic logic unit (RALU) based on reversible adders, subtractors, multipliers, and comparators. The reversible adder a

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Tchendjeu, A. E. Tchahou, R. Tchitnga, and H. B. Fotsin. "FPGA Implementation of Linear Congruential Generator Based on Block Reduction Technique." Journal of Circuits, Systems and Computers 27, no. 10 (2018): 1850154. http://dx.doi.org/10.1142/s0218126618501542.

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This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA based on block reduction technique. The circuit is derived from LCG algorithm proposed by Lehmer. Block reduction technique has been used to simplify the circuit. Several net connections among the blocks of the circuit are ignored or disconnected and the multiplier is replaced by a shifter. Simulations of both behavior and timing have been done and the results confirm its algorithm. The Cyclone II EP2C8Q208C8N and Cyclone IV E EP4CE115F29C7N of Altera have been chosen to extract comparison data

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Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.

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The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). T

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Nandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a

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Lakshmaiah, Gangadharaiah Soralamavu, Narayanappa Chikkajala Krishnappa, Poornima Golluchinnappanahalli Ramappa, Divya Muddenahally Narasimhaiah, Umesharaddy Radder, and Chakali Chandrasekhar. "Efficient power optimized very-large-scale integration architecture of proportionate least mean square adaptive filter." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 2 (2025): 2513. https://doi.org/10.11591/ijece.v15i2.pp2513-2522.

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The focus on power optimization in embedded systems is especially important for embedded applications since it has brought in many methods and factors that are necessary for developing systems that are both power- and area-efficient. In contrast to the current delayed wavelet μ-law proportionate least mean square (DWMPLMS) and delayed least mean square (DLMS) algorithms, this work offers the development of adaptive filters based on the least mean square (LMS) method, which improves power and timing performance. In order to improve area and time efficiency, the proportionate least mean square (

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Lakshmaiah, Gangadharaiah Soralamavu, Narayanappa Chikkajala Krishnappa, Poornima Golluchinnappanahalli Ramappa, Divya Muddenahally Narasimhaiah, Umesharaddy Radder, and Chakali Chandrasekhar. "Efficient power optimized very-large-scale integration architecture of proportionate least mean square adaptive filter." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 2 (2025): 2513–22. https://doi.org/10.11591/ijece.v15i2.pp2513-2522.

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The focus on power optimization in embedded systems is especially important for embedded applications since it has brought in many methods and factors that are necessary for developing systems that are both power- and area-efficient. In contrast to the current delayed wavelet μ-law proportionate least mean square (DWMPLMS) and delayed least mean square (DLMS) algorithms, this work offers the development of adaptive filters based on the least mean square (LMS) method, which improves power and timing performance. In order to improve area and time efficiency, the proportionate least mean squar

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46

Khachab, Nabil I., Abdallah Cherri, and Ahmad Hayssam. "A Versatile General Multiplier Divider Cell by Using Operational Trans-Resistance Amplifiers." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 4, no. 8 (2017): 01–09. http://dx.doi.org/10.53555/nneee.v4i8.161.

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In this paper, we present the design of a versatile general multiplier-divider cell by using the Operational Trans-resistance Amplifier (OTRA) and MOSFETs operating in the linear region. The design and the basic operation of this block is verified. Other operations can also be realized by simply choosing the inputs of the signals at the different terminals. These operations include square root operation, scalar vector multiplier and modulation to name a few. The new cell is reconfigurable and can be programmed by DC voltages. The resulting circuits are simulated by 0.18 m CMOS process through

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Jaiwanglok, Anurak, Kei Eguchi, Krit Smerpitak, and Amphawan Julsereewong. "Modification of Cockcroft–Walton-Based High-Voltage Multipliers with 220 V and 50 Hz Input for Non-Thermal Food Processing Apparatus." Sustainability 12, no. 16 (2020): 6330. http://dx.doi.org/10.3390/su12166330.

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A design of high-voltage multipliers to generate underwater shockwaves is one of the most important factors for successfully providing non-thermal food processing in a cost-effective manner. To be capable of fully utilizing the Cockcroft–Walton-based high-voltage multipliers for underwater shockwave generation, this paper presents a topological modification of three interesting design approaches in bipolar structure for 220 V and 50 Hz AC input to generate more than 3.5 kV DC output within short time periods. In addition to Cockcroft–Walton multipliers (CWMs), the first modified scheme employs

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He, Jinzhong, Ming Zhang, Jian Xu, Lina Yu, and Weijun Li. "Optimizing CNN Hardware Acceleration with Configurable Vector Units and Feature Layout Strategies." Electronics 13, no. 6 (2024): 1050. http://dx.doi.org/10.3390/electronics13061050.

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Convolutional neural network (CNN) hardware acceleration is critical to improve the performance and facilitate the deployment of CNNs in edge applications. Due to its efficiency and simplicity, channel group parallelism has become a popular method for CNN hardware acceleration. However, when processing data involving small channels, there will be a mismatch between feature data and computing units, resulting in a low utilization of the computing units. When processing the middle layer of the convolutional neural network, the mismatch between the feature-usage order and the feature-loading orde

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Yi, Myeong‐Jong, Jung‐Ho Kim, and Seung‐Hwan Chung. "Enhancing the resolving power of least‐squares inversion with active constraint balancing." GEOPHYSICS 68, no. 3 (2003): 931–41. http://dx.doi.org/10.1190/1.1581045.

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Most geophysical inverse problems are solved using least‐squares inversion schemes with damping or smoothness constraints to improve stability and convergence rate. Since the Lagrangian multiplier controls resolution and stability of the inverse problem, we always want to use the optimum multiplier, which is not easy to get and is usually obtained by experience or a time‐consuming optimization process. We present a new regularization approach, in which the Lagrangian multiplier is set as a spatial variable at each parameterized block and automatically determined via the parameter resolution ma

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Vodopyanov, M. A., K. A. Menzorov, V. V. Davydov, and V. Yu Rud. "Method for reducing phase fluctuations of a precision frequency response meter for microwave quantum generators." Journal of Physics: Conference Series 2086, no. 1 (2021): 012071. http://dx.doi.org/10.1088/1742-6596/2086/1/012071.

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Abstract The principle of operation of the device for measuring frequency characteristics is considered. Block diagram of a device for measuring the frequency characteristics of a digital frequency comparator with correlation quadrature processing and description of their components is illustrated. The block diagram of the frequency multiplier is given. The accuracy characteristics of the developed meter design are evaluated. They are compared with the characteristics of previously used devices. The Improve accuracy characteristics and increased stability of operation were found.

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