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Artykuły w czasopismach na temat „Multiplierless Filter”

Autor: Grafiati

Data publikacji: 3 czerwca 2025

Data aktualizacji: 31 lipca 2025

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1

Yagain, Deepa, and A. Vijaya Krishna. "Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool." VLSI Design 2014 (July 24, 2014): 1–18. http://dx.doi.org/10.1155/2014/280701.

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Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPG

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2

Pavlovic, Vlastimir, Dejan Milic, and Jelena Djordjevic-Kozarov. "Shape of impulse response characteristics of linear-phase nonrecursive 2D FIR filter function." Facta universitatis - series: Electronics and Energetics 26, no. 2 (2013): 133–43. http://dx.doi.org/10.2298/fuee1302133p.

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An analytical method for the new class of linear-phase multiplierless 2D FIR filter functions generated by applying the Christoffel-Darboux formula for classical Chebyshev polynomials of the first and the second kind, proposed in [6] was used for designing of linear-phase multiplierless 2D FIR filter described in this paper. Correct transformation from continuous two-dimensional domain into the z domains without residuum and without errors is described. The proposed solution high selectivity is a filter function in the z1 domain, and the Hilbert transformer in the z2 domain. The impulse respon

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3

Macleod, M. D., and A. G. Dempster. "Multiplierless FIR filter design algorithms." IEEE Signal Processing Letters 12, no. 3 (2005): 186–89. http://dx.doi.org/10.1109/lsp.2004.842270.

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4

LIAN, YONG. "A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (2003): 643–54. http://dx.doi.org/10.1142/s0218126603001069.

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This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that

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5

Ye, Wenbin. "Multiplierless Multiple-Stage Cascaded FIR Filter Design." Journal of Circuits, Systems and Computers 24, no. 01 (2014): 1550011. http://dx.doi.org/10.1142/s0218126615500115.

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It is well known that multiplierless finite impulse response (FIR) filters in multiple-stage cascade form can achieve lower hardware cost and lower coefficient sensitivity than that of single stage design. In this work, a novel algorithm is proposed for the design of multiplierless multiple-stage cascaded FIR filters. Unlike to the conventional algorithms in which the number of stages is fixed and usually is fixed to two, the number of stage in the proposed algorithm is automatically determined. The design examples show that the proposed algorithm significantly outperforms the best existing al

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6

Aparna, A., and T. Vigneswaran. "DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (2017): 66. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19564.

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This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirem

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7

Pan, Shing-Tai. "CSD-Coded Genetic Algorithm on Robustly Stable Multiplierless IIR Filter Design." Mathematical Problems in Engineering 2012 (2012): 1–15. http://dx.doi.org/10.1155/2012/560650.

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A Canonic-Signed-Digit-(CSD-) coded genetic algorithm (GA) is proposed to find the optimal design of robustly stable infinite impulse response digital filter (IIR). Under the characteristics of the CSD structure, the circuit of the filter can be simplified and also the calculation speed can be raised to increase the hardware’s efficiency. However, the design of CSD has a big challenge: the CSD structure of the system parameters will be destroyed by an optimal design procedure. To solve this problem, in this research a CSD-coded GA is proposed so that the CSD structure can be maintained. Moreov

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8

Huang, Q., and G. S. Moschytz. "Analog multiplierless LMS adaptive FIR filter structures." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 40, no. 12 (1993): 790–94. http://dx.doi.org/10.1109/82.260244.

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9

Lutovac, M. D., and L. D. Milic. "Approximate linear phase multiplierless IIR halfband filter." IEEE Signal Processing Letters 7, no. 3 (2000): 52–53. http://dx.doi.org/10.1109/97.823523.

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10

Ye, Wen Bin, and Ya Jun Yu. "Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 11 (2014): 3206–15. http://dx.doi.org/10.1109/tcsi.2014.2327287.

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11

Djordjevic-Kozarov, Jelena, and Vlastimir Pavlovic. "A novel analytical method for the selective multiplierless linear-phase 2D FIR filter function." Facta universitatis - series: Electronics and Energetics 29, no. 4 (2016): 689–700. http://dx.doi.org/10.2298/fuee1604689d.

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In this paper, a novel analytical method for new class of selective linear-phase two-dimensional (2D) finite impulse response (FIR) filter functions generated by applying a new modified 2D Christoffel-Darboux formula for classical orthogonal Chebyshev polynomials of the first and the second kind is proposed. Fundamental research proposed in this paper is also illustrated by examples of 2D FIR filter and adequate comparison with new class of multiplierless linear-phase 2D FIR filter function given in the literature.

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12

Pavlović, V. D., D. S. Antić, S. S. Nikolić, and S. Lj Perić. "Low complexity lowpass linear‐phase multiplierless FIR filter." Electronics Letters 49, no. 18 (2013): 1133–35. http://dx.doi.org/10.1049/el.2013.1791.

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13

Barsainya, Richa, Meenakshi Agarwal, and Tarun Kumar Rawat. "Design and FPGA implementation of multiplierless comb filter." International Journal of Circuit Theory and Applications 45, no. 11 (2017): 1497–513. http://dx.doi.org/10.1002/cta.2324.

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14

Tai, Y. L., and T. P. Lin. "Design of multiplierless FIR filters by multiple use of the same filter." Electronics Letters 28, no. 2 (1992): 122. http://dx.doi.org/10.1049/el:19920075.

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15

Rao, Chaolin, and Xin Lou. "Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation." Electronics 11, no. 11 (2022): 1721. http://dx.doi.org/10.3390/electronics11111721.

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In multiplierless finite impulse response (FIR) filters, the product accumulation block (PAB) could be the major contributor to hardware complexity, especially for high-order filters. In this paper, an optimization scheme where the constant multiplication block and the PAB are jointly optimized at the bit-level is proposed to minimize the hardware complexity. In the proposed joint optimization, the multiple constant multiplications (MCM) block is rearranged into several MCM sub-blocks. The products are summed locally before accumulation to reduce the word-length of the structural adders. It is

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16

Hounsell, B. I., and T. Arslan. "Programmable multiplierless digital filter array for embedded SoC applications." Electronics Letters 37, no. 12 (2001): 735. http://dx.doi.org/10.1049/el:20010516.

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17

Fernandez-Vazquez, Alfonso, and Gordana Jovanovic Dolecek. "Maximally Flat CIC Compensation Filter: Design and Multiplierless Implementation." IEEE Transactions on Circuits and Systems II: Express Briefs 59, no. 2 (2012): 113–17. http://dx.doi.org/10.1109/tcsii.2011.2180093.

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18

Rahiman, P. F. Khaleelur, and V. S. Jayanthi. "Low Power Adder Based Auditory Filter Architecture." Scientific World Journal 2014 (2014): 1–6. http://dx.doi.org/10.1155/2014/709149.

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Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is

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19

P.V, Siji, and Manju Manuel. "2-D IIR Spatially Bandpass Beam Filter- A Multiplierless Realization." IARJSET 2, no. 10 (2015): 87–90. http://dx.doi.org/10.17148/iarjset.2015.21018.

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20

Kim, Seehyun. "Compressive Sensing of the FIR Filter Coefficients for Multiplierless Implementation." Journal of the Korea Institute of Information and Communication Engineering 18, no. 10 (2014): 2375–81. http://dx.doi.org/10.6109/jkiice.2014.18.10.2375.

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21

Samueli, H. "A low-complexity multiplierless half-band recursive digital filter design." IEEE Transactions on Acoustics, Speech, and Signal Processing 37, no. 3 (1989): 442–44. http://dx.doi.org/10.1109/29.21716.

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22

Lutovac, Budimir M., and Miroslav D. Lutovac. "Design and VHDL description of Multiplierless Half-Band IIR Filter." AEU - International Journal of Electronics and Communications 56, no. 5 (2002): 348–50. http://dx.doi.org/10.1078/1434-8411-54100114.

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23

Dhabal, Supriya, and Palaniandavar Venkateswaran. "Efficient Cosine Modulated Filter Bank Using Multiplierless Masking Filter and Representation of Prototype Filter Coefficients Using CSD." International Journal of Image, Graphics and Signal Processing 4, no. 10 (2012): 25–33. http://dx.doi.org/10.5815/ijigsp.2012.10.04.

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24

Zhao, S. H., and S. C. Chan. "Design and Multiplierless Realization of Digital Synthesis Filters for Hybrid-Filter-Bank A/D Converters." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 10 (2009): 2221–33. http://dx.doi.org/10.1109/tcsi.2008.2012213.

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25

Monteiro, Marcio, Ismael Seidel, José Luis Güntzel, Mateus Grellert, Leonardo Soares, and Cristina Meinhardt. "A Design Space Exploration of Power-efficient Gaussian Filter Architectures using Logical Optimization and Approximated Adders." Journal of Integrated Circuits and Systems 18, no. 2 (2023): 1–12. http://dx.doi.org/10.29292/jics.v18i2.702.

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Gaussian filtering is an important step in many image-processing applications because it reduces image noise.However, this step is also compute-intensive, so power-optimized hardware architectures are necessary to allow its adoption in embedded devices. This work presents a design space exploration of power-efficient Gaussian filter architectures.Differently from related work, this work shows the impacts of the design decisions on two target applications: the Canny Algorithm and an Automatic License Plate Recognition system.To explore the design space, the 3x3, 5x5, and 7x7kernels were logical

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26

Jovanovic Dolecek, Gordana, and Gabriel Alejandro Martinez Novelo. "Design and FPGA Implementation of Compensator for Sharpening CIC Filter." IOP Conference Series: Materials Science and Engineering 1298, no. 1 (2023): 012017. http://dx.doi.org/10.1088/1757-899x/1298/1/012017.

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Abstract This paper presents a novel compensator design for sharpened CIC (cascade-integrator-comb) proposed in the literature. Sharpened CIC provides higher aliasing attenuation than the CIC filter. However, its passband droop is higher than the corresponding CIC filter and must be compensated. Our motivation was to design a decimator with better compensation than the one proposed in the literature. The proposed decimation filter has two coefficients and six adders. The coefficients are determined using particle swarm optimization (PSO) in MATLAB. Two designs are presented. The first one has

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27

Sharma, Ila, Anil Kumar, Girish Kumar Singh, and Heung‐No Lee. "Design of multiplierless prototype filter for two‐channel filter bank using hybrid method in FCSD space." IET Circuits, Devices & Systems 11, no. 1 (2017): 29–40. http://dx.doi.org/10.1049/iet-cds.2016.0124.

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28

Martins, Wallace A., Mysore R. Bhavani Shankar, and Bjorn Ottersten. "Oversampled DFT-Modulated Biorthogonal Filter Banks: Perfect Reconstruction Designs and Multiplierless Approximations." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 11 (2020): 2777–81. http://dx.doi.org/10.1109/tcsii.2019.2962462.

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29

Kotteri, K. A., A. E. Bell, and J. E. Carletta. "Design of Multiplierless, High-Performance, Wavelet Filter Banks With Image Compression Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 3 (2004): 483–94. http://dx.doi.org/10.1109/tcsi.2003.820234.

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30

Aliasgari, Mohammad, Yeganeh M. Marghi, Mohammadreza Baharani, and Sied Mehdi Fakhraie. "Multiplierless filter-bank based multicarrier system by using canonical signed digit representation." Wireless Communications and Mobile Computing 16, no. 5 (2014): 563–77. http://dx.doi.org/10.1002/wcm.2553.

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31

Jassim M. Abdul-Jabbar, Dr, and Abdulhamed M. Jasim. "Design and MultiPlierless Realization of ECG- Based Gaussian Wavelet Filter with Lattice Structures_ENG." AL-Rafdain Engineering Journal (AREJ) 21, no. 2 (2013): 66–77. http://dx.doi.org/10.33899/rengj.2013.72855.

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32

Kotteri, K. A., A. E. Bell, and J. E. Carletta. "Multiplierless filter Bank design: structures that improve both hardware and image compression performance." IEEE Transactions on Circuits and Systems for Video Technology 16, no. 6 (2006): 776–80. http://dx.doi.org/10.1109/tcsvt.2006.876360.

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33

Chan, S. C., W. Liu, and K. L. Ho. "Multiplierless perfect reconstruction modulated filter banks with sum-of-powers-of-two coefficients." IEEE Signal Processing Letters 8, no. 6 (2001): 163–66. http://dx.doi.org/10.1109/97.923040.

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34

Jovanovic-Dolecek, Gordana. "Design of multiplierless comb compensators with magnitude response synthesized as sinewave functions." Facta universitatis - series: Electronics and Energetics 33, no. 1 (2020): 1–14. http://dx.doi.org/10.2298/fuee2001001j.

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This paper presents a research on design of multiplierless comb compensators with magnitude response synthesized as sinewave functions. First, it is elaborated the importance of comb decimation filter and why we need its compensator. In continuation are presented some favorable characteristics of comb compensator. The compensators, with magnitude characteristic synthesized as sinewave functions fulfill those favorable characteristics. Next, are described some most important results on design of compensators with sinewave-based magnitude responses including single and cascaded sinewave-based fu

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35

ZHANG, WEI, MARK YEARY, J. Q. TRELEWICZ, and MONTE TULL. "EFFICIENT COMPUTATION OF MULTIPLIERLESS FILTERS IN EMBEDDED SYSTEMS EMPLOYING AN OPTIMAL APPROXIMATION METHOD." International Journal of Computational Methods 03, no. 02 (2006): 177–204. http://dx.doi.org/10.1142/s0219876206000801.

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An integerization technique for creating fixed integer transforms with computationally optimal representations is presented, and the improved performance in embedded systems by employing these integerized implementations is explored. This technique uses an optimal approximation algorithm that finds the lowest-length fractional representation of the rational numbers. The integer transform approximation allows multiplication to be replaced by shift-and-add operations in hardware systems; where multiplication can take several cycles, shifts and adds take one or fewer cycles each. The multiplierle

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36

Sajwan, N., I. Sharma, A. Kumar, and L. K. Balyan. "Performance of Multiplierless FIR Filter Based on Directed Minimal Spanning Tree: A Comparative Study." Circuits, Systems, and Signal Processing 39, no. 11 (2020): 5776–800. http://dx.doi.org/10.1007/s00034-020-01433-7.

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37

Kwan, H. K., and C. L. Chan. "Circularly symmetric two-dimensional multiplierless FIR digital filter design using an enhanced McClellan transformation." IEE Proceedings G Circuits, Devices and Systems 136, no. 3 (1989): 129. http://dx.doi.org/10.1049/ip-g-2.1989.0022.

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38

M. Abdul-Jabbar, Jassim, and Rasha Waleed Hamad. "Design and Multiplierless Implementations of9th order linear-PhaseBireciprocal Lattice Wave Digital Wavelet Filter Banks -eng." AL-Rafdain Engineering Journal (AREJ) 21, no. 4 (2013): 68–88. http://dx.doi.org/10.33899/rengj.2013.77276.

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M. Abdul-Jabbar, Jassim, and Waleed Hamad. "Design and Multiplierless Implementations of9th order linear-PhaseBireciprocal Lattice Wave Digital Wavelet Filter Banks - eng." AL-Rafdain Engineering Journal (AREJ) 21, no. 4 (2013): 68–88. http://dx.doi.org/10.33899/rengj.2013.77406.

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40

Kumar, A., I. Sharma, and L. K. Balyan. "Design of low power multiplierless FIR filter with enhanced adder efficiency using flower pollination optimization." Applied Acoustics 174 (March 2021): 107792. http://dx.doi.org/10.1016/j.apacoust.2020.107792.

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41

Pavlovic, Vlastimir D., and Jelena R. Djordjevic‐Kozarov. "Ultra‐selective spike multiplierless linear‐phase two‐dimensional FIR filter function with full Hilbert transform effect." IET Circuits, Devices & Systems 8, no. 6 (2014): 532–42. http://dx.doi.org/10.1049/iet-cds.2013.0432.

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42

M. Jasim, Abdulhamed, and Jassim M. Abdul-Jabbar. "Design and Multiplierless Implementations of ECG-Based 1st Order Gaussian Derivative Wavelet Filter with Lattice Structures." Journal of University of Anbar for Pure Science 6, no. 2 (2012): 124–34. http://dx.doi.org/10.37652/juaps.2012.63369.

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43

M. Abdul-Jabbar, Jassim, and Rasha Waleed Hmad. "Allpass-Based Design, Multiplierless Realization and Implementation of IIR Wavelet Filter Banks with Approximate Linear Phase (English)." AL-Rafdain Engineering Journal (AREJ) 20, no. 5 (2012): 16–25. http://dx.doi.org/10.33899/rengj.2012.61025.

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Chan, S. C., and K. S. Yeung. "On the Design and Multiplierless Realization of Perfect Reconstruction Triplet-Based FIR Filter Banks and Wavelet Bases." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 8 (2004): 1476–91. http://dx.doi.org/10.1109/tcsi.2004.832795.

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45

Djordjevic-Kozarov, Jelena R., and Vlastimir D. Pavlovic. "An Analytical Method for the Multiplierless 2-D FIR Filter Functions and Hilbert Transform in $z2$ Domain." IEEE Transactions on Circuits and Systems II: Express Briefs 60, no. 8 (2013): 527–31. http://dx.doi.org/10.1109/tcsii.2013.2268340.

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Shyu, Jong-Jy, and Ying-Ta Ho. "The Lagrange multiplier approach to the design of multiplierless two-channel two-dimensional linear-phase FIR filter banks." Signal Processing 45, no. 3 (1995): 389–95. http://dx.doi.org/10.1016/0165-1684(95)00065-l.

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47

Chakraborty, Anirban, and Ayan Banerjee. "A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic." Journal of Circuits, Systems and Computers 29, no. 09 (2020): 2050151. http://dx.doi.org/10.1142/s0218126620501510.

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Dedicated hardware for “Discrete Wavelet Transform” (DWT) is at high demand for real-time imaging operations in any standalone electronic devices, as DWT is being extensively utilized for most of the transform-domain imagery applications. Various DWT algorithms exist in the literature facilitating its software implementations which are generally unsuitable for real-time imaging in any stand-alone devices due to their power intensiveness and huge computation time. In this paper, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented.

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48

Jovanovic Dolecek, Gordana, and Alfonso Fernandez-Vazquez. "Improving Passband Characteristics in Chebyshev Sharpened Comb Decimation Filters." Applied Sciences 14, no. 23 (2024): 11421. https://doi.org/10.3390/app142311421.

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This work presents the design of optimal and multiplierless compensators for Chebyshev sharpened comb decimation filters. The narrowband and wideband compensators are proposed. For the narrowband, the compensator with a magnitude response is proposed in a sinusoidal form, while for the wideband, two compensators with magnitude responses of two sinusoidal functions are introduced. The optimum design is performed using particle swarm optimization (PSO), while the multiplierless design is realized by presenting optimum parameters in a signed-power-of-two (SPT) form. Unlike the methods in the lite

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49

Maskell, D. L. "Design of efficient multiplierless FIR filters." IET Circuits, Devices & Systems 1, no. 2 (2007): 175. http://dx.doi.org/10.1049/iet-cds:20060201.

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50

Yurdakul, Arda. "Multiplierless implementation of 2-D FIR filters." Integration 38, no. 4 (2005): 597–613. http://dx.doi.org/10.1016/j.vlsi.2004.10.003.

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