Gotowe bibliografie tematyczne / NAND logic elements

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Gotowa bibliografia na temat „NAND logic elements”

Autor: Grafiati

Data publikacji: 5 czerwca 2025

Data aktualizacji: 2 sierpnia 2025

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Artykuły w czasopismach na temat "NAND logic elements"

Stojanovic, Milan, Dragan Nikic, and Darko Stefanovic. "Implicit-OR tiling of deoxyribozymes: Construction of molecular scale OR, NAND and four-input logic gates." Journal of the Serbian Chemical Society 68, no. 4-5 (2003): 321–26. http://dx.doi.org/10.2298/jsc0305321s.

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We recently reported the first complete set of molecular-scale logic gates based on deoxyribozymes. Here we report how we tile these logic gates and construct new logic elements: OR, NAND, and the first element with four inputs (i1^i5)V(i2^i6). Tiling of logic gates was achieved through a common substrate used for core deoxyribozyme; degradation of this substrate defines the output. This kind of connection between logic gates is an implicit- OR tiling, because it suffices that one componenet of the network is active for the whole network to give an output of 1.

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Nam, Hyoungsik, Young-In Kim, Jina Bae, and Junhee Lee. "GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning." Electronics 10, no. 9 (2021): 1032. http://dx.doi.org/10.3390/electronics10091032.

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This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the improvement on the learning speed. The GateRL consists of an agent for the action and an environment for state, mask, and reward. State and reward are generated from a connection matrix that describes the current circuit configuration, and the mask is obtained from a masking matrix based on constraints

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Illiberi, Andrea, Alessandra Leonhardt, Matthew Surman, et al. "New Materials for Memory Applications by Atomic Layer Deposition." ECS Meeting Abstracts MA2023-02, no. 29 (2023): 1437. http://dx.doi.org/10.1149/ma2023-02291437mtgabs.

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The architectures of integrated logic and memory devices have shifted from 2D to 3D layouts, enabling a continued scaling of device densities. Atomic layer deposition (ALD) allows the conformal deposition of thin films with sub-nm thickness control on high aspect ratio 3D structures. ALD has become the technique of choice for the synthesis of an increasing number of materials in advanced logic and memory devices. In the first part of this presentation, we briefly review some of the key ALD processes which enable the fabrication of state-of-the-art 3D-NAND and 2D-DRAM. Next, we present the ALD

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Chen, Zibo, Ryan D. Kibler, Andrew Hunt, et al. "De novo design of protein logic gates." Science 368, no. 6486 (2020): 78–84. http://dx.doi.org/10.1126/science.aay2790.

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The design of modular protein logic for regulating protein function at the posttranscriptional level is a challenge for synthetic biology. Here, we describe the design of two-input AND, OR, NAND, NOR, XNOR, and NOT gates built from de novo–designed proteins. These gates regulate the association of arbitrary protein units ranging from split enzymes to transcriptional machinery in vitro, in yeast and in primary human T cells, where they control the expression of the TIM3 gene related to T cell exhaustion. Designed binding interaction cooperativity, confirmed by native mass spectrometry, makes th

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Emir, Recep, Dilek Surekci Yamacli, Serhan Yamacli, and Sezai Alper Tekin. "Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology." Electronics 13, no. 15 (2024): 2993. http://dx.doi.org/10.3390/electronics13152993.

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The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the

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Giri, Santosh, and Basanta Joshi. "Multilayer Backpropagation Neural Networks for Implementation of Logic Gates." International Journal of Computer Science & Engineering Survey 12, no. 1 (2021): 1–12. http://dx.doi.org/10.5121/ijcses.2021.12101.

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ANN is a computational model that is composed of several processing elements (neurons) that tries to solve a specific problem. Like the human brain, it provides the ability to learn from experiences without being explicitly programmed. This article is based on the implementation of artificial neural networks for logic gates. At first, the 3 layers Artificial Neural Network is designed with 2 input neurons, 2 hidden neurons & 1 output neuron. after that model is trained by using a backpropagation algorithm until the model satisfies the predefined error criteria (e) which set 0.01 in this ex

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Liu, Houquan, Hongchang Deng, Shijie Deng, Chuanxin Teng, Ming Chen, and Libo Yuan. "Vortex Beam Encoded All-Optical Logic Gates Based on Nano-Ring Plasmonic Antennas." Nanomaterials 9, no. 12 (2019): 1649. http://dx.doi.org/10.3390/nano9121649.

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Vortex beam encoded all-optical logic gates are suggested to be very important in future information processing. However, within current logic devices, only a few are encoded by using vortex beams and, in these devices, some space optical elements with big footprints (mirror, dove prism and pentaprism) are indispensable components, which is not conducive to device integration. In this paper, an integrated vortex beam encoded all-optical logic gate based on a nano-ring plasmonic antenna is proposed. In our scheme, by defining the two circular polarization states of the input vortex beams as the

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Mladenov, Valeri. "Application of Metal Oxide Memristor Models in Logic Gates." Electronics 12, no. 2 (2023): 381. http://dx.doi.org/10.3390/electronics12020381.

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Memristors, as new electronic elements, have been under rigorous study in recent years, owing to their good memory and switching properties, low power consumption, nano-dimensions and a good compatibility to present integrated circuits, related to their promising applications in electronic circuits and chips. The main purpose of this paper is the application and analysis of the operations of metal–oxide memristors in logic gates and complex schemes, using several standard and modified memristor models and a comparison between their behavior in LTSPICE at a hard-switching, paying attention to t

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Goldsworthy, Victoria, Geneva LaForce, Seth Abels, and Emil Khisamutdinov. "Fluorogenic RNA Aptamers: A Nano-platform for Fabrication of Simple and Combinatorial Logic Gates." Nanomaterials 8, no. 12 (2018): 984. http://dx.doi.org/10.3390/nano8120984.

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RNA aptamers that bind non-fluorescent dyes and activate their fluorescence are highly sensitive, nonperturbing, and convenient probes in the field of synthetic biology. These RNA molecules, referred to as light-up aptamers, operate as molecular nanoswitches that alter folding and fluorescence function in response to ligand binding, which is important in biosensing and molecular computing. Herein, we demonstrate a conceptually new generation of smart RNA nano-devices based on malachite green (MG)-binding RNA aptamer, which fluorescence output controlled by addition of short DNA oligonucleotide

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Hassan, Ahmad, Jean-Paul Noël, Yvon Savaria, and Mohamad Sawan. "Circuit Techniques in GaN Technology for High-Temperature Environments." Electronics 11, no. 1 (2021): 42. http://dx.doi.org/10.3390/electronics11010042.

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As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilli

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Części książek na temat "NAND logic elements"

Sundararajan, Gopalakrishnan. "Fault Tolerance in Carbon Nanotube Transistors Based Multi Valued Logic." In Carbon Nanotubes - Redefining the World of Electronics [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.95361.

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This Chapter presents a solution for fault-tolerance in Multi-Valued Logic (MVL) circuits comprised of Carbon Nano-Tube Field Effect Transistors (CNTFET). This chapter reviews basic primitives of MVL and describes ternary implementations of CNTFET circuits. Finally, this chapter describes a method for error correction called Restorative Feedback (RFB). The RFB method is a variant of Triple-Modular Redundancy (TMR) that utilizes the fault masking capabilities of the Muller C element to provide added protection against noisy transient faults. Fault tolerant properties of Muller C element is disc

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Streszczenia konferencji na temat "NAND logic elements"

Doi, Takashi, and Joseph W. Goodman. "Application of MQW devices to Boolean logic operations." In OSA Annual Meeting. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.fbb3.

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We present a method for implementing Boolean logic operations using MQW optical devices and a spatial pattern coding. Serially connected MQW devices such as an S-SEED have some advantages: high speed switching capability, a tolerance to fluctuation of power sources, and logic operation capability. Therefore, if cascadability of logic can be maintained with these devices, we can build high speed optical logic circuits. In this study, we adopted a spatial pattern coding method, which represents logical values (1 or 0) as combinations of bright and dark cells, on both input and output sides as a

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Avishai, A., A. Buxbaum, D. Klochkov, J. T. Neumann, T. Korb, and E. Foca. "Visualization and Measurements of 3D Structures in Memory and Logic Devices." In ISTFA 2019. ASM International, 2019. http://dx.doi.org/10.31399/asm.cp.istfa2019p0209.

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Abstract This paper describes the application of 3D FIB-SEM tomography as a method for quantifying process variations across the die and across the wafer, as well as layout investigations. In this study, the analysis of results acquired by 3D FIB-SEM tomography were applied to a 64L 3D-NAND device where process induced variation in the high aspect ratio vertical memory channels is measured and to a double stack 3D-NAND architecture, which is comprised of two 32-layer stacks where eccentricity of the pillars was evaluated for layers in both upper and lower stacks. In addition, a partial layout

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Mizsei, J., J. Lappalainen, and I. Ulbert. "Thermal electronic logic circuit as neuromorphic element." In 2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2018. http://dx.doi.org/10.1109/nano.2018.8626264.

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Yan, Yingming, B. Zhang, and Shigu Cao. "Many-Valued Logic-Memory Elements Based on Nano-Scale Electromechanical Oscillators." In 2023 Photonics & Electromagnetics Research Symposium (PIERS). IEEE, 2023. http://dx.doi.org/10.1109/piers59004.2023.10221296.

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Dagesyan, Sarkis A., Denis Presnov, Serafima Y. Ryzhenkova, et al. "Fabrication of electrodes for a logic element based on a disordered dopant atoms network." In The International Conference on Micro- and Nano-Electronics 2018, edited by Vladimir F. Lukichev and Konstantin V. Rudenko. SPIE, 2019. http://dx.doi.org/10.1117/12.2522487.

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Proie, Robert M., Ronald G. Polcawich, Jeffrey S. Pulskamp, Tony Ivanov, and Mona Zaghloul. "Nano-electromechanical storage element for a low power complimentary logic architecture using PZT relays." In TRANSDUCERS 2011 - 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference. IEEE, 2011. http://dx.doi.org/10.1109/transducers.2011.5969633.

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Grachev, A. A., and A. B. Sadovnikov. "VOLTAGE-CONTROLLED MULTI-BAND FILTRATION OF SPIN WAVES IN MULTIFERROIC STRUCTURES." In Actual problems of physical and functional electronics. Ulyanovsk State Technical University, 2024. http://dx.doi.org/10.61527/appfe-2024.268-270.

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This work presents the findings of a study investigating the propagation of spin waves in a multiferroic structure comprising two periods, which is subjected to elastic deformations. Radiophysical measurements were employed to obtain data on the transmission and dispersion characteristics of spin waves at varying configurations of the external electric field applied to the piezoelectric layer. It was demonstrated that the formation of forbidden zones in the spectrum of spin waves and alterations in the transmission coefficient of spin waves are contingent upon the configuration of the electric

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Hyungtae Kim, Seongjin Yeon, and Kwangseok Seo. "New NRZ-mode resonant tunneling bistable-to-monostable-to-bistable transition logic element operating up to 36 Gb/s." In 2007 7th IEEE Conference on Nanotechnology (IEEE-NANO). IEEE, 2007. http://dx.doi.org/10.1109/nano.2007.4601418.

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Ke, Changhong, and Horacio D. Espinosa. "A Feedback Controlled Carbon Nanotube Based NEMS Device: Concept and Modeling." In ASME 2004 International Mechanical Engineering Congress and Exposition. ASMEDC, 2004. http://dx.doi.org/10.1115/imece2004-60065.

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A switchable carbon nanotube based nano-electromechanical systems (NEMS) device with close-loop feedback is examined. The device is made of a conductive multi-walled carbon nanotube (MWNT) placed as a cantilever over a micro-fabricated step. A bottom electrode, power supply and a resistor are also parts of the device circuit. The pull-in/pull-out and tunneling characteristics of the device are investigated by means of an electro-mechanical analysis. The model includes the concentration of electrical charge, at the end of the nanocantilever, and the van der Waals force. Finite kinematics accoun

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Phillips, Jonathon, Zayd C. Leseman, Joseph Cordaro, Claudia Luhrs, and Marwan Al-Haik. "Novel Graphitic Structures by Design." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-42977.

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Graphitic Structures by Design (GSD) is a novel technology for growing graphite in precise patterns from the nano to the macroscale, rapidly (&gt;1 layer/sec), at low temperatures (ca. 500°C), and in a single step using ordinary laboratory equipment. The GSD process consists of exposing particular metals (Ni, Pd, Pt, Co), which act as ‘templates’, to a fuel rich combustion environment. As an example, we have thoroughly characterized graphite growth on nickel in a mixture of ethylene and oxygen (O2/C2H4 ratio&lt;3), and found that it grows in a geometry remarkably consistent with the sh

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