Gotowe bibliografie tematyczne / Parity checker

Spis treści

  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
  5. Streszczenia konferencji
  6. Raporty organizacyjne

Gotowa bibliografia na temat „Parity checker”

Autor: Grafiati
Data publikacji: 3 czerwca 2025
Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "Parity checker"

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A.Anjana. "Even and Odd Parity Generator and Checker using the Reversible logic gates." International Journal of Computer Science and Engineering Communications 1, no. 1 (2013): 62–66. https://doi.org/10.5281/zenodo.821766.

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Digital data transmission is the mostly used in the communication. The data transmission from source to destination should be without loss of information. This is made possible by using the method of parity generator and parity checker. The parity checker and the parity generator are of two types they are even parity generator and parity checker, odd parity generator and checker. Reversible logic gates compremises various parameters in the data transmission. There are various reversible logic gates to meet the needs of the parity generator and parity checker. Reversible gates probably reduce t
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Tarnick, Steffen. "Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability." VLSI Design 5, no. 4 (1998): 347–56. http://dx.doi.org/10.1155/1998/67574.

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In self-checking systems, checkers usually do not receive all code words during normal operation. Missing code words may prevent a checker from achieving the totally self-checking property. The paper presents a novel approach to the design of embedded parity and two-rail checkers that allows a checker to receive all code words irrespective of the set of code words that is provided by the functional circuit. A checker gets all code words by an LFSR while at the same time it monitors the output of the functional circuit. Additionally, the LFSR is able to capture the error patterns of noncode wor
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Battula, Brahmaiah, Valeti SaiLakshmi, Karpurapu Sunandha, S. Durga Sri Sravya, Putta Vijaya Lakshmi, and S. Navya Sri. "Design a Low Power and High Speed Parity Checker using Exclusive–or Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 4 (2021): 121–25. http://dx.doi.org/10.35940/ijitee.d8522.0210421.

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In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by
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Brahmaiah, Battula*, SaiLakshmi Valeti, Durga Sri Sravya S., Vijaya Lakshmi Putta, Sunandha Karpurapu, and Navya Sri S. "Design a Low Power and High Speed Parity Checker using Exclusive or Gates." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 4 (2021): 121–25. https://doi.org/10.35940/ijitee.D8522.0210421.

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In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by
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B.Y., Galadima G.S.M Galadanci S.M. Gana A. Tijjani M. Ibrahim. "QCA Based Design of Reversible Parity Generator and Parity Checker Circuits for Telecommunication." NIPES Journal of Science and Technology Research 5, no. 2 (2023): 331–43. https://doi.org/10.5281/zenodo.8070398.

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<em>Quantum-dot cellular automation (QCA) is a transistor-free technology used to implement nanoscale circuit designs. When compared to the widely used complementary metal oxide semiconductor (CMOS) technology, QCA circuits are faster, denser, and use less energy. It has some advantages in reversible logic, including its small size and low power dissipation. In this work, a model of a low-power 3-bit odd parity generator and checker circuit based on a reversible Feynman gate with 23 cells and 40 cells, respectively, is proposed. The proposed reversible odd parity generator and checker circuit
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Campbell, Earl T., and Mark Howard. "Magic state parity-checker with pre-distilled components." Quantum 2 (March 14, 2018): 56. http://dx.doi.org/10.22331/q-2018-03-14-56.

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Magic states are eigenstates of non-Pauli operators. One way of suppressing errors present in magic states is to perform parity measurements in their non-Pauli eigenbasis and postselect on even parity. Here we develop new protocols based on non-Pauli parity checking, where the measurements are implemented with the aid of pre-distilled multiqubit resource states. This leads to a two step process: pre-distillation of multiqubit resource states, followed by implementation of the parity check. These protocols can prepare single-qubit magic states that enable direct injection of single-qubit axial
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Liu, Zilong, Xiaosuo Wu, Huifu Xiao, et al. "On-chip optical parity checker using silicon photonic integrated circuits." Nanophotonics 7, no. 12 (2018): 1939–48. http://dx.doi.org/10.1515/nanoph-2018-0140.

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AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonator
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Poustie, A. J., K. J. Blow, A. E. Kelly, and R. J. Manning. "All-optical parity checker with bit-differential delay." Optics Communications 162, no. 1-3 (1999): 37–43. http://dx.doi.org/10.1016/s0030-4018(99)00070-x.

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Yasasvi, Bhargava, Charu Rana, and Pankaj Rakheja. "Implementation of Parity Checker Using CMOS Logic Techniques." International Journal of Advance Research and Innovation 6, no. 2 (2018): 31–34. http://dx.doi.org/10.51976/ijari.621806.

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The technology is growing rapidly where the sizes of the components are getting reduced as the size gets decreased the, possibility of errors gets increased. These errors can’t be prevented as they are generated in the running phase. To handle such problems, we need a circuit which will be monitoring continuously and correcting the errors generated. This paper proposes different ways to implement a parity checker in the previous self-checking register. When compared with previous techniques. The circuits are stimulated in spice using 90nm CMOS technology.
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Han, Bingchen, Junyu Xu, Pengfei Chen, et al. "All-Optical Non-Inverted Parity Generator and Checker Based on Semiconductor Optical Amplifiers." Applied Sciences 11, no. 4 (2021): 1499. http://dx.doi.org/10.3390/app11041499.

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An all-optical non-inverted parity generator and checker based on semiconductor optical amplifiers (SOAs) are proposed with four-wave mixing (FWM) and cross-gain modulation (XGM) non-linear effects. A 2-bit parity generator and checker using by exclusive NOR (XNOR) and exclusive OR (XOR) gates are implemented by first SOA and second SOA with 10 Gb/s return-to-zero (RZ) code, respectively. The parity and check bits are provided by adjusting the center wavelength of the tunable optical bandpass filter (TOBPF). A saturable absorber (SA) is used to reduce the negative effect of small signal clock
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Rozprawy doktorskie na temat "Parity checker"

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Adhikari, Dikshya. "The Role of Eigenvalues of Parity Check Matrix in Low-Density Parity Check Codes." Thesis, University of North Texas, 2020. https://digital.library.unt.edu/ark:/67531/metadc1707297/.

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The new developments in coding theory research have revolutionized the application of coding to practical systems. Low-Density Parity Check (LDPC) codes form a class of Shannon limit approaching codes opted for digital communication systems that require high reliability. This thesis investigates the underlying relationship between the spectral properties of the parity check matrix and LDPC decoding convergence. The bit error rate of an LDPC code is plotted for the parity check matrix that has different Second Smallest Eigenvalue Modulus (SSEM) of its corresponding Laplacian matrix. It is found
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Guo, Feng. "Low density parity check coding." Thesis, University of Southampton, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.419159.

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Pirou, Florent. "Low-density Parity-Check decoding Algorithms." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2160.

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<p>Recently, low-density parity-check (LDPC) codes have attracted much attention because of their excellent error correcting performance and highly parallelizable decoding scheme. However, the effective VLSI implementation of and LDPC decoder remains a big challenge and is a crucial issue in determining how well we can exploit the benefits of the LDPC codes in the real applications. In this master thesis report, following a error coding background, we describe Low-Density Parity-Check codes and their decoding algorithm, and also requirements and architectures of LPDC decoder implementations.</
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Meidan, Amir. "Linear-time encodable low-density parity-check codes." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0006/MQ40942.pdf.

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Sharifi, Tehrani Saeed. "Stochastic decoding of low-density parity-check codes." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=97010.

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Low-Density Parity-Check (LDPC) codes are one of the most powerful classes of error-control codes known to date. These codes have been considered for many recent digital communication applications. In this dissertation, we propose stochastic decoding of state-of-the-art LDPC codes and demonstrate it as a competitive approach to practical LDPC decoding algorithms.In stochastic decoding, probabilities are represented as streams of random bits using Bernoulli sequences in which the information is contained in the statistics of the bit stream. This representation results in low hardware-complexity
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Davey, M. C. "Error-correction using low-density parity-check codes." Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598305.

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Gallager's low-density parity-check codes are defined by sparse parity-check matrices, usually with a random contruction. Such codes have near Shannon limit performance when decoded using an iterative probabilistic decoding algorithm. We report two advances that improve the error-correction performance of these codes. First, defining the codes over non-binary fields we can obtain a 0.6 dB improvement in signal to noise ratio for a given bit error rate. Second, using irregular parity-check matrices with non-uniform row and column weights we obtain gains of up to 0.5 dB. The empirical error-corr
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Rankin, David Michael. "Single parity check product codes and iterative decoding." Thesis, University of Canterbury. Electrical and Computer Engineering, 2001. http://hdl.handle.net/10092/1084.

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The aim of coding theory is to design codes which can achieve the fundamental limits of communication [52] and yet are simple to implement. On average randomly constructed codes can achieve this goal, but with a decoding complexity that is impractical. Consequently, highly structured codes with practical decoding algorithms have been extensively studied. Unfortunately the vast majority of these codes do not approach capacity. Recent advances involving simple 'random like' codes with practical iterative decoding algorithms have closely approached capacity as the blocklength increases. This the
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Hayes, Bob. "LOW DENSITY PARITY CHECK CODES FOR TELEMETRY APPLICATIONS." International Foundation for Telemetering, 2007. http://hdl.handle.net/10150/604497.

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ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada<br>Next generation satellite communication systems require efficient coding schemes that enable high data rates, require low overhead, and have excellent bit error rate performance. A newly rediscovered class of block codes called Low Density Parity Check (LDPC) codes has the potential to revolutionize forward error correction (FEC) because of the very high coding rates. This paper presents a bri
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Moon, Todd K., and Jacob H. Gunther. "AN INTRODUCTION TO LOW-DENSITY PARITY-CHECK CODES." International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/607470.

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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>Low-Density Parity-Check (LDPC) codes are powerful codes capable of nearly achieving the Shannon channel capacity. This paper presents a tutorial introduction to LDPC codes, with a detailed description of the decoding algorithm. The algorithm propagates information about bit and check probabilities through a tree obtained from the Tanner graph for the code. This paper may be useful as a supplement in a course on error-control coding or digital communication.
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Anitei, Irina. "Circular Trellis based Low Density Parity Check Codes." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1226513009.

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Książki na temat "Parity checker"

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Gallagher, Robert G. Low-density parity-check codes. MIT-Press, 2003.

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Gallager, Robert G. Low-density parity-check codes. M.I.T. Press, 2005.

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Rovini, Massimo. Low-density parity-check codes: A tutorial. ESA Publications Division, 2004.

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Meidan, Amir. Linear-time encodable low-density parity-check codes. National Library of Canada, 1998.

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Park, Eun-Young Christina. New decoding algorithms for regular low-density parity-check codes. National Library of Canada, 2002.

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Johnson, Sarah J. Iterative error correction: Turbo, low-density parity-check and repeat-accumulate codes. Cambridge University Press, 2009.

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Castura, Jeff. Performance analysis and optimization of reduced complexity low density parity check decoding algorithms. National Library of Canada, 2000.

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Mantha, Ramesh. Hybrid automatic repeat request schemes using turbo codes and low density parity check codes. National Library of Canada, 1999.

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Ssemogerere, Paul K. Reality check: Political party financing in Uganda : a critical analysis in reference to other countries. Konrad Adenauer Stiftung, 2011.

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Ssemogerere, Paul K. Reality check: Political party financing in Uganda : a critical analysis in reference to other countries. Konrad Adenauer Stiftung, 2011.

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Części książek na temat "Parity checker"

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Wang, Kuifu, and Jingfeng Yan. "Research on the Method of Parity Checker Design Based on Evolvable Hardware." In Communications in Computer and Information Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23235-0_16.

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Mukherjee, Sudipta, Anindya Jana, and Subir Kumar Sarkar. "Hybrid Single Electron Transistor Based Low Power Consuming Odd Parity Generator and Parity Checker Circuit in 22 nm Technology." In Computational Intelligence in Data Mining - Volume 1. Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-2205-7_50.

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Gupta, Monica, Kirti Gupta, Vijay Kumar, Rachna Narula, and Surinder Kaur. "Design of memristor-CMOS-based hybrid parity generator-checker for error detection in communication systems." In Advances in Electrical and Computer Technologies. CRC Press, 2025. https://doi.org/10.1201/9781003515470-27.

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Chattopadhyay, Tanay. "1D Periodic Nonlinear Model and Using It to Design All-Optical Parity Generator Cum Checker Circuit." In Advances in Terahertz Technology and Its Applications. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5731-3_8.

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Khan, Imran Ahmed, and Md Rashid Mahmood. "Design and Analysis of Power-Efficient Carbon Nanotube-Based Parity Checker Circuits for High-Data Transmission Rate." In Lecture Notes in Networks and Systems. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8512-5_63.

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Tan, Yong Kiam, Jiong Yang, Mate Soos, Magnus O. Myreen, and Kuldeep S. Meel. "Formally Certified Approximate Model Counting." In Computer Aided Verification. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-65627-9_8.

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AbstractApproximate model counting is the task of approximating the number of solutions to an input Boolean formula. The state-of-the-art approximate model counter for formulas in conjunctive normal form (CNF), $$\textsf{ApproxMC}$$ ApproxMC , provides a scalable means of obtaining model counts with probably approximately correct (PAC)-style guarantees. Nevertheless, the validity of $$\textsf{ApproxMC}$$ ApproxMC ’s approximation relies on a careful theoretical analysis of its randomized algorithm and the correctness of its highly optimized implementation, especially the latter’s stateful inte
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Weik, Martin H. "parity check." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_13637.

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Weik, Martin H. "transverse parity check." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_20098.

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Weik, Martin H. "longitudinal parity check." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_10637.

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Weik, Martin H. "parity-check coding." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_13638.

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Streszczenia konferencji na temat "Parity checker"

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Ju, Hyosang, Siwon Jang, and Sang-Hyo Kim. "On the Design of Parity-Check Polar Codes." In 2024 15th International Conference on Information and Communication Technology Convergence (ICTC). IEEE, 2024. https://doi.org/10.1109/ictc62082.2024.10827520.

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Gaurav, Prashant, Prashant, Sangeeta Singh, and Saurabh Kumar Pandey. "Parity Generator & Parity Checker Using Sub-threshold Adiabatic Logic." In 2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE, 2020. http://dx.doi.org/10.1109/upcon50219.2020.9376407.

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Kumar, Dharmendra, Chintoo Kumar, Shipra Gautam, and Debasis Mitra. "Design of Practical Parity Generator and Parity Checker Circuits in QCA." In 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS). IEEE, 2017. http://dx.doi.org/10.1109/inis.2017.16.

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Mondal, Samanwita, Saptaparna Ghosh, Aditi Singha Mahapatra, Deblina Roy, Prerona Sanyal, and Aloke Saha. "Novel 32nm CMOS Ternary Parity Generator-Checker." In 2022 International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON). IEEE, 2022. http://dx.doi.org/10.1109/mesiicon55227.2022.10093548.

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Vanlalchaka, Reginald H., and Soumik Roy. "Power efficient odd parity generator & checker circuits." In 2013 1st International Conference on Emerging Trends and Applications in Computer Science (ICETACS). IEEE, 2013. http://dx.doi.org/10.1109/icetacs.2013.6691397.

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Abdalla, Yasser, and Sherif Sharroush. "A Novel Compact and High-Speed CMOS Parity Generator/Checker." In 2019 International Conference on Computer and Information Sciences (ICCIS). IEEE, 2019. http://dx.doi.org/10.1109/iccisci.2019.8716410.

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Gayathri, S. S., and A. V. Ananthalakshmi. "Design and implementation of efficient reversible even parity checker and generator." In 2014 International Conference on Science Engineering and Management Research (ICSEMR). IEEE, 2014. http://dx.doi.org/10.1109/icsemr.2014.7043605.

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Raman, Sowmya, N. Samanvita, Thaseel Ahmed, Aishwarya Aishwarya, and Karthiganesh D. "Implementation of Parity Generator and Checker using Quantum-Dot Cellular Automata." In 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon). IEEE, 2022. http://dx.doi.org/10.1109/mysurucon55714.2022.9972362.

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Shikha, Neeta Pandey, and Kirti Gupta. "Realization of Positive Feedback Source Coupled Logic Even Parity Generator/Checker." In 2023 7th International Conference On Computing, Communication, Control And Automation (ICCUBEA). IEEE, 2023. http://dx.doi.org/10.1109/iccubea58933.2023.10392162.

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Siddharth, Arihant Raj, Urvashi, and Gargi Khanna. "Low Power Architecture of 4-bit Odd Parity Generator/Checker Scheme." In 2023 5th International Conference on Power, Control & Embedded Systems (ICPCES). IEEE, 2023. http://dx.doi.org/10.1109/icpces57104.2023.10075976.

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Raporty organizacyjne na temat "Parity checker"

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Roca, V., C. Neumann, and D. Furodet. Low Density Parity Check (LDPC) Staircase and Triangle Forward Error Correction (FEC) Schemes. RFC Editor, 2008. http://dx.doi.org/10.17487/rfc5170.

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Roca, V., M. Cunche, and J. Lacan. Simple Low-Density Parity Check (LDPC) Staircase Forward Error Correction (FEC) Scheme for FECFRAME. RFC Editor, 2012. http://dx.doi.org/10.17487/rfc6816.

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Horne, Benjamin, and Matthew J. A. Craig. Despite Meta Ending Its Third-Party Fact-Checking Program, Most People Still Want Fact-Checkers on Social Media. University of Tennessee, 2025. https://doi.org/10.7290/iii037fjd.

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Pretorius, Christo. Populism in Ireland: Sinn Féin and the Alternative to Fine Gael and Fianna Fáil’s Political Dominance. European Center for Populism Studies (ECPS), 2024. http://dx.doi.org/10.55271/pp0039.

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This article seeks to investigate populism in Ireland, but more specifically the populist left-leaning party Sinn Féin. Although having a checkered past, in the last decade the party has seen a surge in popularity as the alternative voting option. Up until now academic literature discussing the populist nature of Sinn Féin often struggles to define it as such, and so, using political psychology and a clear definition of populism, this article not only categorizes the party as a populist, but also discusses its history and what effect it has had (or lack thereof) on its popularity in the leadup
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Cruz, Cesi, Philip Keefer, and Carlos Scartascini. The Database of Political Institutions 2020 (DPI2020). Inter-American Development Bank, 2021. http://dx.doi.org/10.18235/0003049.

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The Database of Political Institutions presents institutional and electoral results data such as measures of checks and balances, tenure and stability of the government, identification of party affiliation and ideology, and fragmentation of opposition and government parties in the legislature. The current version of the database expands its coverage to about 180 countries for 45 years, 1975-2020. It has become one of the most cited databases in comparative political economy and comparative political institutions, with more than 4,500 article citations on Google Scholar as of December 2020.
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Mehnert, Stefan, and Stefan Abrecht. Annual Yield Check of Large Scale Solar Thermal Systems. IEA SHC Task 68, 2025. https://doi.org/10.18777/ieashc-task68-2025-0002.

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This document describes a simple methodology for verifying the predicted annual yield of large-scale solar systems. This method was developed by Fraunhofer ISE and Solar Experience GmbH as part of the ProSolNetz project (FKZ: 03EN603F) (Bundesministerium für Wirtschaft und Klimaschutz [BMWK.IIB5] &amp; Forschungszentrum Jülich GmbH [PT-J.ESN6], 2025) and is described in ISO/DIS 24194. This report is divided into an overview of currently available methods for field characterization, which are relevant in the context of method development. It shows the global objectives that were at the forefron
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Simanta, Soumya, Grace A. Lewis, and Lutz Wrage. T-Check(Servicemark) for Technologies for Interoperability: Open Grid Services Architecture(OGSA) - Part 1. Defense Technical Information Center, 2007. http://dx.doi.org/10.21236/ada472585.

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Watmough, Simon P. From Political Pariah to President: Prabowo Subianto and the Perils of Populism in Indonesia. European Center for Populism Studies (ECPS), 2024. http://dx.doi.org/10.55271/lp0011.

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Prabowo Subianto’s victory in Indonesia’s February 2024 presidential election marks a pivotal moment in the nation’s democratic evolution, echoing a global shift towards nationalist populism. As Indonesia’s eighth president, Prabowo’s political journey and ideological stance have sparked concerns about the future of the country’s democratic institutions. His controversial military past, including allegations of human rights abuses in East Timor and Aceh during the 1990s, continues to raise alarms about the potential for authoritarianism under his leadership. Critics fear his presidency may sig
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Martzloff, Francois D. Surge protection in low-voltage AC power circuits - an anthology, part 2 - development of standards reality checks. National Institute of Standards and Technology, 2002. http://dx.doi.org/10.6028/nist.ir.6714-2.

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Lindner, André, Wolfgang Wende, and Nora Adam. Realitäts-Check auf regionaler Ebene: Implikationen der CBD-COP15 für Sachsen. Edited by Vera Braun. Technische Universität Dresden / Leibniz-Institut für ökologische Raumentwicklung, 2023. http://dx.doi.org/10.25368/2023.217.

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Reaching the goals of the Kunming-Montreal Global Biodiversity Framework requires commitment at all political levels and in all sectors. The State of Saxony also has to contribute its share. Saxony has a great potential, but also faces particular challenges. Almost half of the land area is used for agriculture, mainly for arable farming. However, only around eight percent of the land is farmed ecologically4. Intensification and monotonization of agriculture, as well as the use of pesticides and fertilizers, significantly contribute to the loss of biodiversity. Agriculture plays a crucial role
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