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Artykuły w czasopismach na temat „Parity checker”

Autor: Grafiati

Data publikacji: 3 czerwca 2025

Data aktualizacji: 31 lipca 2025

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1

A.Anjana. "Even and Odd Parity Generator and Checker using the Reversible logic gates." International Journal of Computer Science and Engineering Communications 1, no. 1 (2013): 62–66. https://doi.org/10.5281/zenodo.821766.

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Digital data transmission is the mostly used in the communication. The data transmission from source to destination should be without loss of information. This is made possible by using the method of parity generator and parity checker. The parity checker and the parity generator are of two types they are even parity generator and parity checker, odd parity generator and checker. Reversible logic gates compremises various parameters in the data transmission. There are various reversible logic gates to meet the needs of the parity generator and parity checker. Reversible gates probably reduce t

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2

Tarnick, Steffen. "Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability." VLSI Design 5, no. 4 (1998): 347–56. http://dx.doi.org/10.1155/1998/67574.

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In self-checking systems, checkers usually do not receive all code words during normal operation. Missing code words may prevent a checker from achieving the totally self-checking property. The paper presents a novel approach to the design of embedded parity and two-rail checkers that allows a checker to receive all code words irrespective of the set of code words that is provided by the functional circuit. A checker gets all code words by an LFSR while at the same time it monitors the output of the functional circuit. Additionally, the LFSR is able to capture the error patterns of noncode wor

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3

Battula, Brahmaiah, Valeti SaiLakshmi, Karpurapu Sunandha, S. Durga Sri Sravya, Putta Vijaya Lakshmi, and S. Navya Sri. "Design a Low Power and High Speed Parity Checker using Exclusive–or Gates." International Journal of Innovative Technology and Exploring Engineering 10, no. 4 (2021): 121–25. http://dx.doi.org/10.35940/ijitee.d8522.0210421.

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In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by

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4

Brahmaiah, Battula*, SaiLakshmi Valeti, Durga Sri Sravya S., Vijaya Lakshmi Putta, Sunandha Karpurapu, and Navya Sri S. "Design a Low Power and High Speed Parity Checker using Exclusive or Gates." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 10, no. 4 (2021): 121–25. https://doi.org/10.35940/ijitee.D8522.0210421.

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In the presented paper we designed the parity checker by using EX-OR modules. The two EX-OR modules are presented to design the parity checker and correlated their outcomes based on the constraints like power, area, delay and power delay product (PDP). The previous design is with eight transistors EX-OR, but in the present six transistors EX-OR is used to design the parity checker. While correlating the parity checker design with 8T EX-OR and 6T EX-OR, the 6T EX-OR parity checker design gives optimized power, delay, area and PDP over the 8T EX-OR parity checker design. Simulations are done by

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5

B.Y., Galadima G.S.M Galadanci S.M. Gana A. Tijjani M. Ibrahim. "QCA Based Design of Reversible Parity Generator and Parity Checker Circuits for Telecommunication." NIPES Journal of Science and Technology Research 5, no. 2 (2023): 331–43. https://doi.org/10.5281/zenodo.8070398.

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<em>Quantum-dot cellular automation (QCA) is a transistor-free technology used to implement nanoscale circuit designs. When compared to the widely used complementary metal oxide semiconductor (CMOS) technology, QCA circuits are faster, denser, and use less energy. It has some advantages in reversible logic, including its small size and low power dissipation. In this work, a model of a low-power 3-bit odd parity generator and checker circuit based on a reversible Feynman gate with 23 cells and 40 cells, respectively, is proposed. The proposed reversible odd parity generator and checker circuit

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6

Campbell, Earl T., and Mark Howard. "Magic state parity-checker with pre-distilled components." Quantum 2 (March 14, 2018): 56. http://dx.doi.org/10.22331/q-2018-03-14-56.

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Magic states are eigenstates of non-Pauli operators. One way of suppressing errors present in magic states is to perform parity measurements in their non-Pauli eigenbasis and postselect on even parity. Here we develop new protocols based on non-Pauli parity checking, where the measurements are implemented with the aid of pre-distilled multiqubit resource states. This leads to a two step process: pre-distillation of multiqubit resource states, followed by implementation of the parity check. These protocols can prepare single-qubit magic states that enable direct injection of single-qubit axial

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7

Liu, Zilong, Xiaosuo Wu, Huifu Xiao, et al. "On-chip optical parity checker using silicon photonic integrated circuits." Nanophotonics 7, no. 12 (2018): 1939–48. http://dx.doi.org/10.1515/nanoph-2018-0140.

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AbstractThe optical parity checker plays an important role in error detection and correction for high-speed, large-capacity, complex digital optical communication networks, which can be employed to detect and correct the error bits by using a specific coding theory such as introducing error-detecting and correcting codes in communication channels. In this paper, we report an integrated silicon photonic circuit that is capable of implementing the parity checking for binary string with an arbitrary number of bits. The proposed parity checker consisting of parallel cascaded N micro-ring resonator

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8

Poustie, A. J., K. J. Blow, A. E. Kelly, and R. J. Manning. "All-optical parity checker with bit-differential delay." Optics Communications 162, no. 1-3 (1999): 37–43. http://dx.doi.org/10.1016/s0030-4018(99)00070-x.

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9

Yasasvi, Bhargava, Charu Rana, and Pankaj Rakheja. "Implementation of Parity Checker Using CMOS Logic Techniques." International Journal of Advance Research and Innovation 6, no. 2 (2018): 31–34. http://dx.doi.org/10.51976/ijari.621806.

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The technology is growing rapidly where the sizes of the components are getting reduced as the size gets decreased the, possibility of errors gets increased. These errors can’t be prevented as they are generated in the running phase. To handle such problems, we need a circuit which will be monitoring continuously and correcting the errors generated. This paper proposes different ways to implement a parity checker in the previous self-checking register. When compared with previous techniques. The circuits are stimulated in spice using 90nm CMOS technology.

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10

Han, Bingchen, Junyu Xu, Pengfei Chen, et al. "All-Optical Non-Inverted Parity Generator and Checker Based on Semiconductor Optical Amplifiers." Applied Sciences 11, no. 4 (2021): 1499. http://dx.doi.org/10.3390/app11041499.

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An all-optical non-inverted parity generator and checker based on semiconductor optical amplifiers (SOAs) are proposed with four-wave mixing (FWM) and cross-gain modulation (XGM) non-linear effects. A 2-bit parity generator and checker using by exclusive NOR (XNOR) and exclusive OR (XOR) gates are implemented by first SOA and second SOA with 10 Gb/s return-to-zero (RZ) code, respectively. The parity and check bits are provided by adjusting the center wavelength of the tunable optical bandpass filter (TOBPF). A saturable absorber (SA) is used to reduce the negative effect of small signal clock

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11

Eshra, Abeer, and Ayman El-Sayed. "An Odd Parity Checker Prototype Using DNAzyme Finite State Machine." IEEE/ACM Transactions on Computational Biology and Bioinformatics 11, no. 2 (2014): 316–24. http://dx.doi.org/10.1109/tcbb.2013.2295803.

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12

Hafiz, Md Abdullah Al, Ren Li, Mohammad I. Younis, and Hossein Fariborzi. "A parity checker circuit based on microelectromechanical resonator logic elements." Physics Letters A 381, no. 9 (2017): 843–48. http://dx.doi.org/10.1016/j.physleta.2017.01.017.

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13

A., Abdelmged, Al-Hussien Seddik, and Nada Hussien. "A Technique of Image Steganography using Parity Checker and LSBraille." International Journal of Computer Applications 144, no. 4 (2016): 37–41. http://dx.doi.org/10.5120/ijca2016910323.

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14

Das, Jadav Chandra, and Debashis De. "Quantum-dot cellular automata based reversible low power parity generator and parity checker design for nanocommunication." Frontiers of Information Technology & Electronic Engineering 17, no. 3 (2016): 224–36. http://dx.doi.org/10.1631/fitee.1500079.

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15

Rajkumar, mr, Rahul Rishi, and Shudhir Batra. "A New Steganography Method for Gray Level Images using Parity Checker." International Journal of Computer Applications 11, no. 11 (2010): 18–24. http://dx.doi.org/10.5120/1627-2188.

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16

Fan, Daoqing, Yongchao Fan, Erkang Wang, and Shaojun Dong. "A simple, label-free, electrochemical DNA parity generator/checker for error detection during data transmission based on “aptamer-nanoclaw”-modulated protein steric hindrance." Chemical Science 9, no. 34 (2018): 6981–87. http://dx.doi.org/10.1039/c8sc02482k.

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17

Gao, Ru-Ru, Shuo Shi, Ying Zhu, Hai-Liang Huang, and Tian-Ming Yao. "A RET-supported logic gate combinatorial library to enable modeling and implementation of intelligent logic functions." Chemical Science 7, no. 3 (2016): 1853–61. http://dx.doi.org/10.1039/c5sc03570h.

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A logic gate combinatorial library, including basic logic gates, a single three-input NOR gate, and combinatorial gates to realize intelligent logic functions (keypad-lock, parity checker) is constructed.

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18

A., Raja, Mukherjee K., and N. Roy J. "Design of all-optical parity bit generator and checker using semiconductor material based devices." Journal of Indian Chemical Society Vol. 97, No. 12c, Dec 2020 (2020): 2919–28. https://doi.org/10.5281/zenodo.5654709.

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Department of Physics, Kazi Nazrul University, Asansol-713 340, West Bengal, India Department of Physics, B. B. College, Asansol-713 303, West Bengal, India Centre for Organic Spintronics and Optoelectronics Devices (COSOD), Kazi Nazrul University, Asansol-713 340, West Bengal, India <em>E-mail:</em> klmukherjee003@gmail.com <em>Manuscript received online 02 December 2020, accepted 22 December 2020</em> In this communication, we are trying to design a new all-optical parity bit generator and parity checker operating in ultra high speed using four-wave mixing (FWM) and cross-polarization modula

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19

Sasamal, Trailokya Nath, Ashutosh Kumar Singh, and Anand Mohan. "Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate." International Journal of Computer Theory and Engineering 7, no. 4 (2015): 311–15. http://dx.doi.org/10.7763/ijcte.2015.v7.977.

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20

Ghosh, Amal K. "Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator." Optoelectronics Letters 6, no. 5 (2010): 325–27. http://dx.doi.org/10.1007/s11801-010-0060-1.

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21

Fan, Daoqing, Erkang Wang, and Shaojun Dong. "A DNA-based parity generator/checker for error detection through data transmission with visual readout and an output-correction function." Chemical Science 8, no. 3 (2017): 1888–95. http://dx.doi.org/10.1039/c6sc04056j.

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The first DNA-based molecular parity generator/checker, used for error detection through data transmission with fluorescent and visual readouts, has been constructed. The erroneous transmission can be readily distinguished by the naked eye using the G-quadruplex DNAzyme as a signal reporter of the visual outputs.

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22

Kumar, Rajiv, Niranjan Kumar, and Poonam Singh. "Implementation of All-Optical Even Parity Checker using the Micro-Ring Resonator Structures." Journal of Engineering and Applied Sciences 14, no. 16 (2019): 5665–69. http://dx.doi.org/10.36478/jeasci.2019.5665.5669.

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23

KWON, T. W. "A Parity Checker for a Large RNS Numbers Based on Montgomery Reduction Method." IEICE Transactions on Electronics E88-C, no. 9 (2005): 1880–85. http://dx.doi.org/10.1093/ietele/e88-c.9.1880.

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24

Rakshit, Jayanta Kumar, Jitendra Nath Roy, and Tanay Chattopadhyay. "Design of micro-ring resonator based all-optical parity generator and checker circuit." Optics Communications 303 (August 2013): 30–37. http://dx.doi.org/10.1016/j.optcom.2013.03.025.

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25

Reis, Cecília, J. A. Tenreiro Machado, and J. Boaventura Cunha. "Evolutionary Design of Combinational Logic Circuits." Journal of Advanced Computational Intelligence and Intelligent Informatics 8, no. 5 (2004): 507–13. http://dx.doi.org/10.20965/jaciii.2004.p0507.

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This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.

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26

Bälter, Magnus, Shiming Li, Jesper R. Nilsson, Joakim Andréasson, and Uwe Pischel. "An All-Photonic Molecule-Based Parity Generator/Checker for Error Detection in Data Transmission." Journal of the American Chemical Society 135, no. 28 (2013): 10230–33. http://dx.doi.org/10.1021/ja403828z.

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27

Zhou, Chunyang, Dali Liu, and Shaojun Dong. "Innovative Bimolecular-Based Advanced Logic Operations: A Prime Discriminator and An Odd Parity Checker." ACS Applied Materials & Interfaces 8, no. 32 (2016): 20849–55. http://dx.doi.org/10.1021/acsami.6b05505.

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28

Samanta, Debajyoti, and Sourangshu Mukhopadhyay. "All-optical method of developing parity generator and checker with polarization encoded light signal." Journal of Optics 41, no. 3 (2012): 167–72. http://dx.doi.org/10.1007/s12596-012-0080-2.

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29

Pahari, Nirmalya. "All optical even and odd parity bit generator and checker with optical nonlinear material." Journal of Optics 46, no. 3 (2016): 336–41. http://dx.doi.org/10.1007/s12596-016-0377-7.

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30

Kotb, Amer, Kyriakos E. Zoiros, Chunlei Guo, and Wei Chen. "All-Optical 4-Bit Parity Generator and Checker Utilizing Carrier Reservoir Semiconductor Optical Amplifiers." Electronics 13, no. 12 (2024): 2314. http://dx.doi.org/10.3390/electronics13122314.

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This research explores the forefront of all-optical data processing systems through the utilization of carrier reservoir semiconductor optical amplifiers (CR-SOAs). Recent advancements have showcased the successful design and implementation of CR-SOA-based combinational systems, incorporating pivotal elements like half adders, half subtractors, digital-to-analog converters, latches, header recognition, and header processors. These breakthroughs signify a significant stride towards the realization of faster and more efficient optical logic systems. This study delves into the distinctive charact

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31

Kumar, Santosh, Chanderkanta, and Angela Amphawan. "Design of parity generator and checker circuit using electro-optic effect of Mach–Zehnder interferometers." Optics Communications 364 (April 2016): 195–224. http://dx.doi.org/10.1016/j.optcom.2015.11.054.

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32

A., Abdelmged, Al-Hussien Seddik, and Nada Hussien. "A Combined Approach of Steganography and Cryptography Technique based on Parity Checker and Huffman Encoding." International Journal of Computer Applications 148, no. 2 (2016): 26–32. http://dx.doi.org/10.5120/ijca2016911031.

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33

Yadav, Ajay, Ajay Kumar, and Amit Prakash. "Harnessing XPM effects in non-linear directional couplers for 4-bit gray code conversion and even parity verification." Journal of Electrical Engineering 75, no. 1 (2024): 14–23. http://dx.doi.org/10.2478/jee-2024-0003.

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Abstract The all-optical switching phenomena in the non-linear directional coupler using cross-phase modulation (XPM) effect have been proposed. It is designed to generate an all-optical XOR functionality, considering the XOR logic gates as a basic module the design and analysis of an efficient all-optical 4-bit binary to gray code converter and 4-bit even parity checker circuit is proposed. The design methodology includes the switching of a weak continuous-wave (CW) signal, which is controlled by the combination of two controlled pump signals. In this paper, mathematical analysis of the coupl

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34

Agrawal, Prateek, S. R. P. Sinha, Neeraj Kumar Misra, and Subodh Wairya. "Design of Quantum Dot Cellular Automata Based Parity Generator and Checker with Minimum Clocks and Latency." International Journal of Modern Education and Computer Science 8, no. 8 (2016): 11–20. http://dx.doi.org/10.5815/ijmecs.2016.08.02.

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35

Srivastava, Pragya, Richa Yadav, and Richa Srivastava. "Ultra high speed and novel design of power-aware CNFET based MCML 3-bit parity checker." Analog Integrated Circuits and Signal Processing 104, no. 3 (2020): 321–29. http://dx.doi.org/10.1007/s10470-020-01609-w.

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36

Fayaz, S. Mahammad, and K. Srinivasa Rao. "Design of High Speed UART Protocol with CRC Error Detection at IP Level." International Scientific Journal of Engineering and Management 04, no. 07 (2025): 1–9. https://doi.org/10.55041/isjem04780.

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In this project, we present the design and implementation of a Custom High-Speed UART Protocol with CRC Error Detection at the IP level, specifically tailored for applications that demand reliable and high-speed data transmission, such as medical imaging systems. Traditional UART protocols utilize parity bits for error detection, which are limited in their ability to detect multi-bit or burst errors, thus compromising data integrity in noise-prone environments. To overcome this limitation, the proposed design replaces parity-based error detection with CRC (Cyclic Redundancy Check) logic, enabl

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37

BINDU, MADDI. "Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40371.

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The Universal Asynchronous Receiver and Transmitter (UART) are described, which is essentially a serial data transfer protocol used in digital circuit applications. The UART transmitter architecture has a baud rate generator, a parity generator, a transmitter finite state machine (FSM), and a parallel in serial out (PISO) register. The UART receiver is composed of a baud rate generator, a negative edge detector, a parity checker, a receiver Finite State Machine (FSM), and a serial in parallel out (SIPO) register. The transmitter and the receiver have the same baud rate generator; therefore, th

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38

Vittapu, Sravan K., Ravichand Sankuru, Ravi Bolimera, Kuruva Madhu Ramudu, Mekala Rameshwar Reddy, and Maddula Manasa Reddy. "Reversible logic-based parity generator circuit for nano communication network using QCA." Characterization and Application of Nanomaterials 7, no. 2 (2024): 6236. http://dx.doi.org/10.24294/can.v7i2.6236.

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An alternative to CMOS VLSI called Quantum Cellular Automata (QCA) is presently being researched. Although a few basic logical circuits and devices have been examined, very little, if any, research has been done on the architecture of QCA device systems. In the context of nano communication networks, data transmission that is both dependable and efficient is still critical. The technology known as Quantum Dot Cellular Automata (QCA) has shown great promise in the development of nano-scale circuits because of its extremely low power consumption and rapid functioning. This study introduces a uni

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39

Abdullah-Al-Shafi, Md, and Ali Newaz Bahar. "Designing majority gate-based nanoscale two-dimensional two-dot one-electron parity generator and checker for nano-communication." International Nano Letters 9, no. 3 (2019): 265–76. http://dx.doi.org/10.1007/s40089-019-0279-1.

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40

Ma, Shang, JianHao Hu, Lin Zhang, and Xiang Ling. "An efficient RNS parity checker for moduli set {2 n − 1, 2 n + 1, 22n + 1} and its applications." Science in China Series F: Information Sciences 51, no. 10 (2008): 1563–71. http://dx.doi.org/10.1007/s11432-008-0097-y.

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41

Maji, K., K. Mukherjee, Ashif Raja, and J. N. Roy. "Numerical simulations of an all-optical parity generator and checker utilizing a reflective semiconductor optical amplifier at 200 Gbps." Journal of Computational Electronics 19, no. 2 (2020): 800–814. http://dx.doi.org/10.1007/s10825-020-01451-3.

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42

Norouzi, Ali, and Saeed Rasouli Heikalabad. "Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata." Photonic Network Communications 38, no. 2 (2019): 231–43. http://dx.doi.org/10.1007/s11107-019-00850-2.

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43

李, 佳起. "Design of a Three-Input Parity Checker Based on an All-Spin Logic Device and Its Clock Control Methodology." Hans Journal of Nanotechnology 14, no. 02 (2024): 13–22. http://dx.doi.org/10.12677/nat.2024.1412002.

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44

Kumar, Ajay, and Sanjeev Kumar Raghuwanshi. "Implementation of optical gray code converter and even parity checker using the electro-optic effect in the Mach–Zehnder interferometer." Optical and Quantum Electronics 47, no. 7 (2014): 2117–40. http://dx.doi.org/10.1007/s11082-014-0087-9.

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45

Dimitriadou, E., K. E. Zoiros, T. Chattopadhyay, and J. N. Roy. "Design of ultrafast all-optical 4-bit parity generator and checker using quantum-dot semiconductor optical amplifier-based Mach-Zehnder interferometer." Journal of Computational Electronics 12, no. 3 (2013): 481–89. http://dx.doi.org/10.1007/s10825-013-0463-x.

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46

Lin, Kun-Jin, and Cheng-Wen Wu. "Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications." Journal of Circuits, Systems and Computers 07, no. 01 (1997): 31–48. http://dx.doi.org/10.1142/s0218126697000048.

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CMOS Exclusive-OR (EXOR) gate implementation using conventional logic structures results in high hardware cost and long propagation delay, making it unattractive to logic designers. A number of more efficient two-input CMOS EXOR-gate structures with only six transistors have been proposed in the past. In many applications, such as parity generator, checker, and Exclusive-OR Sum-of-Product (ESOP) circuits, multiple-input EXOR circuits are required. Two kinds of multiple-input EXOR circuit structures are presented, which are smaller, faster, and more power-saving than those formed by simply conn

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47

Jeong, Gu-Min, Chang-Woo Park, Sang-Il Choi, Kyoungwoo Lee, and Nikil Dutt. "Robust Face Recognition Against Soft-errors Using a Cross-layer Approach." International Journal of Computers Communications & Control 11, no. 5 (2016): 657. http://dx.doi.org/10.15837/ijccc.2016.5.2020.

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Recently, soft-errors, temporary bit toggles in memory systems, have become increasingly important. Although soft-errors are not critical to the stability of recognition systems or multimedia systems, they can significantly degrade the system performance. Considering these facts, in this paper, we propose a novel method for robust face recognition against soft-errors using a cross layer approach. To attenuate the effect of soft-errors in the face recognition system, they are detected in the embedded system layer by using a parity bit checker and compensated in the application layer by using a

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Fan, Daoqing, Erkang Wang, and Shaojun Dong. "Exploiting Polydopamine Nanospheres to DNA Computing: A Simple, Enzyme-Free and G-Quadruplex-Free DNA Parity Generator/Checker for Error Detection during Data Transmission." ACS Applied Materials & Interfaces 9, no. 2 (2017): 1322–30. http://dx.doi.org/10.1021/acsami.6b14317.

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Datta, Kakali, Debarka Mukhopadhyay, and Paramartha Dutta. "Comprehensive study on the performance comparison of logically reversible and irreversible parity generator and checker designs using two-dimensional two-dot one-electron QCA." Microsystem Technologies 25, no. 5 (2017): 1659–67. http://dx.doi.org/10.1007/s00542-017-3445-2.

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Zhu, Liping, Linying Yu, Tian Meng, Yao Peng, and Xiurong Yang. "Contrary Logic Pair Library, Parity Generator/Checker and Various Concatenated Logic Circuits Engineered by a Label‐Free and Immobilization‐Free Electrochemiluminescence Resonance Energy Transfer System." Small 17, no. 46 (2021): 2102881. http://dx.doi.org/10.1002/smll.202102881.

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