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Artykuły w czasopismach na temat „Pass transistor logic based adders”

Autor: Grafiati

Data publikacji: 2 czerwca 2025

Data aktualizacji: 31 lipca 2025

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1

Yin, Ningyuan, Wanyuan Pan, Yihe Yu, Chengcheng Tang, and Zhiyi Yu. "Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier." Electronics 12, no. 15 (2023): 3209. http://dx.doi.org/10.3390/electronics12153209.

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conv

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2

Rajitha, J. "Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits." International Journal for Research in Applied Science and Engineering Technology 12, no. 2 (2024): 1042–48. http://dx.doi.org/10.22214/ijraset.2024.58495.

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Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in tu

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3

Chaitanya, S.* Abhishek B. S. Harshavardhan S. Karthik S. Manju T. M. "Design and Analysis of Adders Using Pass Transistor Logic for Multipliers." International Journal of Scientific Research and Technology 2, no. 5 (2025): 326–37. https://doi.org/10.5281/zenodo.15421140.

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This paper demonstrates the design and optimization of a Multiplier using pass transistor logic with half and full adders in 90 nm and 45 nm CMOS technology. The design methodology utilizes fewer transistors and low-power pass transistor logic to improve system efficiency. Implementation and simulation proved these designs to be superior than traditional CMOS designs in terms of area, delay, power dissipation, and energy efficiency. Optimized adders in the multiplier framework thus provide compact, power efficient multiplier design. A comparison to conventional designs shows significant reduct

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4

Zhang, Qi, Yuping Wu, and Lan Chen. "A Subthreshold Bootstrapped SAPTL-Based Adder Design." Electronics 8, no. 10 (2019): 1161. http://dx.doi.org/10.3390/electronics8101161.

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This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amplifier including a voltage boosting part and adopting an adder architecture based on bootstrapped SAPTL, significant improvements in performance and energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology demonstrated that the proposed adder outperformed other work

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5

Barla, Prashanth, Vinod Kumar Joshi, and Somashekara Bhat. "Design and evaluation of hybrid SHE+STT-MTJ/CMOS full adder based on LIM architecture." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (2021): 012015. http://dx.doi.org/10.1088/1757-899x/1187/1/012015.

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Abstract This work aimed at developing a full adder using hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) based on the logic-in-memory architecture (LIM). LIM has emerged as the most promising alternative to the standard von-Neumann architecture in the impeding post-CMOS era. Performance of the hybrid full adder is evaluated in terms of power, delay, power delay product (PDP), and device count. These results are compared with the existing double pass transistor logic-based clocked CMOS (DPTL-C2MOS) full adder. Further, Monte-Carlo simulations on both variants

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6

Yu, Yihe, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin, and Zhiyi Yu. "Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model." Electronics 13, no. 7 (2024): 1284. http://dx.doi.org/10.3390/electronics13071284.

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finall

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7

Raju, Hajare, and Lakshminarayana C. "Design and software characterization of finFET based full adders." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 1 (2019): 51–60. https://doi.org/10.11591/ijres.v8.i1.pp51-60.

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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and

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8

Hu, Jian Ping, Xiao Ying Yu, and Bin Bin Liu. "Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems." Key Engineering Materials 460-461 (January 2011): 473–78. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.473.

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Power-efficient multipliers are essential for micro systems, where low-power signal processing hardware is demanded. This paper presents an adiabatic array multiplier based on PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. It is composed of a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. For comparison, a conventional array multiplier is also implemented. Full-custom layouts are drawn, and HSPICE simulations are carried out using the net-list extracted from their layout. The adia

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9

Gnilenko, Alexey. "LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC." System technologies 1, no. 126 (2020): 46–53. http://dx.doi.org/10.34185/1562-9945-1-126-2020-05.

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The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and o

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10

Rajasekhar, K., B. Sandhya, G. Srinivas, and N. Manogna. "Performance of Different Full Adder Structures for Optimized Design." International Journal of Advance Research and Innovation 8, no. 2 (2020): 74–80. http://dx.doi.org/10.51976/ijari.822013.

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Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss du

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11

Ramana Murthy, G., C. Senthilpari, P. Velrajkumar, and Lim Tien Sze. "Monte-Carlo analysis of a new 6-T full-adder cell for power and propagation delay optimizations in 180 nm process." Engineering Computations 31, no. 2 (2014): 149–59. http://dx.doi.org/10.1108/ec-01-2013-0023.

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Purpose – Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operation

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12

Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim, and Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology." Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

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The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), T

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13

Shah, Ambika Prasad, Rajat Kumar Jain, and Vaibhav Neema. "A Novel Energy Efficient High-Speed 10-Transistor Full Adder Cell Based on Pass Transistor Logic." Journal of Nanoelectronics and Optoelectronics 12, no. 5 (2017): 499–504. http://dx.doi.org/10.1166/jno.2017.2030.

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14

Kumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Low-Power High-Speed Double Gate 1-bit Full Adder Cell." International Journal of Electronics and Telecommunications 62, no. 4 (2016): 329–34. http://dx.doi.org/10.1515/eletel-2016-0045.

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Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and fr

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15

Mehrabani, Yavar Safaei, Reza Faghih Mirzaee, and Mohammad Eshghi. "A novel low-energy CNFET-based full adder cell using pass-transistor logic." International Journal of High Performance Systems Architecture 5, no. 4 (2015): 193. http://dx.doi.org/10.1504/ijhpsa.2015.072846.

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V, Thamizharasan, and Ramya M. "Investigation on Power, Delay and Area optimization of XOR Gate." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 19 (February 24, 2021): 297–304. http://dx.doi.org/10.37394/23201.2020.19.32.

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Nowadays a mobile computing and multimedia applications are need for high-performance reduced size and low-power devices. The multiplication is major operation in any signal processing applications. In any multiplier architecture, adder is one of the major processing elements. In which XOR is the basic block of an adder and multiplier. In this paper, a various design styles of XOR Gate have been surveyed and simulated using Microwind tool. In that XOR gate was analyzed the power using the different styles. They are conventional XOR gate, Pass transistor logic based EX-OR gate, Static inverter

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17

Tirumalasetty, Venkata Rao, K. Babulu, and G. Appala Naidu. "Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design." WSEAS TRANSACTIONS ON SYSTEMS 23 (April 9, 2024): 141–48. http://dx.doi.org/10.37394/23202.2024.23.16.

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CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exc

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18

Manchala, Venkat Subba Rao, Satyajeet Sahoo, and G. Ramana Murthy. "Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications." International Journal on Recent and Innovation Trends in Computing and Communication 10, no. 1s (2022): 329–36. http://dx.doi.org/10.17762/ijritcc.v10i1s.5900.

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Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with

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19

S, Sriram Sundar, and Mahendran G. "CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications." Integration 95 (March 2024): 102132. http://dx.doi.org/10.1016/j.vlsi.2023.102132.

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Bhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.

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Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation

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21

HAMDI, Belgacem, Khaled Ben Khalifa, and Aymen FRADI. "HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 10, no. 6 (2013): 1771–78. http://dx.doi.org/10.24297/ijct.v10i6.7025.

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In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes.

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MeenaakshiSundari, R. P. "Implementation of Low Power CMOS Full Adders Using Pass Transistor Logic." IOSR Journal of VLSI and Signal Processing 2, no. 5 (2013): 38–43. http://dx.doi.org/10.9790/4200-0253843.

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Rao Tirumalasetty, Venkata, C. V. Mohan Krishna, K. Sai Sree Tanmaie, T. Lakshmi Naveena, and Ch Jonathan. "A novel design of high performance1-bit adder circuit at deep sub-micron technology." International Journal of Engineering & Technology 7, no. 1.1 (2017): 660. http://dx.doi.org/10.14419/ijet.v7i1.1.10822.

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In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-

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Rebecca Florance, D., B. Prabhakar, and Manoj Kumar Mishra. "Design and Implementation of ALU Using Graphene Nanoribbon Field-Effect Transistor and Fin Field-Effect Transistor." Journal of Nanomaterials 2022 (July 1, 2022): 1–17. http://dx.doi.org/10.1155/2022/3487853.

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Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry

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25

Ono, Y., H. Inokawa, and Y. Takahashi. "Binary adders of multigate single-electron transistors: specific design using pass-transistor logic." IEEE Transactions on Nanotechnology 1, no. 2 (2002): 93–99. http://dx.doi.org/10.1109/tnano.2002.804743.

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SHUKLA, SOUMITRA, BAHNIMAN GHOSH, and MOHAMMAD WASEEM AKRAM. "1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM." SPIN 02, no. 02 (2012): 1250012. http://dx.doi.org/10.1142/s2010324712500129.

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This paper presents the implementation of important full adder circuits using quantum dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A fair comparison among these adders shows that the mirror adder implementation in SSL paradigm does not carry any advantage over the CMOS adder in terms of complexity and number of QDs, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, static and dynamic Manchester carry gate adders in SSL reduces the complexity and number of QDs, in harmony w

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Sarada Musala. "Analysis of Energy Efficient Differential Fault Tolerant Adders with Minimized Nonlinearities." Communications on Applied Nonlinear Analysis 32, no. 5s (2024): 69–77. https://doi.org/10.52783/cana.v32.2968.

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In this paper, two 1-bit Differential fault tolerant Full Adder circuits (1b-FA)proposed focusing on reducing nonlinearities to improve performance and reliability in modern electronic systems, using Carbon Nano FETs (CNFETs).Transmission gate logic and pass transistor logic is being used in proposed adders to improve energy and fault tolerant characteristics of Full Adder. Fault detection and fault correction mechanisms are proposed in outputs of 1-bit differential full adder. The proposed fault detection can detect only single error and proposed error correction can correct it. By using Cade

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Hsiao, Shen-Fu, Jia-Siang Yeh, and Da-Yen Chen. "High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic." VLSI Design 15, no. 1 (2002): 417–26. http://dx.doi.org/10.1080/1065514021000054736.

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An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserte

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Vallem, Dr Sharmila, G. Tejaswi, Hrithik Sidharth, and Shilpa Reddy. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. http://dx.doi.org/10.35940/ijrte.b7685.0712223.

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An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multiplier

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Dr., Sharmila Vallem, Tejaswi G., Sidharth Hrithik, and Reddy Shilpa. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. https://doi.org/10.35940/ijrte.B7685.0712223.

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<strong>Abstract: </strong>An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI

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Datta, Rajesh Kumar. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design 3, no. 2 (2023): 5–8. http://dx.doi.org/10.54105/ijvlsid.b1222.093223.

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This study introduces a gate design that uses pass transistor switches and enables the implementation of all necessary logic gates with a single structure. This gate design can be used for efficient circuit resizing and creating secure obfuscated circuits. This work also presents simulation results that demonstrate the effectiveness of the gate in performing various logic gate operations.

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Rajesh, Kumar Datta. "A Pass Transistor based Multifunction Gate Design." Indian Journal of VLSI Design (IJVLSID) 3, no. 2 (2023): 5–8. https://doi.org/10.54105/ijvlsid.B1222.093223.

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This study introduces a gate design that uses pass transistor switches and enables the implementation of all necessary logic gates with a single structure. This gate design can be used for efficient circuit resizing and creating secure obfuscated circuits. This work also presents simulation results that demonstrate the effectiveness of the gate in performing various logic gate operations.

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Hatefinasab, Seyedehsomayeh. "Carbon Nanotube Field Effect Transistor-Based Hybrid Full Adders Using Gate-Diffusion Input Structure." Journal of Nanoelectronics and Optoelectronics 14, no. 11 (2019): 1512–22. http://dx.doi.org/10.1166/jno.2019.2661.

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Scaling down the size of transistor in the nanoscale reduces the power supply voltage, as a result, the design of high-performance nano-circuit at low voltage has been considered. Most of digital circuits are composed of different components which determine the performance of the entire digital circuits. With the improvement of these components, the digital circuits can be optimized. One of these components is full adder for which various structures have been proposed to improve its performance, among them the two novel full adder structures are based on Gate-Diffusion Input (GDI) structure an

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Srilakshmi, K., A. V. S. Karthikeya Chowdary, D. Lakshmi Soumya, Ch Hemasri, and G. Pavan Kumar. "Performance Analysis of High Speed Low Power BCD Adder using CMOS and Dynamic logic." Indian Journal Of Science And Technology 18, no. 21 (2025): 1703–15. https://doi.org/10.17485/ijst/v18i21.700.

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Background: In the field of high-speed digital circuits, the efficiency of Binary Coded Decimal (BCD) adders consists of significant importance in optimizing the speed of arithmetic operations in computing systems. BCD arithmetic is crucial in scientific and financial computing systems that require decimal accuracy. Objectives: This study examines the performance of BCD adders as designed using two different logic families, Complementary Metal Oxide Semiconductor (CMOS) and dynamic logic. CMOS logic which is meant to have low static power dissipation and dynamic logic which is meant to have hi

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YUAN, SHOUCAI, and YAMEI LIU. "DUAL THRESHOLD VOLTAGE DOMINO ADDER DESIGN WITH PASS TRANSISTOR LOGIC USING STANDBY SWITCH FOR REDUCING SUB-THRESHOLD LEAKAGE CURRENT." Journal of Circuits, Systems and Computers 23, no. 03 (2014): 1450043. http://dx.doi.org/10.1142/s0218126614500431.

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Standby switch can strongly turn off all the high threshold voltage transistors, which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce sub-threshold leakage current. Sub-threshold leakage currents are especially important in burst mode type integrated circuits where the system is in an idle mode in the majority of the time. The standby switch allows a domino system to enter and leave a low leakage standby mode within a single clock cycle. In addition, we combine domino dynamic logic with pass transistor XNOR and pass transistor NAND gates to achieve logic 1 out

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Parameshwara, M. C., and H. C. Srinivasaiah. "Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750014. http://dx.doi.org/10.1142/s0218126617500141.

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A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipa

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Tsung-Te Liu, L. P. Alarcon, M. D. Pierson, and J. M. Rabaey. "Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 7 (2009): 883–92. http://dx.doi.org/10.1109/tvlsi.2008.2012054.

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Murthy, G. Ramana, C. Senthilpari, P. Velrajkumar, and T. S. Lim. "Monte-Carlo Analysis of a New 6-T Full-Adder Cell for Power and Propagation Delay Optimizations in 180nm Process." Applied Mechanics and Materials 284-287 (January 2013): 2580–89. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2580.

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This paper presents a 1-bit full adder by using as few as six transistors per bit in its design. It is designed with a combination of multiplexing control input and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-transistor adder cell. The design adopts Multiplexing with Control input technique to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. The proposed design successfully embeds the buffering circuit in the full adder design a

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Bobba, Ramyabanu, and Pooja Illa. "XOR Based Carry Select Adder for Area and Delay." International Journal of Innovative Science and Research Technology 5, no. 6 (2020): 1615–21. http://dx.doi.org/10.38124/ijisrt20jun1117.

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Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and

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Pathak, Anjali. "Advanced Ternary Addition Circuits Leveraging Carbon Nanotube Field-Effect Transistors." International Journal for Research in Applied Science and Engineering Technology 13, no. 7 (2025): 562–70. https://doi.org/10.22214/ijraset.2025.73036.

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This work introduces new ternary addition circuits realized in terms of "carbon nanotube field-effect transistors" (CNFETs). These designs take advantage of the characteristic features of CNFETs to gain significant improvements in device numbers, power dissipation, and computation time over traditional CMOS-based ternary adders. Three different CNFET-based ternary adder architectures are introduced: a basic design, an optimized design leveraging the multiple threshold voltages and the ability to realize complex ternary functions using fewer transistors in CNFETs, and a high-performance design

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Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power

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K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power

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B.Paulchamy, K.Kalpana, and J.Jaya. "An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 2605–11. https://doi.org/10.35940/ijeat.C5311.029320.

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Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and eff

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Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL

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C., Venkataiah, Mallikarjuna Rao Y., Manjula Jayamma, et al. "Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits." E3S Web of Conferences 391 (2023): 01221. http://dx.doi.org/10.1051/e3sconf/202339101221.

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Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed technique

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Avedillo, María J., José M. Quintana, and Raúl Jiménez-Naharro. "Pass-transistor based implementations of threshold logic gates for WOS filtering." Microelectronics Journal 35, no. 11 (2004): 869–73. http://dx.doi.org/10.1016/j.mejo.2004.07.006.

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Bhuvaneswari, Thangavel, Vishnuvajjula Charan Prasad, and Ajay Kumar Singh. "Reversed signal propagation BDD based low-power pass-transistor logic synthesis." IEEJ Transactions on Electrical and Electronic Engineering 8, S1 (2013): S66—S71. http://dx.doi.org/10.1002/tee.21920.

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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g

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Pandey, Neeta, Kirti Gupta, and Bharat Choudhary. "New Proposal for MCML Based Three-Input Logic Implementation." VLSI Design 2016 (September 19, 2016): 1–10. http://dx.doi.org/10.1155/2016/8712768.

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is a

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Hemanth, Badri Sai, and M. Sathish Kumar. "Low power, less area, and highly efficient hybrid 1-bit full adder." Journal of Physics: Conference Series 2571, no. 1 (2023): 012026. http://dx.doi.org/10.1088/1742-6596/2571/1/012026.

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Abstract The widely used and efficient technique is to design an FA circuit using XNOR-XOR cells in the Pass transistor and CMOS hybrid logic. The performance metrics of hybrid full adders, such as power, driving capability, and power, depend highly on the XNOR-XOR circuit. The proposed FA design provides optimization with respect to speed and performance. Low load capacitance and low static power dissipation in the circuit enabled the optimized design characteristics. The proposed circuits outperform existing designs in device parameters such as device speed, total energy consumption, power,

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