Gotowe bibliografie tematyczne / Reconfigurable logic gates

Spis treści

  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
  5. Streszczenia konferencji

Gotowa bibliografia na temat „Reconfigurable logic gates”

Autor: Grafiati
Data publikacji: 23 listopada 2024
Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "Reconfigurable logic gates"

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Vlădescu, Elena, and Daniela Dragoman. "Reconfigurable Plasmonic Logic Gates." Plasmonics 13, no. 6 (2018): 2189–95. http://dx.doi.org/10.1007/s11468-018-0737-z.

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Luo, Shijiang, Min Song, Xin Li, et al. "Reconfigurable Skyrmion Logic Gates." Nano Letters 18, no. 2 (2018): 1180–84. http://dx.doi.org/10.1021/acs.nanolett.7b04722.

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Díaz-Díaz, Irwin, and Eric Campos. "Toward a Voltage Reconfigurable Logic Gate." Memorias del Congreso Nacional de Control Automático 6, no. 1 (2023): 503–6. http://dx.doi.org/10.58571/cnca.amca.2023.107.

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Currently, novel approaches are being developed to overcome the imminent Moore's law failure. The techniques attempt to gain greater computing power by reducing the number of transistors. This work presents the simulation of a reconfigurable voltage logic gate based on the equation of a plane. The proposal is achieved by using two variables of the equation of a plane as inputs and the other as output. The proposed circuit can perform the NAND and NOR logic gates, known as universal logic gates. The simulation results show the feasibility of the proposed reconfigurable logic gate. Also, the pre
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Qi, Mingxuan, Peijun Shi, Xiaokang Zhang, et al. "Reconfigurable DNA triplex structure for pH responsive logic gates." RSC Advances 13, no. 15 (2023): 9864–70. http://dx.doi.org/10.1039/d3ra00536d.

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We constructed pH-responsive logic gates through substrate conformational change that uses two types of logic calculations, ‘AND’ and ‘OR’. Our logic gates necessitate fewer substrates when two types of logic calculations are needed.
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Medina‐Santiago, A., Mario Alfredo Reyes‐Barranca, Ignacio Algredo‐Badillo, Alfonso Martinez Cruz, Kelsey Alejandra Ramírez Gutiérrez, and Adrián Eleazar Cortés‐Barrón. "Reconfigurable arithmetic logic unit designed with threshold logic gates." IET Circuits, Devices & Systems 13, no. 1 (2018): 21–30. http://dx.doi.org/10.1049/iet-cds.2018.0046.

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Zou, Jianping, Kang Zhang, Weifan Cai, Tupei Chen, Arokia Nathan, and Qing Zhang. "Optical-reconfigurable carbon nanotube and indium-tin-oxide complementary thin-film transistor logic gates." Nanoscale 10, no. 27 (2018): 13122–29. http://dx.doi.org/10.1039/c8nr01358f.

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Rothenbuhler, Adrian, Thanh Tran, Elisa Smith, Vishal Saxena, and Kristy Campbell. "Reconfigurable Threshold Logic Gates using Memristive Devices." Journal of Low Power Electronics and Applications 3, no. 2 (2013): 174–93. http://dx.doi.org/10.3390/jlpea3020174.

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Raitza, Michael, Steffen Marcker, Jens Trommer, et al. "Quantitative Characterization of Reconfigurable Transistor Logic Gates." IEEE Access 8 (2020): 112598–614. http://dx.doi.org/10.1109/access.2020.3001352.

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Zhang, Yuqing, Zheng Peng, Zhicheng Wang, et al. "Non-Volatile Reconfigurable Compact Photonic Logic Gates Based on Phase-Change Materials." Nanomaterials 13, no. 8 (2023): 1375. http://dx.doi.org/10.3390/nano13081375.

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Photonic logic gates have important applications in fast data processing and optical communication. This study aims to design a series of ultra-compact non-volatile and reprogrammable photonic logic gates based on the Sb2Se3 phase-change material. A direct binary search algorithm was adopted for the design, and four types of photonic logic gates (OR, NOT, AND, and XOR) are created using silicon-on-insulator technology. The proposed structures had very small sizes of 2.4 μm × 2.4 μm. Three-dimensional finite-difference time-domain simulation results show that, in the C-band near 1550 nm, the OR
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Yang, Liu, Wendi Li, Ying Tao, Kaifeng Dong, Fang Jin, and Huihui Li. "Reconfigurable and reusable skyrmion logic gates with circular track." AIP Advances 13, no. 2 (2023): 025227. http://dx.doi.org/10.1063/9.0000402.

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Magnetic skyrmion, a nano-sized spin texture with topological property, have the potential to develop high-density, low-power, and multifunctional spintronic devices. To realize the reconfiguration of a single logic device and the implementation of the complete logic functions, a new reconfigurable and reusable skyrmion logic is proposed and verified by micromagnetic simulation. Logic functions including AND, OR, NOT, NAND and NOR are realized in ferromagnetic (FM) nanotrack by skyrmion-edge repulsions and the voltage control of magnetic anisotropy (VCMA) effect. The working state of the poten
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Rozprawy doktorskie na temat "Reconfigurable logic gates"

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Ting, Darwin Ta-Yueh. "Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.

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Zaghloul, Yasser A. "Polarization based digital optical representation, gates, and processor." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43675.

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A complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor could be implemented, was proposed. Following the new polarization-based representation, a new Orthoparallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output once in a truth table, was developed. This representation allows for the implementation of all basic 16 logic gates, including the NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generaliz
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Dell'Ova, Florian. "Étude de la photoluminescence non linéaire dans des microcavités plasmoniques d’or." Electronic Thesis or Diss., Bourgogne Franche-Comté, 2024. http://www.theses.fr/2024UBFCK038.

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Ce travail de thèse est consacré à l'étude détaillée de la photoluminescence non linéaire émise par des microcavités plasmoniques modales en or. Aujourd’hui encore, l’origine de cette émission lumineuse secondaire fait débat et de nombreuses recherches tentent d’identifier les mécanismes physiques impliqués. Nos résultats démontrent sans ambiguïté le rôle de la dynamique thermique du bain d'électrons chauds, généré par l'absorption d'impulsions laser femtosecondes, dans le processus d'émission non linéaire. Ce travail de thèse est consacré à l'étude détaillée de la photoluminescence non linéai
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Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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Milliord, Corey. "Dynamic Voting Schemes to Enhance Evolutionary Repair in Reconfigurable Logic Devices." Honors in the Major Thesis, University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/780.

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This item is only available in print in the UCF Libraries. If this is your Honors Thesis, you can help us make it available online for use by researchers around the world by following the instructions on the distribution consent form at http://library.ucf<br>Bachelors<br>Engineering and Computer Science<br>Computer Engineering
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Sedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.

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Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Parris, Matthew. "OPTIMIZING DYNAMIC LOGIC REALIZATIONS FOR PARTIAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS." Master's thesis, University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4128.

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Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced conf
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Al-aqeeli, Abulqadir. "Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate array." Ohio University / OhioLINK, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1177008904.

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Varadharajan, Swetha. "Digital and Analog Applications of Double Gate Mosfets." Ohio University / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1132759182.

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Książki na temat "Reconfigurable logic gates"

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C, Dorf Richard, ed. Field-programmable gate arrays: Reconfigurable logic for rapid prototyping and implementation of digital systems. Wiley, 1995.

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International Workshop on Field-Programmable Logic and Applications (10th 2000 Villach, Austria). Field-programmable logic and applications: The roadmap to reconfigurable computing : 10th international conference, FPL 2000, Villach, Austria, August 27-30, 2000 : proceedings. Springer, 2000.

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International Workshop on Field-Programmable Logic and Applications (10th 2000 Villach, Austria). Field programmable logic and applications: The roadmap to reconfigurable computing : 10th international conference, FPL 2000, Villach, Austria, August 27-31, 2000 : proceedings. Springer, 2000.

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International Conference on Field-Programmable Logic and Applications (12th 2002 Montpellier, France). Field-programmable logic and applications: Reconfigurable computing id going mainstream :12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002 : proceedings. Springer, 2002.

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John, Schewel, and Society of Photo-optical Instrumentation Engineers., eds. High-speed computing, digital signal processing, and filtering using reconfigurable logic: 20-21 November 1996, Boston, Massachusetts. SPIE, 1996.

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John, Schewel, and Society of Photo-optical Instrumentation Engineers., eds. Field programmable gate arrays (FPGAs) for fast board development and reconfigurable computing: 25-26 October, 1995, Philadelphia, Pennsylvania. SPIE, 1995.

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IEEE International Conference on Reconfigurable Computing (3rd 2006 San Luis Potosí, Mexico). Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's: ReConFig 2006 : 20-22 September 2006, San Luis Potosi, Mexico. IEEE, 2006.

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Gaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.

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Gaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.

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Gaillardon, Pierre-Emmanuel. Reconfigurable Logic: Architecture, Tools, and Applications. Taylor & Francis Group, 2018.

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Części książek na temat "Reconfigurable logic gates"

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Watanabe, Minoru, and Fuminori Kobayashi. "A High-Density Optically Reconfigurable Gate Array Using Dynamic Method." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_28.

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O’Connor, Ian, Ilham Hassoune, and David Navarro. "Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs." In IFIP Advances in Information and Communication Technology. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12267-5_6.

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Capmany, José, and Daniel Pérez. "Field Programmable Photonic Gate Arrays." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0009.

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The field programmable photonic gate array (FPPGA) is an integrated photonic device/subsystem that operates similarly to a field programmable gate array in electronics. It is a set of programmable photonics analogue blocks (PPABs) and of reconfigurable photonic interconnects (RPIs) implemented over a photonic chip. The PPABs provide the building blocks for implementing basic optical analogue operations (reconfigurable/independent power splitting and phase shifting). Broadly they enable reconfigurable processing just like configurable logic elements (CLE) or programmable logic blocks (PLBs) car
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Creedon Eoin and Manzke Michael. "Software vs. Hardware Message Passing Implementations for FPGA Clusters." In Advances in Parallel Computing. IOS Press, 2010. https://doi.org/10.3233/978-1-60750-530-3-584.

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A parallel algorithm mapped onto multiple Field Programmable Gate Arrays (FPGAs) and CPUs needs to communicate and synchronise data between the FPGAs' digital logic micro-architectures and the CPU(s). A reconfigurable logic API for the FPGA and the CPU can assist the system programmer with mapping the parallel algorithm across the available resources. This work investigates alternative ways of implementing the reconfigurable logic API.
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Véstias, Mário Pereira. "Field-Programmable Gate Array." In Encyclopedia of Information Science and Technology, Fifth Edition. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-3479-3.ch020.

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Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article
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Ben Salem, Ahmed Karim, Hedi Abdelkrim, and Slim Ben Saoud. "Flexible Implementation of Industrial Real-Time Servo Drive System." In Reconfigurable Embedded Control Systems. IGI Global, 2011. http://dx.doi.org/10.4018/978-1-60960-086-0.ch018.

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The research presented in this chapter deals with the design and implementation of Real-Time (RT) control systems applying advanced Field Programmable Gate Array (FPGAs). The chapter proposes a promising flexible architecture that uses RT Operating System (RTOS) and ready-to-use Intellectual Properties (IPs). The authors detail an approach that uses software closed control loop function blocks (FB), running on embedded processor cores. These FBs implement the different control drive sub-modules into RTOS tasks of the execution environment, where each task has to be executed under well defined
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Harb, Naim, Smail Niar, and Mazen A. R. Saghir. "Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6194-3.ch014.

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Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a
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Mukhopadhyay, Sumitra, and Soumyadip Das. "A System on Chip Development of Customizable GA Architecture for Real Parameter Optimization Problem." In Handbook of Research on Natural Computing for Optimization Problems. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0058-2.ch004.

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This chapter presents the design and development of a hardware based architecture of Evolutionary Algorithm for solving both the unimodal and multimodal fixed point real parameter optimization problems. Here a modular architecture has been proposed to provide a tradeoff between real time performance and flexibility and to work as a resource efficient reconfigurable device. The evolutionary algorithm used here is Genetic Algorithm. Prototype implementation of the algorithm has been performed on a system-on-chip field programmable gate array. The notable feature of the architecture is the capabi
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Calore, Enrico, and Sebastiano Fabio Schifano. "Porting a Lattice Boltzmann Simulation to FPGAs Using OmpSs." In Parallel Computing: Technology Trends. IOS Press, 2020. http://dx.doi.org/10.3233/apc200100.

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Reconfigurable computing, exploiting Field Programmable Gate Arrays (FPGA), has become of great interest for both academia and industry research thanks to the possibility to greatly accelerate a variety of applications. The interest has been further boosted by recent developments of FPGA programming frameworks which allows to design applications at a higher-level of abstraction, for example using directive based approaches. In this work we describe our first experiences in porting to FPGAs an HPC application, used to simulate Rayleigh-Taylor instability of fluids with different density and tem
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Streszczenia konferencji na temat "Reconfigurable logic gates"

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Sarker, Md Shamim, Lihao Yao, E. M. K. Ikball Ahamed, Hiroyasu Yamahara, Sankar Ganesh Ramaraj, and Hitoshi Tabata. "Tunable magnon interference-based reconfigurable logic gate using microstructured Y3 Fe5 O12 Thin Films." In 2024 13th International Conference on Electrical and Computer Engineering (ICECE). IEEE, 2024. https://doi.org/10.1109/icece64886.2024.11024899.

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Sui, Bing-cai, Ya-qing Chi, Hai-liang Zhou, Zuo-cheng Xing, and Liang Fang. "Reconfigurable single-electron transistor logic gates." In 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). IEEE, 2008. http://dx.doi.org/10.1109/icsict.2008.4734593.

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Goddard, Lynford L., Jeffrey S. Kallman, and Tiziana C. Bond. "Rapidly reconfigurable all-optical universal logic gates." In Optics East 2006, edited by Joachim Piprek and Jian Jim Wang. SPIE, 2006. http://dx.doi.org/10.1117/12.686169.

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Thanh Tran, Adrian Rothenbuhler, Elisa H. Barney Smith, Vishal Saxena, and Kristy A. Campbell. "Reconfigurable Threshold Logic Gates using memristive devices." In 2012 IEEE Subthreshold Microelectronics Conference (SubVT). IEEE, 2012. http://dx.doi.org/10.1109/subvt.2012.6404301.

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Kuttappa, Ragh, Lunal Khuon, Bahram Nabet, and Baris Taskin. "Reconfigurable threshold logic gates using optoelectronic capacitors." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927060.

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Donghyeok Bae, Jaehong Park, Maengkyu Kim, Yongsik Jeong, and Kyounghoon Yang. "RTD-based reconfigurable logic gates for programmable logic array applications." In 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)]. IEEE, 2016. http://dx.doi.org/10.1109/iciprm.2016.7528573.

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Dery, Hanan, Hui Wu, Berkehan Ciftcioglu, et al. "Reconfigurable nanoelectronics using graphene based spintronic logic gates." In SPIE NanoScience + Engineering, edited by Henri-Jean M. Drouhin, Jean-Eric Wegrowe, and Manijeh Razeghi. SPIE, 2011. http://dx.doi.org/10.1117/12.890318.

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Papandroulidakis, G., A. Khiat, A. Serb, S. Stathopoulos, L. Michalas, and T. Prodromakis. "Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates." In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018. http://dx.doi.org/10.1109/iscas.2018.8351192.

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Johnson, Mark, Jindong Song, Jinki Hong, and Joonyeon Chang. "Magnetic field controlled reconfigurable logic gates with integrated nanomagnets." In SPIE NanoScience + Engineering, edited by Henri-Jean Drouhin, Jean-Eric Wegrowe, and Manijeh Razeghi. SPIE, 2013. http://dx.doi.org/10.1117/12.2024409.

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Zhu, Haotong, Guihai Yu, Zheng Zhou, et al. "Reconfigurable Optoelectronic Logic Gates Based on Complementary FDSOI-Based Phototransistor." In 2024 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2024. http://dx.doi.org/10.7567/ssdm.2024.n-7-04.

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