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Rozprawy doktorskie na temat „Stencil printing”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 6 lutego 2022

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1

Braunstein, Daniel J. (Daniel Judah). "Real time process monitoring of solder paste stencil printing." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/35374.

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Rodriguez, German Dario. "Analysis of the solder paste release in fine pitch stencil printing processes." Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/18867.

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Ismail, Ismarani. "Stencil printing of solder paste for reflow soldering of surface mount technology assembly." Thesis, University of Salford, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.426875.

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Edwards, Matthew Bruce ARC Centre of Excellence in Advanced Silicon Photovoltaics &amp Photonics Faculty of Engineering UNSW. "Screen and stencil print technologies for industrial N-type silicon solar cells." Publisher:University of New South Wales. ARC Centre of Excellence in Advanced Silicon Photovoltaics & Photonics, 2008. http://handle.unsw.edu.au/1959.4/41372.

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To ensure that photovoltaics contributes significantly to future world energy production, the cost per watt of producing solar cells needs to be drastically reduced. The use of n-type silicon wafers in conjunction with industrial print technology has the potential to lower the cost per watt of solar cells. The use of n-type silicon is expected to allow the use of cheaper Cz substrates, without a corresponding loss in device efficiency. Printed metallisation is well utilised by the PV industry due to its low cost, yet there are few examples of its application to n-type solar cells. This thesis

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Marks, Antony Edward. "Characterisation of lead-free solder pastes and their correlation with the stencil printing process performance." Thesis, University of Greenwich, 2012. http://gala.gre.ac.uk/9456/.

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Solder pastes are complex materials whose properties are governed by many factors. Variations exhibited in solder paste characteristics make it increasingly difficult to understand the correlations between solder paste properties and their printing process performance. The recent EU directives on RoHS (Restriction of Hazardous Substances – enacted by UK regulations) and WEEE (Waste from Electrical and Electronic Equipment) has led to the use of lead-free soldering in the SMA (surface mount assembly) process, and an urgent need for better understanding of the characteristics and printing perfor

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He, D. "Modelling and computer simulation of the behaviour of solder paste in stencil printing for surface mount assembly." Thesis, University of Salford, 1998. http://usir.salford.ac.uk/14676/.

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One of the main challenges facing the electronics manufacturing industry in solder paste printing for ultra-fine pitch surface mount and flip-chip assembly is the difficulty in achieving consistent paste deposit volumes from pad-to-pad. At the very small aperture geometries required for ultra-fine pitch and flip chip assembly, flow properties of the paste becomes one of the dominant factors in the printing process. It is widely accepted that over 60% of assembly defects originate from the solder paste printing stage, and hence the urgent need for a better understanding of solder paste rheology

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Jemai, Norchene. "Développement de la technique de sérigraphie pour la formation de billes de connexions inférieures a 100µm pour l'assemblage 3D : optimisation et étude de fiabilité." Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0010/document.

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L’assemblage et le conditionnement en électronique représentent un enjeu de création de nouveaux systèmes électroniques hybrides rassemblant sur un même substrat des éléments électroniques, optiques, mécaniques… La technologie Flip-chip , introduite par IBM et baptisée C4 (Control Collapse Chip Connection), garantit une plus grande densité d’intégration tout en gardant les mêmes dimensions de puce. Au coeur de cette technologie, le « Bumping » est un procédé qui consiste en l’introduction d’une microbille conductrice entre deux plots de connexion des puces afin de réaliser une liaison électriq

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Jakub, Miroslav. "Technologické postupy pájení pouzder QFN." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221072.

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This master´s thesis deals with QFN packages soldering and technology procedures optimization. The aim of theoretical part is description of QFN packages, their assembly and reflow soldering on PCB in HONEYWELL. The aim of the practical part is to propose a method of measuring temperature and optimizing the thermal profiles of selected PCB with QFN packages by using convection (HONEYWELL) and infrared (BUT) reflow ovens. Comparison and evaluation of thermal profiles for 3 production PCBś with QFN packages using solder paste AIM NC257-2 were realised. The main part of master´s thesis are appear

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Barajas, Leandro G. "Process Control in High-Noise Environments Using A Limited Number Of Measurements." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/7741.

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The topic of this dissertation is the derivation, development, and evaluation of novel hybrid algorithms for process control that use a limited number of measurements and that are suitable to operate in the presence of large amounts of process noise. As an initial step, affine and neural network statistical process models are developed in order to simulate the steady-state system behavior. Such models are vitally important in the evaluation, testing, and improvement of all other process controllers referred to in this work. Afterwards, fuzzy logic controller rules are assimilated into a mathe

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Lin, Chen-Yu, and 林珍猷. "Discovering Stencil Printing Quality Defects." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/16229399228224883494.

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碩士<br>樹德科技大學<br>經營管理研究所<br>98<br>台灣經濟的增長已經嚴重依賴於高科技廠商在製造集成電路和3C產品。計算機和電信產品的主要類別，通過建立電子裝配過程。表面貼裝技術（SMT ）是一個主要手段，生產各種電子產品。提升整體素質和能力的SMT組裝線為主體，以降低生產成本，提高質量保證水平，並成為台灣主要的挑戰保持住在競爭edge.SMT製成品的主要方法是產生各種電子產品。噴花是一個最重要的SMT裝配過程。根據行業報告，平均60 ％的焊接缺陷是由於噴花進程。在本研究中，數據挖掘方法挖掘潛在的印刷缺陷模式。通過實驗設計（ DOE）的結構進行了數據收集利用決策樹算法（ C5.0 ），方差分析（方差）算法。此外，根據分類的缺陷，開發預測缺陷印刷parameters.The根據調查結果，可進一步提供電子製造商能夠加快行安裝程序，提高焊接質量。

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Shien, Yeh Pei, and 葉沛先. "Optimization of Stencil Printing Process." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/12968979670283399319.

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碩士<br>樹德科技大學<br>經營管理研究所<br>93<br>Following scientific and technological progress, the requirements of electronic products become increasingly thinner, lighter, smaller and functionally more powerful models, such as cell phones, laptop computers, PDAs, digital cameras and other gadgets are sought after. In view of this perspective, electronics manufacturers have been developing more stable production methods that assure greater stability, which in turn promotes the development of better technologies for printed circuits board assembly (PCBA). Of the latter, the key lies in the development of th

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TSAI, HAN-WEI, and 蔡瀚緯. "Developing the prediction models of solder paste volume for stencil printing process in surface mount assembly-A case study of stencil printing for TQFP package." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/r974z2.

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碩士<br>國立高雄科技大學<br>工業工程與管理系<br>108<br>Surface mount technology (SMT) is the main process to produce many types of modern electronics products in electronics assembly industry. SMT consists of three sub-processes: (1) solder paste stencil printing, (2) component placement, and (3) solder reflow. Based on literatures and industrial reports, a poor solder paste printing performance can lead to an averaged 60% of soldering defect, which increases manufacturing costs and jeopardizes product quality. Generally, engineers integrate their working experience with a variety of trial-and-error approaches

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林欣怡. "The Application of Artificial Neural Networks to Surface Mounted Stencil Printing Process." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85777875126218326708.

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碩士<br>明新科技大學<br>工業工程與管理研究所<br>97<br>Due to the trend of miniature of electronic products been evolved, the application of surface mount technology (SMT) to the printed circuit boards (PCBs) assemblies is more and more popular, matured and versatile.The process is still not well understood as indicated by the fact that industry reports 52–71% (SMT) defects are related to the solder paste stencil printing process (SPP). This research presents a neural network model for the stencil printing process in surface mount technology manufacturing of printed circuit boards. A Design of Experiment (DOE) w

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陳彥彰. "The Relationship Between Stencil Features and Paste Deposition in Surface Mounted Printing Processes." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/86147174305683282881.

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碩士<br>明新科技大學<br>工程管理研究所<br>96<br>Following by the highly development of the consuming electronic products and the trend toward the miniatureel size and user-friendly interfaces, the well-implementation of Surface Mount Technology (SMT) in today’s printed circuit board (PCB) assemblies is becoming more crucial during the processes. With the increasing difficulties and complexity of surface mounted techniques due to the miniature of electronic devices, the process yield descends and the extra cost increases. Therefore the improvement of the producing process is becoming more and more urgent now.

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Lyu, You-Chyuan, and 呂祐全. "The Use of Intelligent Parameter Design for the Optimization of Stencil Printing Process." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/87482465053060301908.

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碩士<br>華梵大學<br>工業工程與經營資訊學系碩士班<br>95<br>The demands of electronic products towards thinner, lighter, smaller and more powerful functionally. Electronics manufacturers are devoted to more stable process in the Surface Mount Technology (SMT) assembly domain. One of the key process in SMT assembly is stencil printing for solder paste deposition. Literature indicates that nearly 60% of soldering defects related to stencil printing process. Currently, there is no standard parameter setting for stencil printing in the electronic industry. The determination of printing parameters for new product is ba

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Yeh, Junwu, and 葉俊吾. "Using Artificial Neural Networks to Build a Quality Control System of SMT Stencil Printing Process." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/nq7ac8.

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碩士<br>國立成功大學<br>製造工程研究所碩博士班<br>90<br>Surface Mount Technology (SMT) assembly is the placement and attachment of electronic components to the surface of a printed circuit board, and it has become the key technology to transform manufacturing in the electronics industry to continuously respond to the needs of the global market. The relationship between the input/output variables in SMT acts nonlinearly and severely. The stencil printing is one of the most critical stages and accounts for 52~71% of overall soldering defects. This research will help in understanding the solder paste stencil printi

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Cheng, I.-peng, and 程一鵬. "Using Model Tree to Build up a Quality Control Model of SMT Stencil Printing Process." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/38862198648553104696.

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碩士<br>國立成功大學<br>工業與資訊管理學系專班<br>96<br>Solder paste printing is the first assembly process of surface mount technology (SMT). Researches had been shown that 52%-71% of the assembly defects were caused by the improper setup of the printing process. The former setup of process parameter and material choice are most proceeding by design of experiment (DOE). This will be not only waste time also high cost. It is an important issue for using current process data and how to deal with it that becomes the meaning predict model. This research applies model tree and use stencil open hole shape to be the c

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Chang, Yu-Lan, and 張毓藍. "Investigations on the Electrical Properties and Material Reaction Behavior of Solder Bumps Produced by Stencil Printing." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/58066995814221539239.

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碩士<br>國立成功大學<br>材料科學及工程學系碩博士班<br>91<br>The objective of this research was to investigate the mechanical and electrical properties of solder bumps produced with solder paste by printing. The shear strength of solder bumps and the interfacial reaction behavior between solder and UBM was investigated after reliability tests. Besides, it was also to measure the electrical resistance of flip chip bonded solder joints and to investigate the correlation between the change of the electrical resistance and the reaction behavior of the materials after different environmental tests. The interfacia

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Pan, Jianbiao. "Modeling and process optimization of solder paste stencil printing for micro-BGA and fine pitch surface mount assembly /." Diss., 2000. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:9982874.

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Chen, Pi-Shun, and 陳必軒. "The design and development of a novel micro-structured stencil for high precision printings." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/56718170217661473845.

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碩士<br>國立中山大學<br>機械與機電工程學系研究所<br>102<br>This work developed a novel micro-structured stencil for high precision printings. Printing technology are the major techniques for producing printing circuit board in electronic industry. Because, printing process are usually in low-cost and mass production for producing products. However, it is difficult to produce small patterns using conventional printing technique due to the limitation of the woven mesh or stencil’s thickness. Therefore, the critical dimension for typical printing process is limited between 50 µm to 100 µm. The electronic products ar

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