Gotowe bibliografie tematyczne / Transistor scaling

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  1. Artykuły w czasopismach
  2. Rozprawy doktorskie
  3. Książki
  4. Części książek
  5. Streszczenia konferencji

Gotowa bibliografia na temat „Transistor scaling”

Autor: Grafiati
Data publikacji: 6 września 2023
Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "Transistor scaling"

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Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.

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For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production.
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Endo, Kazuhiko. "(Invited) Technology Scaling from Bulk to Fin and Nano-Sheet Transistors." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1519. http://dx.doi.org/10.1149/ma2023-02301519mtgabs.

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In recent years, scaling of semiconductor device has progressed, leading to the development of advanced semiconductor devices with code names of below 10-nm. Various new materials and technologies have been introduced to accompany the miniaturization of semiconductor devices. First, the resistivity of aluminum became higher due to miniaturization, and aluminum was replaced by copper as the wiring metal. Then, to increase the gate capacitance of MOS field-effect transistors, the thickness of the gate insulating film (SiO2) was reduced to the limit, and as a result, gate leakage current could no
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Datta, Suman, Wriddhi Chakraborty, and Marko Radosavljevic. "Toward attojoule switching energy in logic transistors." Science 378, no. 6621 (2022): 733–40. http://dx.doi.org/10.1126/science.ade7656.

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Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scalin
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SARKOZY, S., X. MEI, W. YOSHIDA, et al. "AMPLIFIER GAIN PER STAGE UP TO 0.5 THz USING 35 NM InP HEMT TRANSISTORS." International Journal of High Speed Electronics and Systems 20, no. 03 (2011): 399–404. http://dx.doi.org/10.1142/s0129156411006684.

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Pivotal in the design of circuits is the ability to efficiently translate available transistor gain to high gain per stage. Remarkably, for 35-nm InP HEMT transistors, the efficiency of this translation remains high even up to ~0.5 THz. The ever shrinking wavelength correlated with higher frequencies necessitates a scaling of not only the device layout, but also of the passive elements and wafer thickness. Furthermore, to avoid distributed effects, the length of transistor gate fingers must be reduced.
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Reid, Dave, Campbell Millar, Scott Roy, et al. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.

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The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS p
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Fazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.

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AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films us
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Moroz, Victor, Soren Smidstrup, Munkang Choi, Ronald Gull, and Shela Aboud. "(Invited) Material Engineering for the GAA and Post-GAA Transistors and Interconnects." ECS Meeting Abstracts MA2024-01, no. 30 (2024): 1499. http://dx.doi.org/10.1149/ma2024-01301499mtgabs.

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Feature scaling in advanced CMOS technology has been slowing down starting at 10 nm node and is expected to stop completely in the next few years. Nevertheless, transistor density scaling is continuing at a Moore’s law pace, driven by DTCO and 3D IC. Transistor dimensions and minimum metal pitch are expected to be massaged down only by 10% to 20% during the next decade. However, both the transistor and the interconnect will continue to evolve and improve both in performance and in variability. Currently, the industry is transitioning from FinFET technology to GAA (Gate All-Around) technology.
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Angelov, George V., Dimitar N. Nikolov, and Marin H. Hristov. "Technology and Modeling of Nonclassical Transistor Devices." Journal of Electrical and Computer Engineering 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/4792461.

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This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) n
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Ieong, Meikei, Vijay Narayanan, Dinkar Singh, Anna Topol, Victor Chan, and Zhibin Ren. "Transistor scaling with novel materials." Materials Today 9, no. 6 (2006): 26–31. http://dx.doi.org/10.1016/s1369-7021(06)71540-1.

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Castañer, Luis M., Ramon Alcubilla, and Anna Benavent. "Bipolar transistor vertical scaling framework." Solid-State Electronics 38, no. 7 (1995): 1367–71. http://dx.doi.org/10.1016/0038-1101(94)00254-d.

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Rozprawy doktorskie na temat "Transistor scaling"

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Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.

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Deshpande, Veeresh. "Scaling Beyond Moore: Single Electron Transistor and Single Atom Transistor Integration on CMOS." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00813508.

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La r eduction (\scaling") continue des dimensions des transistors MOS- FET nous a conduits a l' ere de la nano electronique. Le transistor a ef- fet de champ multi-grilles (MultiGate FET, MuGFET) avec l'architecture \nano l canal" est consid er e comme un candidat possible pour le scaling des MOSFET jusqu' a la n de la roadmap. Parall element au scaling des CMOS classiques ou scaling suivant la loi de Moore, de nombreuses propo- sitions de nouveaux dispositifs, exploitant des ph enom enes nanom etriques, ont et e faites. Ainsi, le transistor mono electronique (SET), utilisant le ph enom ene de
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Woo, Raymond. "Band-to-band tunneling transistor scaling and design for low-power logic applications /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Yuan, Jiahui. "Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33837.

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The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research. Drift-diffusion (DD) theory is used to investigate a novel negative differentia
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Schuette, Michael L. "Advanced processing for scaled depletion and enhancement-mode AlGaN/GaN HEMTs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1275524410.

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Ahmed, Adnan. "Study of Low-Temperature Effects in Silicon-Germanium Heterojunction Bipolar Transistor Technology." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7227.

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This thesis investigates the effects of low temperatures on Silicon Germanium (SiGe) Hterojunction Bipolar Transistors (HBT) BiCMOS technology. A comprehensive set of dc measurements were taken on first, second, third and fourth generation IBM SiGe technology over a range of temperatures (room temperature to 43K for first generation, and room temperature to 15K for the rest). This work is unique in the sense that this sort of comprehensive study of dc characteristics on four SiGe HBT technology generations over a wide range of temperatures has never been done before to the best of the authors
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Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.

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Nicoletti, Talitha. "Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.

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O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na lit
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Murali, Raghunath. "Scaling opportunities for bulk accumulation and inversion MOSFETs for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/submitted/etd-02132004-173432/unrestricted/murali%5FRaghunath%5F405%5F.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.<br>Hess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).
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Hoppe, Arne [Verfasser]. "Scaling limits and Megahertz operation in thiophene-based field effect transistors / Arne Hoppe." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2008. http://d-nb.info/1034966928/34.

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Książki na temat "Transistor scaling"

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Thompson, Scott, Faran Nouri, Wen-Chin Lee, and Wilman Tsai. Transistor Scaling : Volume 913: Methods, Materials and Modeling. University of Cambridge ESOL Examinations, 2014.

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Transistor Scaling: Methods, Materials and Modeling: Symposium Held April 18-19, 2006, San Francisco, California, U.S.A. (Materials Research Society Symposium Proceedings). Materials Research Society, 2006.

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Ashraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Morgan & Claypool Publishers, 2016.

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Ashraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Springer International Publishing AG, 2016.

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Ashraf, Nabil Shovon, Shawon Alam, and Mohaiminul Alam. New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation. Morgan & Claypool Publishers, 2016.

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Nardmann, Tobias. Physics-Based Compact Modeling and Parameter Extraction for Inp Heterojunction Bipolar Transistors with Special Emphasis on Material-Specific Physical Effects and Geometry Scaling. Books on Demand GmbH, 2017.

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Części książek na temat "Transistor scaling"

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Julien, Levisse Alexandre Sébastien, Xifan Tang, and Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices." In Emerging Computing: From Devices to Systems. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.

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AbstractSince the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (F
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Chaudhry, Amit. "Scaling of a MOS Transistor." In Fundamentals of Nanoscaled Field Effect Transistors. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6822-6_1.

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Liu, T. J. K., and L. Chang. "Transistor Scaling to the Limit." In Into the Nano Era. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-74559-4_8.

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Skotnicki, T., and F. Boeuf. "Optimal Scaling Methodologies and Transistor Performance." In High Dielectric Constant Materials. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/3-540-26462-0_6.

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Tigelaar, Howard. "The Incredible Shrinking IC: Part 2 FEOL Isolation Scaling and Transistor Scaling." In How Transistor Area Shrank by 1 Million Fold. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-40021-7_10.

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Amiri, Iraj Sadegh, and Mahdiar Ghadiry. "Introduction on Scaling Issues of Conventional Semiconductors." In Analytical Modelling of Breakdown Effect in Graphene Nanoribbon Field Effect Transistor. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-6550-7_1.

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J.M. Veendrick, Harry. "Geometrical-, Physical- and Field-Scaling Impact on MOS Transistor Behaviour." In Nanometer CMOS ICs. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47597-4_2.

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Veendrick, Harry. "Geometrical, Physical and Field-Scaling Impact on MOS Transistor Behaviour." In Nanometer CMOS ICs. Springer International Publishing, 2024. http://dx.doi.org/10.1007/978-3-031-64249-4_2.

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Veendrick, H. J. M. "Geometrical-, physical- and field-scaling impact on MOS transistor behaviour." In Nanometer CMOS ICs. Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8333-4_2.

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Prasher, Rakesh, Devi Dass, and Rakesh Vaid. "Novel Attributes in Scaling Issues of an InSb-Nanowire Field-Effect Transistor." In Physics of Semiconductor Devices. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-03002-9_174.

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Streszczenia konferencji na temat "Transistor scaling"

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Lanzillo, Nicholas A., Shahrukh Khan, Jim Mazza, Utkarsh Bajpai, and Koichi Motoyama. "A Perspective on Interconnect Scaling Challenges in the NanoStack Transistor Era : AP/DFM: Advanced Patterning / Design for Manufacturing (Design-Technology Co-Optimization)." In 2025 36th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2025. https://doi.org/10.1109/asmc64512.2025.11010679.

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Robbes, A.-S., O. Dulac, K. Soulard, et al. "Etching Monitoring of Advanced Forksheet Devices Using AKONIS SIMS Tool." In ISTFA 2024. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0175.

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Abstract Imec has developed a fully-functional integrated forksheet field-effect transistors (FETs), which is the most promising architecture for advancing beyond the GAA (Gate-All-Around) nanosheet generation for scaling and performance improvements past the 2nm technology node. From a manufacturing perspective, forksheet devices are extremely complex to process and requires accurate and sensitive analytical instruments like the AKONIS SIMS tool.
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Wu, Wen-Chia, Terry Y. T. Hung, D. Mahaveer Sathaiya, et al. "On the Extreme Scaling of Transistors with Monolayer MOS2 Channel." In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631401.

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Li, Weisheng, Mingyi Du, Chunsong Zhao, et al. "Scaling MoS2 Transistors to 1 nm Node." In 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024. https://doi.org/10.1109/iedm50854.2024.10873379.

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Yang, Fu-Liang, Hou-Yu Chen, and Chang-Yun Chang. "SOI Transistor/Power Scaling and Scaling-Strengthened Strain." In 2004 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2004. http://dx.doi.org/10.7567/ssdm.2004.c-7-1.

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Chen, Tianbing, Tzung-Yin Lee, Justin Allum, and Mike McPartlin. "The thermal scaling: From transistor to array." In 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2014. http://dx.doi.org/10.1109/rfic.2014.6851675.

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Tadayon, Saied, Bijan Tadayon, and Lester F. Eastman. "Effect of InAlAs emitter on the microwave performance of InAlAs/InGaAs abrupt npn heterojunction bipolar transistor." In High-Speed Electronics and Device Scaling, edited by Lester F. Eastman. SPIE, 1990. http://dx.doi.org/10.1117/12.20909.

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Van Der Bent, G., A. P. De Hek, and F. E. Van Vliet. "EM - Based GaN Transistor Small-Signal Model Scaling." In 2018 13th European Microwave Integrated Circuits Conference (EuMIC). IEEE, 2018. http://dx.doi.org/10.23919/eumic.2018.8539925.

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Kim, Michael E. "GaAs heterojunction bipolar transistor device and IC technology for high-performance analog/microwave, digital, and A/D conversion applications." In High-Speed Electronics and Device Scaling, edited by Lester F. Eastman. SPIE, 1990. http://dx.doi.org/10.1117/12.20903.

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Kuhn, Kelin J. "CMOS transistor scaling past 32nm and implications on variation." In 2010 21st Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC). IEEE, 2010. http://dx.doi.org/10.1109/asmc.2010.5551461.

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