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Rozprawy doktorskie na temat „Transistor scaling”

Autor: Grafiati

Data publikacji: 6 września 2023

Data aktualizacji: 19 lipca 2025

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1

Chen, Qiang. "Scaling limits and opportunities of double-gate MOSFETS." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15011.

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2

Deshpande, Veeresh. "Scaling Beyond Moore: Single Electron Transistor and Single Atom Transistor Integration on CMOS." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00813508.

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La r eduction (\scaling") continue des dimensions des transistors MOS- FET nous a conduits a l' ere de la nano electronique. Le transistor a ef- fet de champ multi-grilles (MultiGate FET, MuGFET) avec l'architecture \nano l canal" est consid er e comme un candidat possible pour le scaling des MOSFET jusqu' a la n de la roadmap. Parall element au scaling des CMOS classiques ou scaling suivant la loi de Moore, de nombreuses propo- sitions de nouveaux dispositifs, exploitant des ph enom enes nanom etriques, ont et e faites. Ainsi, le transistor mono electronique (SET), utilisant le ph enom ene de

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3

Woo, Raymond. "Band-to-band tunneling transistor scaling and design for low-power logic applications /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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4

Yuan, Jiahui. "Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33837.

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The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research. Drift-diffusion (DD) theory is used to investigate a novel negative differentia

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5

Schuette, Michael L. "Advanced processing for scaled depletion and enhancement-mode AlGaN/GaN HEMTs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1275524410.

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Ahmed, Adnan. "Study of Low-Temperature Effects in Silicon-Germanium Heterojunction Bipolar Transistor Technology." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7227.

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This thesis investigates the effects of low temperatures on Silicon Germanium (SiGe) Hterojunction Bipolar Transistors (HBT) BiCMOS technology. A comprehensive set of dc measurements were taken on first, second, third and fourth generation IBM SiGe technology over a range of temperatures (room temperature to 43K for first generation, and room temperature to 15K for the rest). This work is unique in the sense that this sort of comprehensive study of dc characteristics on four SiGe HBT technology generations over a wide range of temperatures has never been done before to the best of the authors

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7

Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.

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8

Nicoletti, Talitha. "Estudo de transistores UTBOX SOI não auto-alinhados como célula de memória." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-10072014-012728/.

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O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na lit

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9

Murali, Raghunath. "Scaling opportunities for bulk accumulation and inversion MOSFETs for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/submitted/etd-02132004-173432/unrestricted/murali%5FRaghunath%5F405%5F.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004.<br>Hess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).

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10

Hoppe, Arne [Verfasser]. "Scaling limits and Megahertz operation in thiophene-based field effect transistors / Arne Hoppe." Bremen : IRC-Library, Information Resource Center der Jacobs University Bremen, 2008. http://d-nb.info/1034966928/34.

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11

Wang, Lihui. "Quantum Mechanical Effects on MOSFET Scaling." Diss., Available online, Georgia Institute of Technology, 2006, 2006. http://etd.gatech.edu/theses/available/etd-07072006-111805/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.<br>Philip First, Committee Member ; Ian F. Akyildiz, Committee Member ; Russell Dupuis, Committee Member ; James D. Meindl, Committee Chair ; Willianm R. Callen, Committee Member.

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12

Chaves, Romero Ferney Alveiro. "Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling." Doctoral thesis, Universitat Autònoma de Barcelona, 2012. http://hdl.handle.net/10803/96232.

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L’escalat dels transistors MOSFET convencionals ha portat a aquests dispositius a la nanoescala per incrementar tant les seves prestacions com el nombre de components per xip. En aquest process d’escalat, els coneguts “Short Channel Effects” representen una forta limitació. La forma més efectiva de suprimir aquests efectes i aixi estendre l’ús del MOSFET convencional, és la reducció del gruix de l’òxid de porta i l’augment de la concentració de dopants al canal. Quan el gruix d’òxid de porta es redueix a unes quantes capes atòmiques, apareix l’efecte túnel mecano-quàntic d’electrons, produint

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13

Elias, Caroline. "Étude d'héterostructures HEMT ScAlN/GaN élaborées par épitaxie sous jets moléculaires assistée ammoniac." Electronic Thesis or Diss., Université Côte d'Azur, 2023. http://www.theses.fr/2023COAZ4137.

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L'alliage ScAlN est un semiconducteur III-N à large bande interdite connu pour ses propriétés piézoélectriques remarquables. Ses propriétés de polarisation spontanée et piézoélectrique sont également intéressantes pour la réalisation d'hétérojonctions avec le GaN en vue de fabriquer des transistors à haute mobilité électronique (HEMTs). Dans ces hétérojonctions, remplacer le matériau barrière AlGaN habituellement utilisé par ScAlN présente plusieurs avantages, parmi lesquels la possibilité de générer des gaz bidimensionnels d'électrons (2DEGs) avec des densités bien plus importantes. En corola

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14

Peršun, Marijan. "Scaling of the Silicon-on-Insulator Si and Si1-xGex p-MOSFETs." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4934.

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Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gat

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15

Flachowsky, Stefan. "Verspannungstechniken zur Leistungssteigerung von SOI-CMOS-Transistoren." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-63136.

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Mit dem Erreichen der Grenzen der konventionellen MOSFET-Skalierung werden neue Techniken untersucht, um die Leistungsfähigkeit der CMOS-Technologie dem bisherigen Trend folgend weiter zu steigern. Einer dieser Ansätze ist die Verwendung mechanischer Verspannungen im Transistorkanal. Mechanische Verspannungen führen zu Kristalldeformationen und ändern die elektronische Bandstruktur von Silizium, so dass n- und p-MOSFETs mit verspannten Kanälen erhöhte Ladungsträgerbeweglichkeiten und demzufolge eine gesteigerte Leistungsfähigkeit aufweisen. Die vorliegende Arbeit beschäftigt sich mit den Auswi

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16

Rosa, André Luís Rodeghiero. "Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/118526.

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Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco célula

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17

Gomez, gomez Ricardo. "Design of innovative solutions to improve the variability and reliability of CMOS circuits on thin film technologies." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT023.

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La sensibilité accrue aux variations des procedés de fabrication, de tension, de température et de vieillissement (PVTA) dans les nœuds technologiques avancés d'integration est responsable d'une dégradation significative des spécifications des circuits integrés lors de la fabrication à grand volume. Celle-ci est devenue une préoccupation croissante dans la conception de circuits numériques, qui doit faire face aux exigences de plus en plus strictes des applications modernes en termes d'efficacité énergétique, de fiabilité et de sécurité. Dans ce travail de thèse, les techniques de surveillance

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18

Akgul, Yeter. "Gestion de la consommation basée sur l’adaptation dynamique de la tension, fréquence et body bias sur les systèmes sur puce en technologie FD-SOI." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20132/document.

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Au-delà du nœud technologique CMOS BULK 28nm, certaines limites ont été atteintes dans l'amélioration des performances en raison notamment d'une consommation énergétique devenant trop importante. C'est une des raisons pour lesquelles de nouvelles technologies ont été développées, notamment celles basées sur Silicium sur Isolant (SOI). Par ailleurs, la généralisation des architectures complexes de type multi-cœurs, accentue le problème de gestion de la consommation à grain-fin. Les technologies CMOS FD-SOI offrent de nouvelles opportunités pour la gestion de la consommation en permettant d'ajus

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19

Wang, Cai-Jia, and 王才嘉. "The scaling effects on the CMOS compatible bipolar transistor used in the low-noise, low offset voltage CMOS amplifier." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/64237608835914195262.

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20

Fitsilis, Michael [Verfasser]. "Scaling of the ferroelectric field effect transistor and programming concepts for non-volatile memory applications / vorgelegt von Michael Fitsilis." 2005. http://d-nb.info/975146378/34.

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21

Moradi, Maryam. "Vertical Thin Film Transistors for Large Area Electronics." Thesis, 2008. http://hdl.handle.net/10012/3937.

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The prospect of producing nanometer channel-length thin film transistors (TFTs) for active matrix addressed pixelated arrays opens up new high-performance applications in which the most amenable device topology is the vertical thin film transistor (VTFT) in view of its small area. The previous attempts at fabricating VTFTs have yielded devices with a high drain leakage current, a low ON/OFF current ratio, and no saturation behaviour in the output current at high drain voltages, all induced by short channel effects. To overcome these adversities, particularly dominant as the channel length appr

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22

Kurakula, Sidda Reddy. "Studies On The Electrical Properties Of Titanium Dioxide Thin Film Dielectrics For Microelectronic Applications." Thesis, 2007. https://etd.iisc.ac.in/handle/2005/484.

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The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors requires replacement of conventional silicon dioxide layer with higher dielectric constant (K) material for gate dielectric. In order to reduce the gate leakage current, and also to maximize gate capacitance, ‘high K’ gate oxide materials such as Al2O3, ZrO2, HfO2, Ta2O5, TiO2, Er2O3, La2O3, Pr2O3, Gd2O3, Y2O3, CeO2 etc. and some of their silicates such as ZrxSi1–xOy, HfxSi1–xOy, AlxZr1–xO2 etc. are under investigation. A systematic consideration of the required properties of gate dielectrics indicates that the ke

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23

Kurakula, Sidda Reddy. "Studies On The Electrical Properties Of Titanium Dioxide Thin Film Dielectrics For Microelectronic Applications." Thesis, 2007. http://hdl.handle.net/2005/484.

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The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors requires replacement of conventional silicon dioxide layer with higher dielectric constant (K) material for gate dielectric. In order to reduce the gate leakage current, and also to maximize gate capacitance, ‘high K’ gate oxide materials such as Al2O3, ZrO2, HfO2, Ta2O5, TiO2, Er2O3, La2O3, Pr2O3, Gd2O3, Y2O3, CeO2 etc. and some of their silicates such as ZrxSi1–xOy, HfxSi1–xOy, AlxZr1–xO2 etc. are under investigation. A systematic consideration of the required properties of gate dielectrics indicates that the key

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24

Kumar, Jeevesh. "Atomic-level Investigation and Proposals to Address Technological Roadblocks and Reliability Challenges in 2D Material Based Nanoelectronic Devices." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5872.

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The transistor scaling is witness to many extraordinary inventions during its consecutive miniaturization. The journey began from Dennard’s classical constant field scaling, crossing through the milestones like strain engineering, high ‘k’ gate dielectric, ultrathin body transistor (UTB), silicon on insulator (SOI), and multi-gate 3D architectures, and continues in the form of advanced FinFET technology. However, further downscaling is sensing a dead-end because of the various challenges due to fundamental limitations of silicon, the building material of the transistor. Among these, two signif

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25

Chen, Chun Yu, and 陳俊佑. "Study on Scaling Capability of Nanowire Transistors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/06479724790748063412.

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碩士<br>國立宜蘭大學<br>電子工程學系碩士班<br>97<br>The thesis mainly focuses on the scaling capability of the nanowire transistors, and the impact of quantum effect is investigated via physical 3D numerical simulation. We analyze the channel scalability and discuss how to control the short channel effects of nanowire, FinFET and Tri-Gate transistors characteristics. Several emerging patterning processes have been proposed in recent years. Due to device size scaling, quantum mechanical effects become significant. The physical quantum mechanical model is one of key figures for 3D numerical device simulation. Th

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26

Chen, Chin-Yi, and 陳沁儀. "Scaling Issues in Trigate GaN Nanowire Transistors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/67345808631375742762.

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碩士<br>國立臺灣大學<br>光電工程學研究所<br>100<br>This thesis analyzes the scalability of nitride-based nanowire high electron mobility transistors (HEMTs). The positive polarization charge between the AlGaN and GaN interface induces high density of electron which also known as the two dimensional electron gate (2DEG). With the 2DEG, the device does not need high n-type doping to increase the electron density in the channel. Therefore, the mobility can reach a high value due to less impurity scattering in the device. We use a fully three dimensional(3D) self-consistent nite element model to solves drift-di

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27

Hoppe, Arne. "Scaling limits and Megahertz operation in thiophene-based field effect transistors /." 2007. http://www.jacobs-university.de/phd/files/1210172114.pdf.

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28

Tsai, Chan-Yi, and 蔡展壹. "Evaluation of the Various Scaling Routes on Novel Poly-Si Junctionless Transistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t3jn55.

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碩士<br>國立交通大學<br>電子物理系所<br>106<br>For the demands and developments of semiconductor industry, the device dimension is scaled down continuously. In this dissertation, we investigate the pros and cons of the multi-gate poly-Si junctionless transistors in the various scaling routes. The routes are conventionally physical scaling, novel electrical scaling, and ultimate scaling, respectively. In the conventional physical scaling route, thinning down the channel of junctionless transistor is able to enhance the switching ability, but its series resistance arise to cause the current declines as the ch

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29

Wang, Wei-Chun, and 王瑋駿. "Impact of Ferroelectric HfZrOx Gate-Stack Scaling on N-type and P-type Negative Capacitance Transistors." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/x7vcf2.

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碩士<br>國立交通大學<br>光電系統研究所<br>108<br>In recent years, with the flourish of smart phones, Internet of Things (IoT) and other related applications, low-power consumption electronic devices are in urgent need. Tunneling FETs (TFETs) and Negative Capacitances (NCFETs) are been investigated to be different from traditional Si-based FETs to break through the thermophysical limitation of less than 60mV/decade subthershold (SS), allowing the transistors to turn on the devices with less biasing. Since the TFET has a shortage that Ion is hard to improve and a tradeoff effect with Ioff, the NC-FETs with neg

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