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Horst, Fabian. "Compact DC Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2019. http://hdl.handle.net/10803/668957.
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En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec.
Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT.
La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.<br>En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec.
Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT.
La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.<br>In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec.
In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved.
The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator.
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Gräf, Michael. "Two-Dimensional Analytical Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2017. http://hdl.handle.net/10803/450516.
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Basat en un mecanisme de transport de corrent de banda a banda, el túnel-FET és capaç de superar la limitació de pendent sub-llindar física del MOSFET de 60 mV /dec. Per tant, s'ha convertit en un dels dispositius més prometedors per ser el successor del MOSFET clàssic en els últims anys.
Aquesta tesi descriu tots els passos necessaris per modelar analíticament un Túnel-FET de doble porta. El model inclou una solució electrostàtica de dues dimensions en totes les regions del dispositiu, el que permet fins i tot simulacions hetero-unió del dispositiu. Per a un comportament més realista del dispositiu, cal tenir en compte el rendiment del dispositiu que limita els perfils de dopatge de forma Gaussiana en les unions del canal. Les expressions per a les probabilitats de túnel de banda a banda i les de Trap-Assisted-Tunneling (TAT) són executades per un enfocament WKB quasi bidimensional. El corrent del dispositiu es calcula mitjançant la teoria de transmissió de Landauer. El model és vàlid per a dispositius de canal curt i les estàncies estan ben comparades amb les dades de simulació TCAD Sentaurus i amb les medicions proporcionades.
S'introdueix un modelo general per les flactuacions del dopant aleatoria, que prediu les influencies característiques del dispositiu en el corrent de sortida i el voltatge llindar. El model s'aplica al MOSFET, així com a dispositius TFET.<br>Basado en un mecanismo de transporte de corriente banda a banda, el Tunnel-FET es capaz de superar la limitación de pendiente sub-umbral física del MOSFET de 60 mV/dec. Por lo tanto, esto lo convierte en uno de los dispositivos más prometedores para ser el sucesor del MOSFET clásico en los últimos años.
Esta tesis describe todos los pasos necesarios para modelar analíticamente un Tunnel-FET de doble puerta. El modelo incluye una solución electrostática bidimensional en todas las regiones del dispositivo, lo que permite incluso simulaciones de hetero-unión del dispositivo. Para un comportamiento más realista del dispositivo se tiene en cuenta el rendimiento del dispositivo que limita los perfiles de dopaje de forma Gaussiana en las uniones del canal. Las expresiones para las probabilidades de túnel de banda a banda y de Trap-Assisted-Tunneling (TAT) se implementan mediante un enfoque de WKB cuasi bidimensional. La corriente del dispositivo se calcula mediante la teoría de transmisión de Landauer. El modelo es válido para dispositivos de canal corto y las estancias están bien comparadas con los datos de simulación TCAD Sentaurus y con las mediciones proporcionadas.
Se introduce un modelo general para las fluctuaciones del dopado aleatorio, que predice las influencias características del dispositivo en la corriente de salida y el voltaje umbral. El modelo se aplica al MOSFET, así como a los dispositivos TFET.<br>Based on a band-to-band current transport mechanism, the Tunnel-FET is able to overcome the physical subthreshold slope limitation of the MOSFET of 60 mV/dec. Therefore, it has become one of the most promising devices to be the successor of the classical MOSFET in the last few years.
This thesis describes all necessary steps to analytically model a double-gate Tunnel-FET. The model includes a two-dimensional electrostatic solution in all device regions, which enables even hetero-junction device simulations. Device performance limiting Gaussian-shaped doping profiles at the channel junctions are taken into account for a realistic device behavior. Expressions for the band-to-band and trap-assisted-tunneling probabilities are implemented by a quasi two-dimensional WKB approach. The device current is calculated based on Landauer's transmission theory. The model is valid for short-channel devices and stays is good agreement with the TCAD Sentaurus simulation data and with the provided measurements.
A general model for random-dopant-fluctuations is introduced, which predicts characteristic device influences on the output current and threshold voltage. The model is applied to MOSFET, as well as TFET devices.
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Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb type-Il heterojunction vertical tunnel-FETs." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84857.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 59-62).<br>The supply voltage (VDD) scaling of conventional CMOS technology is approaching its limit due to the physical limit of 60 mV/dec subthreshold swing (SS) at room temperature and the requirement for controlled leakage current. In order to continue VDD scaling for low power applications, novel device structures with steep SS have been proposed. Tunnel-FETs (TFETs) are among the most attractive device structure due to their compatibility with conventional CMOS technology and the potential for outstanding VDD scalability. Heterostructure vertical TFETs with enhanced gate modulation promise significantly improved electrostatic control and drive current relative to lateral tunneling designs. In this thesis, vertical TFETs based on InGaAs/GaAsSb heterostructure are investigated in terms of design, fabrication and electrical characterization. Ino.53Gao.47As/ GaAso.5Sb0.5 heterostructure vertical TFETs are fabricated with an airbridge structure, designed to prevent parasitic tunneling path in the device, with a two-step highly selective undercut process. Electrical measurement of the devices with various gate areas demonstrates area-dependent tunneling current. The Ino.53Gao.47As/ GaAs0 .5 Sb. 5 vertical TFETs with HfO2 high-k gate dielectric (EOT ~ 1.3 nm) exhibit minimum sub-threshold swings of 140 and 58 mV/dec at 300 and 150 K respectively, with an ON-current density of 0.5 [mu]A/[mu]m2 at VDD = 0.5 V at 300 K. A physical model of TFET operation in the ON-state is proposed based on temperature dependent measurements, which reveal a current barrier due to an ungated region near the drain. Simulations illustrate that the gate-to-drain distance must be scaled to eliminate this barrier. In diode-mode operation, outstanding backward diode performance is demonstrated in this system for the first time, with gate-tunable curvature coefficient of 30 V1 near VDS= 0 V. These results indicate the potential of vertical TFETs in hybrid IC applications.<br>by Tao Yu.<br>S.M.
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Farokhnejad, Atieh. "Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2020. http://hdl.handle.net/10803/669806.
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La miniaturització dels MOSFET en els circuits integrats ha elevat la tecnologia microelectrònica. Aquesta tendència també augmenta el grau de complexitat d'aquests circuits i els seus components bàsics. En els MOSFET convencionals, el corrent es basa en l'emissió termoiònica de portadors de càrrega, que per això limita el pendent subumbral en aquests transistors a 60 mV / dec. Per tant, per superar aquest límit i continuar amb la miniaturització per mantenir el ritme de la llei de Moore, es requereixen estructures alternatives. Entre aquestes, el transistor d'efecte de camp per túnel (TFET) es considera un possible successor de l'MOSFET. A causa del seu mecanisme alternatiu de transport de corrent, conegut com a túnel de banda a banda (B2B), el pendent subumbral en TFET pot fer-se inferior al límit de 60 mV / dec.
Per comprendre i estimar el comportament dels TFET, no només com un element únic sinó també a nivell de circuit, es requereix un model compacte d'aquest dispositiu. En aquesta tesi es presenta un model basat en càrrega per descriure el comportament capacitiu d'un TFET de doble porta (DG TFET). No obstant això, la simplicitat i la flexibilitat de el model permeten usar-lo per a un altre tipus d'estructures TFET, com els TFET planars o de nanofils d'una sola porta (SG TFETs). El model és verificat amb les simulacions TCAD, així com amb mesures experimentals de TFET fabricats.
El model de capacitància també inclou l'efecte dels elements paràsits. A més, en el context d'aquest treball també s'investiga la influència dels contactes de barrera Schottky en el comportament capacitiu dels TFET. Aquest model finalment es combina amb un model DC compacte existent per formar un model TFET compacte complet. A continuació, el model compacte s'implementa per a simulacions transitòries de circuits oscil·ladors d'anell basats en TFET.<br>La miniaturización de los MOSFET en los circuitos integrados ha elevado la tecnología microelectrónica. Esta tendencia también aumenta el grado de complejidad de estos circuitos y sus componentes básicos. En los MOSFET convencionales, la corriente se basa en la emisión termoiónica de portadores de carga, que por ello limita la pendiente subumbral en estos transistores a 60 mV/dec. Por tanto, para superar este límite y continuar con la miniaturización para mantener el ritmo de la ley de Moore, se requieren estructuras alternativas. Entre estas, el transistor de efecto de campo por túnel (TFET) se considera un posible sucesor del MOSFET. Debido a su mecanismo alternativo de transporte de corriente, conocido como túnel de banda a banda (B2B), la pendiente subumbral en TFET puede hacerse inferior al límite de 60 mV/dec.
Para comprender y estimar el comportamiento de los TFET, no sólo como un elemento único sino también a nivel de circuito, se requiere un modelo compacto de este dispositivo. En esta tesis se presenta un modelo basado en carga para describir el comportamiento capacitivo de un TFET de doble puerta (DG TFET). Sin embargo, la simplicidad y la flexibilidad del modelo permiten usarlo para otro tipo de estructuras TFET, como los TFET planares o de nanohílos de una sola puerta (SG TFETs). El modelo es verificado con las simulaciones TCAD, así como con medidas experimentales de TFET fabricados.
El modelo de capacitancia también incluye el efecto de los elementos parásitos. Además, en el contexto de este trabajo también se investiga la influencia de los contactos de barrera Schottky en el comportamiento capacitivo de los TFET. Este modelo finalmente se combina con un modelo DC compacto existente para formar un modelo TFET compacto completo. A continuación, el modelo compacto se implementa para simulaciones transitorias de circuitos osciladores de anillo basados en TFET.<br>Miniaturization of the MOSFETs on the integrated circuits has elevated the microelectronic technology. This trend also increases the degree of complexity of these circuits and their building blocks. In conventional MOSFETs the current is based on the thermionic—emission of charge carrier, which therefore limits the subthreshold swing in these transistors to 60 mV/dec. Hence, to overcome this limit and continue with down scaling to keep pace with the Moor’s law, alternative structures are required. Among these, the tunnel—field—effect transistor (TFET) is considered as a potential successor of the MOSFET. Due to its alternative current transport mechanism, known as band—to—band (B2B) tunneling, the subthreshold swing in TFETs can overcome the 60 mV/dec limit.
In order to comprehend and estimate the behavior of TFETs, not only as a single element but also on the circuit level, a compact model of this device is required. In this dissertation a charge –based model to describes the capacitive behavior of a double—gate (DG) TFET is presented. However, simplicity and flexibility of the model allow to use it for other type of TFET structures such as single—gate (SG) planar or nanowire TFETs. The model is verified with the TCAD simulations as well as the measurement data of fabricated TFETs.
The capacitance model also includes the effect of the parasitic elements. Furthermore, in the context of this work also the influence of Schottky barrier contacts on the capacitive behavior of TFETs is investigated. This model is finally combined with an existing compact DC model to form a complete compact TFET model. The compact model is then implemented for transient simulations of TFET—based inverter and ring—oscillator circuits.
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Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb quantum-well Tunnel-FETs for ultra-low power applications." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106101.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references.<br>The Tunnel-FET (TFET), where carrier injection is determined by gate-controlled tunneling from the source to the channel, has been attractive as one of the promising candidates for future ultra-low power applications. In this thesis, inline-TFETs with tunneling direction aligned to the gate electric field are designed, fabricated and analyzed based on InGaAs/GaAsSb material. Using ultrathin InGaAs/GaAsSb quantum-well (QW), the device fabrication technology was developed and the tunneling properties of two successive generations of QWTFETs were investigated. In the first generation QWTFETs, the limitation of gate oxide quality on InGaAs and parasitic thermal currents manifests itself in degraded subthreshold swing (SS) of 140 mV/dec, as well as strongly temperature dependent SS from 300 K to 77 K. The second generation QWTFETs with sub-nm InP cap between gate oxide and InGaAs channel and revised structure design has demonstrated improved SS of 87 mV/dec at 300 K and temperature independent SS below 140 K, indicating the achievable tunneling current steepness with the current device design. Physical modeling and quantum simulations based on the low temperature I-V characteristics were used to analyze the fundamental gate efficiency of the experimental QWTFETs in order to reveal the ultimate intrinsic tunneling steepness of the InGaAs/GaAsSb tunneling junction. The extracted gate efficiency around 55-64% is due to the coupling of the gate capacitance and tunneling junction capacitance and degrades dramatically the attainable SS in the QWTFET. On the other hand, the implied intrinsic tunneling steepness of the InGaA/GaAsSb is around 30 mV/dec, almost identical to previously reported non-abruptness of the conduction/valence band-edge into the bandgap. The result indicates the possibility of achieving SS as low as 38 mV/dec in QWTFETs by improving gate efficiency by up to 78% with proposed optimized parameters based on simulation results. Non-logic TFET-specific circuits are also explored to understand the advantage of TFETs in real-world applications. Due to the superior nonlinearity in the device I-V characteristics and gate-dependent negative-differential-resistance (NDR) under forward bias condition (VDS < 0), experimental and simulation results of QWTFET-based RF detector, oscillator and mixer have demonstrated the potential of QWTFET in these non-logic circuit applications, especially for ultralow standby power applications.<br>by Tao Yu.<br>Ph. D.
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Cavalheiro, David. "Ultra-low power circuits based on tunnel FETs for energy harvesting applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/406391.
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There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today.
The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadratically with the decrease of power supply voltage, leakage power presents a limitation due to the inverse sub-threshold slope (SS). A power supply reduction implies a consequent threshold voltage reduction that, given the fixed SS, cause an exponential increase in leakage current. This poses a limitation in the reduction of power consumption that is inherent to the conventional thermionicbased transistors (MOSFETS and FinFETs). In thermionic-based transistors the SS at room temperature is limited to 60 mV/dec.
To circumvent the SS limitation of conventional transistors, devices with different carrier
injection mechanisms independent of the thermal (Boltzmann) distribution of mobile charge carriers are required. The Tunnel Field-Effect Transistor (TFET) is presented as the most promising post CMOS-technology due to its non-thermal carrier injection mechanism based on Band-To-Band Tunneling (BTBT) effect. TFETs are known as steep slope devices (SS < 60 mV/dec at room temperature). Large current gain (ION/IOFF > 105) at low voltage operation (sub-0.25 V) and extremely low leakage current have already been demonstrated, placing TFETs as serious candidates for ultra-low power and energy efficient circuit applications. TFETs have been explored mostly in digital circuits and applications.
In this thesis, the use of TFETs is explored as an alternative technology also for ultra-low power and voltage conversion and management circuits, suited for weak energy harvesting (EH) sources.
As TFETs are designed as reverse biased p-i-n diodes (different doping types in source/drain regions), the particular electrical characteristics under reverse bias conditions require changes in conventional circuit topologies. Rectifiers, charge pumps and power management circuits (PMC) are designed and analyzed with TFETs, evaluating their performance with the proposal of new topologies that extend the voltage/power range of operation compared to current technologies and circuit topologies. TFET-based PMCs for RF and DC EH sources are proposed and limitations (with solutions) of using TFETs in conventional inductor-based boost converters identified.<br>Ha habido una tremenda evolución en la tecnología de circuitos integrados en las últimas décadas. Con el escalado de transistores de metal-óxido-semiconductor (CMOS), se han hecho posibles chips más rápidos, con menos consumo de energía y más complejos con menos área y esto ha posibilitado la existencia de los aparatos electrónicos que vemos en la actualidad.
La creciente demanda de portabilidad implica que el consumo de energía es un indicador clave en el diseño analógico y digital. Mientras que el consumo de potencia dinámica disminuye cuadráticamente con la disminución de la tensión de fuente de alimentación, la potencia de fugas presenta una limitación debido a la pendiente sub-umbral inverso (sub-threshold slope, SS). Una reducción de la tensión de alimentación implica una consecuente reducción de tensión umbral a fin de mantener las prestaciones que, dado el SS fijo, causa un aumento exponencial de la corriente de fuga. Esto plantea una limitación en la reducción de consumo de energía que es inherente a los transistores convencionales basados en inyección de portadores termoiónicos (MOSFETS y FinFETs). En transistores termoiónicos la SS a temperatura ambiente está limitado a 60 mV / dec.
Para eludir la limitación SS de transistores convencionales se requieren dispositivos con mecanismos diferentes de inyección de portadores. El transistor túnel de efecto campo (TFET) se presenta como la tecnología más prometedora debido a su mecanismo de inyección de portadores no térmico basado en el efecto Band-To-Band Tunneling (BTBT). Los TFETs se conocen como dispositivos de alta pendiente sub-umbral (SS <60 mV / dec a temperatura ambiente). Han sido ya demostradas ganancias de corriente elevadas (ION / IOFF> 10 ^ 5) en operación de baja tensión (sub-0,25 V) y una corriente de fugas extremadamente bajo, colocando los TFETs como serios candidatos para aplicaciones de circuitos eficientes de ultra-baja potencia y energía. Los TFETs se han explorado sobre todo en circuitos digitales y aplicaciones.
En esta tesis, el uso de TFETs se explora como una tecnología alternativa también para circuitos de potencia y de conversión de tensión ultra-bajas, adecuada para fuentes de energía del ambiente, usualmente muy limitadas en magnitud. Debido a que los TFETs están diseñados como diodos p-i-n en polarización inversa (hay diferente tipo de dopaje en las regiones fuente / drenador), sus características eléctricas particulares en condiciones de polarización inversa requieren cambios en las topologías de circuito convencionales. En la tesis, rectificadores, bombas de carga y circuitos de gestión de la energía (PMC) con TFETs se diseñan y analizan, realizando una evaluación de su rendimiento con la propuesta de nuevas topologías que extienden el rango de tensión y potencia de operación en comparación con tecnologías y topologías de circuitos actuales. Se proponen PMCs basados en TFET para fuentes de RF y DC y se identifican las limitaciones (con soluciones) de la utilización de TFETs en convertidores elevadores convencionales basados en inductores.<br>Hi ha hagut una tremenda evolució en la tecnologia de circuits integrats en les últimes dècades. Amb l'escalat de transistors de metall-òxid-semiconductor (CMOS), s'han fet possibles xips més ràpids, amb menys consum d'energia i més complexos amb menys àrea i això ha possibilitat l'existència dels aparells electrònics que veiem en l'actualitat. La creixent demanda de portabilitat implica que el consum d'energia és un indicador clau en el disseny analògic i digital. Mentre que el consum de potència dinàmica disminueix quadràticament amb la disminució de la tensió de font d'alimentació, la potència de fuites presenta una limitació a causa del pendent sub-llindar invers (sub-threshold slope, SS). Una reducció de la tensió d'alimentació implica una conseqüent reducció de tensió llindar a fi de mantenir les prestacions que, donat el SS fix, causa un augment exponencial del corrent de fuita. Això planteja una limitació en la reducció de consum d'energia que és inherent als transistors convencionals basats en injecció de portadors termoiònics (MOSFETS i FinFETs). En transistors termoiònics la SS a temperatura ambient està limitat a 60 mV / dec. Per eludir la limitació SS de transistors convencionals es requereixen dispositius amb mecanismes diferents d'injecció de portadors. El transistor túnel d'efecte camp (TFET) es presenta com la tecnologia més prometedora a causa del seu mecanisme d'injecció de portadors no tèrmic basat en l'efecte Band-To-Band Tunneling (BTBT). Els TFETs es coneixen com a dispositius d'alt pendent sots-llindar (SS <60 mV / dec a temperatura ambient). Han estat ja demostrats guanys de corrent gran (ION / IOFF> 10 ^ 5) en operació de baixa tensió (sub-0,25 V) i un corrent de fuites extremadament baix, col·locant els TFETs com a seriosos candidats per a aplicacions de circuits eficients d'ultra-baixa potència i energia. Els TFETs s'han explorat sobretot en circuits digitals i aplicacions. En aquesta tesi, l'ús de TFETs s'explora com una tecnologia alternativa també per a circuits de potència i de conversió de tensió ultra-baixes, adequada per a fonts d'energia de l'ambient, usualment molt limitades en magnitud. Degut a que els TFETs estan dissenyats com díodes p-i-n en polarització inversa (hi ha diferent tipus de dopatge en les regions font / drenador), les seves característiques elèctriques particulars en condicions de polarització inversa requereixen canvis en les topologies de circuit convencionals. En la tesi, rectificadors, bombes de càrrega i circuits de gestió de l'energia (PMC) amb TFETs es dissenyen i analitzen, realitzant una avaluació del seu rendiment amb la proposta de noves topologies que estenen el rang de tensió i potència d'operació en comparació amb tecnologies i topologies de circuits actuals. Es proposen PMCs basats en TFET per fonts de RF i DC i s'identifiquen les limitacions (amb solucions) de la utilització de TFETs en convertidors elevadors convencionals basats en inductors.
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Richter, Simon [Verfasser]. "Strained silicon and silicon-germanium nanowire tunnel FETs and inverters / Simon Richter." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2014. http://d-nb.info/1059533189/34.
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Narimani, Keyvan [Verfasser], Joachim [Akademischer Betreuer] Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.
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Narimani, Keyvan Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.
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Blaeser, Sebastian Verfasser], Siegfried [Akademischer Betreuer] [Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.
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Riederer, Felix [Verfasser]. "Skalierung von Tripel & Multi Backgate Bauteilen für die Herstellung von Tunnel- & Superlattice-FETs / Felix Riederer." München : Verlag Dr. Hut, 2018. http://d-nb.info/1164293710/34.
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Blaeser, Sebastian [Verfasser], Siegfried [Akademischer Betreuer] Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.
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Luong, Gia Vinh Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Gate-All-Around Silicon Nanowire Tunnel FETs for Low Power Applications / Gia Vinh Luong ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1162559780/34.
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Sterkel, Martin. "Ultra-Kurzkanal Tunnel-Feldeffekt-Transistoren auf Silizium- und SOI-Substraten." Göttingen Cuvillier, 2008. http://d-nb.info/990746445/04.
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Ramesh, Anisha. "TUNNELING BASED QUANTUM FUNCTIONAL DEVICES AND CIRCUITS FOR LOW POWER VLSI DESIGN." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1338315073.
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Haffner, Thibault. "Elaboration et intégration de nanofils GeSn pour la réalisation de dispositifs nanoélectroniques basse consommation." Thesis, Université Grenoble Alpes, 2020. https://tel.archives-ouvertes.fr/tel-03066536.
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Depuis les années 60, le développement technologique est principalement porté par la miniaturisation des composants et suit la fameuse conjoncture de Moore. En effet, la miniaturisation apportait, au début, de nombreux avantages. Temps de commutation plus faible, systèmes plus compacts, tension d'alimentation plus faible, et donc, transistors consommant moins, etc. Seulement, cette approche a commencé à s'essouffler ces dernières années. En effet , les limites de la miniaturisation ont commencés à apparaitre et la puissance consommée globale des circuits a commencé à augmenter ce qui limite la réalisation des systèmes. Il devient alors nécessaire de développer des composants basse consommation, tels que les transistors à effet tunnel. Ces transistors ont, à ce jour, un défaut majeur qui est leurs courants à l'état passant, bien plus faible que les MOSFET. Ce courant dépend majoritairement de l'architecture du transistor ainsi que de la largeur de la bande interdite du matériau de l'électrode "source".Nous proposons dans cette thèse d'élaborer et d'étudier des nanofils et des hétérostructures à base de l'alliage germanium-étain. Le $Ge_{1-x}Sn_x$ est un alliage de la colonne IV qui possède un gap très faible, inférieur à 0,66 eV avec la particularité de passer d'un gap indirect à un gap direct à partir d'une concentration de 10% d'étain, ce qui est favorable aux transistors à effet tunnel. Les nanofils ont été élaborés par dépôt chimique en phase vapeur en utilisant le mécanisme vapeur-liquide-solide et des analyses physico-chimiques telles la spectroscopie à rayon X et la spectroscopie par nano-Auger ont été mises en œuvre pour les caractériser. Des hypothèses ont été émises afin de comprendre les mécanismes impliqués dans la croissance de nanofils GeSn et d'en maitriser au mieux l'élaboration. Des hétérostructures axiales qui serviront comme matériaux de base pour la réalisation de transistors à effet tunnel sont présentées et détaillées. Nous présentons par la suite l'étude de l'interface GeSn/diélectrique dans le but d'améliorer les performances des capacités MOS sur GeSn, et donc d'améliorer les dispositifs nanoélectroniques. Des traitements chimiques ont été appliqués sur la surface du GeSn, et des analyses XPS et pAR-XPS ont été menées afin de déterminer l'efficacité des traitements. Afin d'améliorer les performances des capacités MOS, nous avons déposé un empilement formée d'une couche interfaciale suivie d'un diélectrique à forte permittivité, tel que le $HfO_2$, dans le but d'obtenir une densité d'états d'interface la plus faible possible. Enfin, l'intégration et l'étude de transistors à effet tunnel à base d'hétérostructures sont présentées. Nous présentons dans un premiers temps les étapes de développement technologiques développées afin de réaliser les dispositifs nanoélectroniques. Les niveaux de dopage des hétérostructures ont été évalués par le biais de mesures de résistivités. Les performances des transistors à effet tunnel ont été évaluées à l'aide de mesures électriques et ont été confrontées à l'état de l'art actuel<br>Since the 1960's, technological development has been mainly driven by the miniaturization of components and follows the famous Moore's law. Indeed, miniaturization brought many advantages at the start. Lower switching time, more compact systems, lower supply voltage, and therefore, transistors consuming less, etc. However, this approach has started to falter in recent years. Indeed, the limits of miniaturization began to appear and the overall power consumption of the circuits began to increase which limits the realization of the systems. It then becomes necessary to develop low-consumption components, such as tunnel effect transistors. These transistors have, to date, a major defect which is their currents in the on state, much weaker than the MOSFETs. This current depends mainly on the architecture of the transistor as well as on the gap width of the source material.In this thesis, we propose to develop and study nanowires and heterostructures based on the germanium-tin alloy. The $ Ge_{1-x}Sn_x $ is an alloy of column IV which has a very small gap, less than 0.66 eV with the particularity of passing from an indirect gap to a direct gap from a concentration 10% of tin, which is favorable to tunnel effect transistors. Nanowires were developed by chemical vapor deposition using the vapor-liquid-solid mechanism and physicochemical analyzes such as X-ray spectroscopy and nano-Auger spectroscopy were used to characterize them. Hypotheses have been put forward in order to understand the mechanisms involved in the growth of GeSn nanowires and to better control their development. Axial heterostructures which will serve as basic materials for the realization of tunnel effect transistors are presented and detailed. We then present the study of the GeSn/dielectric interface in order to improve the performance of MOS capacities on GeSn, and therefore, to improve nanoelectronic devices. Chemical treatments were applied to the GeSn surface, and XPS and pAR-XPS analyzes were conducted to determine the effectiveness of the treatments. In order to improve the performance of the MOS capacities, we deposited a stack formed of an interfacial layer followed by a dielectric with high permittivity, such as $ HfO_2$, in order to obtain a low interface trap density. Finally, the integration and study of tunnel effect transistors based on heterostructures are presented. We first present the technological development stages developed in order to produce nanoelectronic devices. The doping levels of the heterostructures were evaluated by means of resistivity measurements. The performances of tunnel effect transistors were evaluated using electrical measurements and were compared with the current state of the art
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Brouzet, Virginie. "Réalisation et étude des propriétés électriques d'un transistor à effet tunnel 'T-FET' à nanofil Si/SiGe." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT120/document.
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La demande d’objets connectés dans notre société est très importante, au vu du marché florissant des smartphones. Ces nouveaux objets technologiques ont pour avantage de regrouper plusieurs fonctions en un seul objet ultra compact. Cette diversité est possible grâce à l’avènement des systèmes-sur-puce (SoC, System-on-Chip) et à la miniaturisation extrême des composants. Les SoC s’intègrent dans l’approche « More than Moore » et demande une superficie importante des puces. Celle-ci peut-être réduite par l’utilisation d’une autre approche appelée « More Moore » qui fut largement utilisée ces dernières années pour miniaturiser la taille des transistors. Cependant cette approche tend vers ses limites physiques puisque la réduction drastique de la taille des MOSFETs (« Metal Oxide Semicondutor Field Effect Transistor ») ne pourra pas être poursuivie à long terme. En outre, les transistors de taille réduite présentent des effets parasites, liés aux effets de canaux courts et à une mauvaise dissipation de la chaleur dégagée lors du fonctionnement des MOSFETs miniaturisés. Les effets de canaux courts peuvent-être minimisés grâce à de nouvelles architectures, telles que l’utilisation de nanofils, qui permettent d’obtenir une grille totalement enrobante du canal. Mais le problème de la puissance de consommation reste un frein pour le passage au prochain nœud technologique et pour l’augmentation des fonctions dans les appareils nomades. En effet, la puissance de consommation des MOSFETs ne fait qu’augmenter à chaque nouvelle génération, ce qui est en partie dû à l’accroissement des pertes énergétiques induites par la puissance statique de ces transistors. Pour diminuer celle-ci, la communauté scientifique a proposée plusieurs solutions, dont une des plus prometteuses est le transistor à effet tunnel (TFET). Car ce dispositif est peu sensible aux effets de canaux courts, et il peut fonctionner à de faibles tensions de drain et avoir un inverse de pente sous le seuil inférieur à 60mV/dec. L’objectif de la thèse est donc de fabriquer et de caractériser des transistors à effet tunnel à base de nanofil unique en silicium et silicium germanium. Nous présenterons la croissance et l’intégration des nanofils p-i-n en TFET. Puis nous avons étudié l’influence de certains paramètres sur les performances de ces transistors, et en particulier, l’effet du niveau de dopage de la source et du contrôle électrostatique de la grille sera discuté. Ensuite, l’augmentation des performances des TFETs sera montrée grâce à l’utilisation de semiconducteur à petit gap. En effet, nous insérons du germanium dans la matrice de silicium pour en diminuer le gap et garder un matériau compatible avec les techniques de fabrication de l’industrie de la microélectronique. Un modèle de simulation du courant tunnel bande à bande a été réalisé, se basant sur le modèle de Klaassen. Les mesures électriques des dispositifs seront comparées aux résultats obtenus par la simulation, afin d’extraire le paramètre B de la transition tunnel pour chacun des matériaux utilisés. Enfin nous présenterons les améliorations possibles des performances par une intégration verticale des nanofils<br>The connected objects demand in our society is very important , given the successfull smartphone market. These newtechnological objects have the advantage to combine several functions in one ultra compact object. This diversity is possibledue to the advent of system-on-chip (SoC) and the components scaling down. The SoCs are into the More than Mooreapproach and require a large chips area, which can be reduced by the use of "More Moore" approach which was widelyused in recent years to scale down the transistors. However, this approach tends to physical limitations since the drasticscaling down of the MOSFETs ("Metal Oxide Field Efect Transistor Semicondutor") can not be continued in the future. Inaddition, the nanoŰMOSFET have parasitic efects, related to short-channel efects and a low heating dissipation. Theshort channel efects can be minimized thanks to new architectures, such as the use of nanowires, which enable a gate allaround of the channel. But the power consumption problem still drag on the transition to the next technology node and theaddition of new functions in mobile devices. Indeed, the MOSFETŠs consumed power increases with each new generation,which is mainly due to the static power increase of these transistors. To reduce it, the scientiĄc community has proposedseveral solutions, and one of the most promising is a tunnel efect transistor (TFET). Because this device exhibit lessshort-channel efects compared to the conventional MOSFET, it can operate at low drain voltages and their subthresholdslope could be lower than 60 mV/dec. The thesis aims are to fabricate and characterize tunneling transistors based onsingle silicon nanowire and silicon germanium. We will present the growth and integration of pŰiŰn nanowires TFET. Thenwe investigated the inĆuence of some parameters on the electrical performance of these transistors, in particular, the efectof the source doping level and the electrostatic gate control will be discussed. In the next part, the increase of TFETsperformance will be shown thanks to the small band-gap semiconductor use. Indeed, we insert germanium in the silicon dieto reduce the bandgap and keep a material compatible with the CMOS manufacturing. A band to band tunneling modelwas used to calculate the device current, based on the model Klaassen. Electrical measurements will be compared to thesimulated results, in order to extract the B parameter of tunnel transition for each materials used. Finally we will presentthe possible performance improvements thanks to the vertical nanowires integration
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Fu, Yen-Chun. "Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS." Thesis, University of Glasgow, 2018. http://theses.gla.ac.uk/30588/.
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The main objective of this thesis is realising a non-planar III-V Tunnel-FET for low power device applications. The differentiating aspect of this work is based around clustered inductively coupled plasma (ICP) etch and atomic layer deposition (ALD) tools. This approach was intended to mitigate native oxide formation on etched III-V surfaces prior to gate stack deposition by ALD. The use of a cluster tool also offers the benefit of cleaning III-V surfaces “in-situ” using low damage plasma based approaches. In addition, activity on scaling the equivalent oxide thickness of the gate stack and evaluating different heterostructures are explored in this work for the realisation of high performance TunnelFET. Initially, gate stacks on both p- and n- (110)-oriented In0.53Ga0.47As were examined to understand the basic electrical properties of these interfaces, important for non-planar device architectures. An optimised process, based on ex-situ sulphur-based passivation before ALD of gate dielectrics, and forming gas annealing (FGA) after gate metal deposition, is demonstrated for the first time to show significant Fermi level movement through the bandgap. Quantitatively, interface state density (Dit) values in the range of 0.87-1.8 × 1012 cm-2eV-1 around the midgap energy level were obtained. The lowest Dit value is estimated to be 3.1 × 1012 cm-2eV-1 close to the conduction band edge showing the combination of sulphur passivation and (FGA) is effective is passivating the trap states in the upper half of the bandgap on Al2O3/In0.53Ga0.47As (110) MOSCAPs. Furthermore, by analysis of CV hysteresis biasing at 1.1 V beyond the flatband voltage, the border trap density on n-type MOSCAPs was observed to reduce, after FGA from 1.8 × 1012 cm-2 to 5.3 × 1011 cm-2. The result observed in p-type MOSCAPs is in contrast, with increasing border trap density from 7.3 × 1011 cm-2 to 1.4 × 1012 cm-2 under the similar bias condition, i.e. the FGA process is not as effective in passivating states close to the valence band. In addition, the analysis undertaken in this thesis determined the value of the conduction band offset at the Al2O3/In0.53Ga0.47As (110) to be is 1.81eV – the first report of this parameter. The non-planar devices of this work also require low damage etching processes for fin/wire formation. Therefore, the performance of in-situ deposited gate stacks to In0.53Ga0.47As (100)- and (110)-oriented substrates which had been subjected to a CH4/Cl2/H2 based ICP etch chemistry, which forms vertical InGaAs sidewall profiles, were assessed. Based on CV and IV, and X-ray Photo-Spectroscopy (XPS) spectral analyses, the performance of gate stacks deposited on (110)-oriented In0.53Ga0.47As subjected to a ICP dry etch suffers more damage compared to gate stacks on (100)-oriented In0.53Ga0.47As. To minimise the etching damage, cyclic TMA/plasma gas pretreatment prior to ALD is introduced on both (100)- and (110)-oriented surfaces. The interface trap density of gate stacks on (110)-oriented In0.53Ga0.47As with TMA/H2 gas pre-treatment improves from 6 × 1011 cm-2eV-1 to 2.8 × 1011 cm-2eV-1 close to the conduction band edge. Based on this in-situ gate stack process, a gate stack with reduced capacitor equivalent thickness (CET) on both (100) and (110) oriented surfaces are achieved by using a TiN layer deposited in-situ by ALD before ex-situ gate metal deposition. The lowest CET was around 1.09 nm for a HfO2/TiN stack deposited on (100)-oriented In0.53Ga0.47As. This optimised gate stack was included in an InGaAs-based tunnel-FET process flow using p-n, p-i-n, and p-n-i-n heterostructures. Comparing with p-n Tunnel-FETs, the pi-n structure provides better electrical characteristics for In0.53Ga0.47As with a subthreshold swing (SS) of 120 mV/dec at the condition of VDS = 0.05V. The peak transconductance peak of the p-i-n Tunnel-FET at the condition of VDS = 0.3V is around 6 uS/um. Next, an inserted n-pocket p-n-i-n Tunnel-FET was studied. In addition to providing comparable on current with the p-i-n Tunnel-FET of 1.1 uA/um at the bias condition of VDS = 300mV, the subthreshold swing of the p-n-i-n devices improves by 46% due to the lower leakage floor from the n-pocket layer incorporation. Most importantly, the non-planar configuration of the p-n-i-n Tunnel-FET improves both the SS and on-current to 152 mV/dec at the bias condition of VDS = 300mV and 1.3 uA/um at the bias condition of VDS = 500mV and VGS = 900mV, respectively. Above these aspects and benchmark, all this data implies that a non-planar p-n-i-n InGaAs TunnelFET is a promising candidate for future generations of low power applications.
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Wan, Jing. "Dispositifs innovants à pente sous le seuil abrupte : du TEFT au Z²-FET." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00845632.
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Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d'effet tunnel. Un modèle analytique combinantl'effet tunnel et le transport dans le canal a été développé, montrant un bon accord entre les résultatsexpérimentaux et les simulations.Nous avons conçu et démontré un nouveau dispositif (Z2-FET, pour pente sous le seuil verticale et zéroionisation par impact), qui présente une commutation extrêmement abrupte (moins de 1 mV par décade decourant), avec un rapport ION / IOFF >109, un large effet de hystérésis et un potentiel de miniaturisation jusqu'à 20nm. La simulation TCAD a été utilisée pour confirmer que la commutation électrique du Z2-FET fonctionne parl'intermédiaire de rétroaction entre les flux des électrons et trous et leurs barrières d'injection respectives. LeZ2-FET est idéalement adapté pour des applications mémoire à un transistor. La mémoire DRAM basée sur leZ2-FET montre des performances très bonnes, avec des tensions d'alimentation jusqu'à 1,1 V, des temps derétention jusqu'à 5,5 s et des vitesses d'accès atteignant 1 ns. Une mémoire SRAM utilisant un seul Z²-FET estégalement démontrée sans nécessité de rafraichissement de l'information stockée.Notre travail sur le courant GIDL intervenant dans les MOSFETs de type FDSOI a été combiné avec leTFET afin de proposer une nouvelle structure de TFETs optimisés, basée sur l'amplification bipolaire du couranttunnel. Les simulations de nouveau dispostif à injection tunnel amélioré par effet bipolaire (BET-FET) montrentdes résultats prometteurs, avec des ION supérierus à 4mA/��m et des pentes sous le seuil SS inférieures à 60mV/dec sur plus de sept décades de courant, surpassant tous les TFETs silicium rapportés à ce jour.La thèse se conclut par les directions de recherche futures dans le domaine des dispositifs à pente sous leseuil abrupte.
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Revelant, Alberto. "Modélisation, simulation et caractérisation de dispositifs TFET pour l'électronique à basse puissance." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT022.
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Dans les dernières années, beaucoup de travail a été consacré par l’industrie électronique pour réduire la consommation d’énergie des composants micro-électroniques qui représente un fardeau important dans la spécification des nouveaux systèmes.Afin de réduire la consommation d’énergie, nombreuses stratégies peuvent être adoptées au niveau des systèmes micro-électroniques et des simples dispositifs nano-électroniques. Récemmentle Transistor Tunnel `a effet de champ (Tunnel-FET) s’est imposé comme un candidat possible pour remplacer les dispositifs MOSFET conventionnels pour applications de tr`es basse puissance à des tensions d’alimentation VDD < 0.5V. Nous présentons un modèle Multi-Subband Monte Carlo modifié (MSMC) qui a été adapté pour la simulation de TFET Ultra Thin Body Fully Depleted Seminconductor on Insulator (FDSOIUTB) avec homo- et hétéro-jonctions et des matériaux semi-conducteurs arbitraires. Nous prenons en considération la quantification de la charge avec une correction quantique heuristique mais précise, validée via des modèles quantiques complets et des résultats expérimentaux.Le modèle MSMC a été utilisé pour simuler et évaluer la performance de FD-SOI TFET sidéealisées avec homo- et hétéro-jonction en Si, alliages SiGe ou composés InGaAs. Dans la deuxième partie de l’activité de doctorat un travail de caractérisation à basse températurea été réalisé sur les TFETs en Si et SiGe homo- et hétéro-jonction fabriqués par le centre de recherche français du CEA -LETI. L’objectif est d’estimer la présence de l’effet Tunnel comme principal mécanisme d’injection et la contribution d’autres mécanismes d’injection comme le Trap Assisted Tunneling<br>In the last years a significant effort has been spent by the microelectronic industry to reducethe chip power consumption of the electronic systems since the latter is becoming a majorlimitation to CMOS technology scaling.Many strategies can be adopted to reduce the power consumption. They range from thesystem to the electron device level. In the last years Tunnel Field Effect Transistors (TFET)have imposed as possible candidate devices for replacing the convential MOSFET in ultra lowpower application at supply voltages VDD < 0.5V. TFET operation is based on a Band-to-BandTunneling (BtBT) mechanism of carrier injection in the channel and they represent a disruptiverevolutionary device concept.This thesis investigates TFET modeling and simulation, a very challenging topic becauseof the difficulties in modeling BtBT accurately. We present a modified Multi Subband MonteCarlo (MSMC) that has been adapted for the simulation of Planar Ultra Thin Body (UTB)Fully Depleted Semiconductor on Insulator (FD-ScOI) homo- and hetero-junction TFET implementedwith arbitrary semiconductor materials. The model accounts for carrier quantizationwith a heuristic but accurate quantum correction validated by means of comparison with fullquantum model and experimental results.The MSMC model has been used to simulate and assess the performance of idealized homoandhetero-junction TFETs implemented in Si, SiGe alloys or InGaAs compounds.In the second part of the thesis we discuss the characterization of TFETs at low temperature.Si and SiGe homo- and hetero-junction TFETs fabricated by CEA-LETI (Grenoble,France) are considered with the objective to identify the possible presence of alternative injectionmechanisms such as Trap Assisted Tunneling<br>Negli ultimi anni uno sforzo significativo `e stato speso dall’industria microelettronica per ridurreil consumo di potenza da parte dei sistemi microelettronici. Esso infatti sta diventando unadelle limitazioni pi`u significative per lo scaling geometrico della tecnologia CMOS.Diverse strategie possono essere adottate per ridurre il consumo di potenza considerando ilsistema microelettronico nella sua totalit`a e scendendo fino a giungere all’ottimizzazione delsingolo dispositivo nano-elettronico. Negli ultimi anni il transistore Tunnel FET (TFET) si`e imposto come un possibile candidato per rimpiazzare, in applicazioni a consumo di potenzaestremamente basso con tensioni di alimentazione inferiori a 0.5V, i transistori convenzionaliMOSFET. Il funzionamento del TFET si basa sul meccanismo di iniezione purament quantisticodel Tunneling da banda a banda (BtBT) e che dovrebbe permettere una significativa riduzionedella potenza dissipata. Il BtBT nei dispositivi convenzionali `e un effetto parassita, nel TFETinvece esso `e utilizzato per poter ottenere significativi miglioramenti delle performance sottosogliae pertanto esso rappresenta una nuova concezione di dispositivo molto innovativa erivoluzionaria.Questa tesi analizza la modellizazione e la simulazione del TFET. Questi sono argomenti moltocomplessi vista la difficolt`a che si hanno nel modellare accuratamente il BtBT. In questo lavoroviene presentata una versione modificata del modello di trasporto Multi Subband Monte Carlo(MSMC) adattato per la simulazione di dispositivi TFET planari Ultra Thin Body Fully DepletedSilicon on Insulator (UTB FD-SOI), implementati con un canale composto da un unicosemiconduttore (omogiunzione) o con differenti materiali semiconduttori (eterogiunzione). Ilmodello proposto tiene il conto l’effetto di quantizzazione dovuto al confinamento dei portatoridi carica, con un’euristico ma accurato sistema di correzione. Tale modello `e stato poivalidato tramite una comparazione con altri modelli completamente quantistici e con risultatisperimentali.Superata la fase di validazione il modello MSMC `e utilizzato per simulare e verificare le performancedi dispositivi TFET implementati come omo o eterogiunzione in Silicio, leghe SiGe,o composti semiconduttori InGaAs.Nella seconda parte della tesi viene illustrato un lavoro di caratterizazione di TFET planari abassa temperatura (fino a 77K). Sono stati misurati dispositivi in Si e SiGe a omo o eterogiuzioneprodotti nella camera bianca del centro di ricerca francese CEA-LETI di Grenoble. Tramite talimisure `e stato possibile identificare la probabile presenza di meccanismi di iniezione alternativial BtBT come il Tunneling assistito da trappole (TAT) dimostrando come questo effetto `e,con ogni probabilit`a, la causa delle scarse performance in sottosoglia dei dispositivi TFETsperimentali a temperatura ambiente
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Viereck, Cornelius. "A computer-controlled passive multi-harmonic tuner used to optimise a power FET up to the third harmonic." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0006/MQ42929.pdf.
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Diaz, llorente Carlos. "Caractérisation de transistors à effet tunnel fabriqués par un processus basse température et des architectures innovantes de TFETs pour l’intégration 3D." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT096/document.
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Cette thèse porte sur l’étude de transistor à effet tunnel (TFET) en FDSOI à géométries planaire et triple grille/nanofils. Nous rapportons pour la première fois des TFETs fabriqués par un processus basse température (600°C), qui est identique à celui utilisé pour l’intégration monolithique 3D. La méthode “Dual IDVDS” confirme que ces TFETs fonctionnent par effet tunnel et non pas par effet Schottky. Les résultats des mesures électriques montrent que l’abaissement de la température de fabrication de 1050°C (HT) à 600°C (LT) ne dégrade pas les propriétés des TFETs. Néanmoins, les dispositifs réalisés à basse température montrent un courant de drain et de fuite plus élevés et une tension de seuil différente par rapport aux HT TFETs. Ces phénomènes ne peuvent pas être expliqués par le mécanisme d’effet tunnel. Le courant de pompage de charges révèle une densité d’états d’interface plus grande à l’interface oxide/Si pour les dispositifs LT que dans les TFETs HT pour les zones actives étroites. Par ailleurs, une analyse de bruit basse fréquence permet de mieux comprendre la nature des pièges dans les TFETs LT et HT. Dans les TFETs réalisés à basse température nous avons mis en évidence une concentration en défauts non uniforme à l’interface oxide/Si et à la jonction tunnel qui cause un effet tunnel assisté par piège (TAT). Ce courant TAT est responsable de la dégradation de la pente sous seuil. Ce résultat montre la direction à suivre pour optimiser ces structures, à savoir une épitaxie de très haute qualité et une optimisation fine des jonctions. Finalement, nous avons proposé de nouvelles architectures innovatrices de transistors à effet tunnel. L’étude de simulation TCAD montre que l’extension de la jonction tunnel dans le canal augmente la surface de la région qui engendre le courant BTBT. Une fine couche dopée avec une dose ultra-haute en bore pourrait permettre l’obtention à la fois d’une pente sous le seuil faible et un fort courant ON pour le TFET<br>This thesis presents a study of FDSOI Tunnel FETs (TFETs) from planar to trigate/nanowire structures. For the first time we report functional “Low-Temperature” (LT) TFETs fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration. “Dual IDVDS” method confirms that these devices are real TFETs and not Schottky FETs. Electrical characterization shows that LT TFETs performance is comparable with “High-Temperature” (HT) TFETs (1050°C). However, LT TFETs exhibit ON-current enhancement, OFF-current degradation and VTH shift with respect to HT TFETs that cannot be explained via BTBT mechanism. Charge pumping measurements reveal a higher defect density at the top silicon/oxide interface for geometries with narrow widths in LT than HT TFETs. In addition, low-frequency noise analyses shed some light on the nature of these defects. In LT TFETs, we determined a non-uniform distribution of defects at the top surface and also at the tunneling junction that causes trap-assisted tunneling (TAT). TAT is responsible of the current generation that degrades the subthreshold swing. This indicates the tight requirements for quality epitaxy growth and junction optimization in TFETs. Finally, we proposed novel TFET architectures. TCAD study shows that the extension of the source into the body region provides vertical BTBT and a larger tunneling surface. Ultra-thin heavily doped boron layers could allow the possibility to obtain simultaneously a good ON-current and sub-thermal subthreshold slope in TFETs
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Pallempati, Mallikarjunarao. "Investigation on Spacer Engineered Multigate Tunnel FETs." Thesis, 2016. http://ethesis.nitrkl.ac.in/9274/1/2016_MT_MPallempati.pdf.
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In this modern era of semiconductor technology, the number of transistors per chip are increasing continuously for designing a computing system to perform innumerable of functions with tremendous speed. Thus, the electronics industry is constantly facing the challenge of miniaturization of transistors to increase the package density. Hence scaling of CMOS technology is essential in nano-electronic regime which leads to increase of static power consumption and thus conventional MOSFETs are unsuitable in this situation due to Short Channel Effects (SCEs). Hence the non-conventional devices became significant in order to achieve the requirements of ITRS.
Tunnel FET is one of the emerging devices which exhibits a very low OFF-state current in the order of 10−15A/µm due to its different current flow mechanism i.e., Bandto-Band Tunneling mechanism and thus one of the potential candidate for mitigating power crisis. Also, Tunnel FET is an energy efficient device because, it can achieve a Subthreshold Swing of sub-60mV/decade and also less sensitive towards SCEs which is a benefit over MOSFET. Due to these reasons, Tunnel FETs can replace the ongoing CMOS technology for future low power (LP) applications.
In the proposed work, an underlap silicon n-channel Tunnel Field Effect Transistor (n-TFET) i.e., symmetric single-k spacer (SSS) Double Gate N-TFET (DGTFET) is modeled to improve the performance of the device by using different spacer materials. A detailed investigation has been made on the device characteristics with the help of extensive 2-D TCAD simulations. It is demonstrated that an optimized underlap length has a significant contribution of on-state current (ION ) without deteriorating the off- state current (IOF F ) and sub-threshold swing (SS). The proposed model with different spacer materials has been extensively analyzed by using transfer characteristics, output characteristics, and analog/RF characteristics. The structure is optimized based on the comparison among various performance metrics evaluated by considering different spacer materials like SiO2 (k=3.9), Si3N4 (k=7.5), and HfO2 (k=25).
Further, temperature analysis has been performed with the help of 3-D numerical simulations by proposing Spacer Engineered Trigate Silicon-ON-Insulator (SOI) N-TFET for better Sub-threshold swing (SS) and OFF-state current (IOF F ). The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. A detailed investigation has made on the device characteristics and on various performance metrics in order to ensure its reliability for harsh temperature environment applications. Further, the Spacer Engineered Trigate SOI TFET is subjected to Heavy Ion Irradiation simulation model in order to characterize the device sensitivity towards radiation hardness point of view. A detailed investigation has been made on the Transient operation of the device by analyzing various parameters like electron density, Heavy Ion charge generation, bipolar gain and Transient Drain current. All the simulations presented in this work are done by using TCAD Sentaurus software.
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Mathew, S. "Performance analysis of Dual Material Gate (DMG) Silicon on Insulator (SOI) tunnel fets." Thesis, 2014. http://ethesis.nitrkl.ac.in/6167/1/E-46.pdf.
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As modern day computing systems are designed to perform innumerable number of functions with tremendous speed, the number of circuits to be accommodated in a chip keeps increasing day by day. Hence electronics industry constantly faces the challenge of miniaturization of transistors to increase the package density and thus linear scaling of CMOS technology has become a necessity in the present day microelectronic and nano-electronic regime. This leads to a major crisis of static power consumption and hence conventional MOSFETs fail to be a suitable candidate to handle the situation. Also Short Channel Effects(SCEs) come into picture. So non-conventional devices started gaining its significance to meet the ITRS requirements. A promising candidate that attracted attention was Tunnel FETs which are gated reverse biased p-i-n diodes where ON current would be due to band-to-band tunneling and they exhibit very low OFF current of 10-17 A/µm which makes them a potential solution for power crisis. Also they prove to be an energy efficient electronic switch with a subthreshold swing not limited to 60mV/decade. Negligible Short Channel Effects of these devices gives them an added advantage over conventional MOSFETs .All these features raise up Tunnel FET as superior candidate for future CMOS era. In the presented work, an analysis into the performance of a Dual Material Gate Single Dielectric SOI Tunnel FET has been done. Numerous simulations were done to determine the influence of work functions of both the gate materials on the electrical characteristics of the device. Comparative study was done between Dual Material Gate device and Single Material Gate device with regards to their electrical characteristics as well as SCEs like Drain Induced Barrier Lowering(DIBL) and threshold voltage roll-off. Parameters like intrinsic capacitances as well as transconductances were also determined.
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Wang, Chiu-Ting, and 王秋婷. "Performance Enhancement of III-V Tunnel FETs considering Line Tunneling and Non-uniform Channel Thickness." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/wh3py3.
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碩士<br>國立中央大學<br>電機工程學系<br>106<br>Power scaling is one of the major challenges in modern CMOS technology for ultra-low power applications, such as emerging IoT (Internet of Things) technologies and wearable devices. Lowering the supply voltage (Vdd) is an efficient technique to achieve ultra-low power consumption for circuits. Device with steep subthreshold slope is essential in order to achieve energy-efficient switching and low leakage power as supply voltage scaling. Conventional MOSFET exhibits the lower-bound limitation of subthreshold swing (SS) which is about 60 mV/dec at room temperature. Tunneling field-effect transistors (TFETs) have been actively explored to tackle this problem and provide steep subthreshold slope below 60mV/dec [1].
Tunnel field-effect transistors (Tunnel FETs, TFETs), which have a subthreshold swing below 60 mV/decade, were proposed as an alternative to conventional MOSFETs in response to the quest for lower power consumption integrated circuits. III-V channel materials become promising materials for TFETs due to their lower bandgap which leads to better tunneling efficiency. However, III-V TFETs still show lower drive current than conventional Si MOSFET at high supply voltage due to their low density of states.
This work aims at structure optimization of III-V TFETs for improving the drive current based on InGaAs/GaAsSb heterostructures. The InGaAs/GaAsSb TFET simulation framework with TCAD tool was established in this work. First, a novel TFET structure with line tunneling was proposed and analyzed comprehensively. By inserting an expitaxial layer between source and gate dielectric regions, TFET consists both lateral point tunneling and line tunneling. Compared with the conventional p-i-n TFET with point tunneling only. The on current of TFETs with epi layer and line tunneling can be further increased due to the increased tunneling area. We analyze the impact of device design on the TFET with epi layer comprehensively. The impacts of epi layer thickness (Tepi), gate-to-source overlap length (Lovs), source thickness, and gate-to-drain underlap length (Lund) on the Id-Vg characteristics of heterojunction III-V TFETs were analyzed comprehensively in this work. This study provides the device design guidelines for performance enhancement of TFETs with epi layer. Compared with the conventional TFET without epitaxial layer, the heterojunction TFET with epitaxial layer and gate to source overlap length = 10 nm shows 3.3 times higher on currents and Ion = 406 (μA/μm) at Vdd = 0.5V.
Sencond, GaAs1-xSbx/In1-yGayAs heterojunction TFETs with bandgap engineering by using non-uniform channel thickness (Tch) are analyzed comprehensively for improving Ion and suppressing ambipolar leakage. Quantum confinement induced bandgap widening as a function of Tch is considered. We analyze the impact of source doping concentration (Ns), drain doping comcentration (Nd), and channel thickness (Tch) on the Id-Vg characteristics of uniform Tch Type II and Type III heterojunction TFETs. The impact of source/channel junction thickness (Ts), drain/channel junction thickness (Td), and thicker channel length (LW) on the Id-Vg characteristics of non-uniform type-II TFETs are also analyzed comprehensively. Finally, the Ioff of type-III non-uniform TFETs can be further reduced by using gate-to-drain underlap design. The Ioff can be improved by 70% as Lund changes from 0 nm to 8 nm.
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Palle, Dharmendar Reddy. "Modeling of graphene-based FETs for low power digital logic and radio frequency applications." 2013. http://hdl.handle.net/2152/22008.
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There are many semiconductors with nominally superior electronic properties compared to silicon. However, silicon became the material of choice for MOSFETs due to its robust native oxide. With Moore's observation as a guiding principle, the semiconductor industry has come a long way in scaling the silicon MOSFETs to smaller dimensions every generation with engineering ingenuity and technological innovation. As per the 2012 International Technology Roadmap for Semiconductors (ITRS), the MOSFET is expected to be scaled to near 6 nm gate length by 2025. However, materials, design and fabrication capabilities aside, basic physical considerations such as source to drain quantum mechanical tunneling, channel to gate tunneling, and thermionic emission over the channel barrier suggest an end to the roadmap for CMOS is on the horizon. The semiconductor industry is already aggressively looking for the next switch which can replace the silicon FET in the long term. My Ph.D. research is part of the quest for the next switch. The promises of process compatibility with existing CMOS technologies, fast carriers with high mobilities, and symmetric conduction and valence bands have led to graphene being considered as a possible alternative to silicon. This work looks at three devices based on graphene using first principles atomistic transport simulations and compact models capturing essential physics: the large-area graphene RF FET, the Bilayer pseudoSpin FET, and the double electron layer resonant tunneling transistor. The characteristics and performance of each device is explored with a combination of SPICE simulations and atomistic quasi static transport simulations. The BiSFET device was found to be a promising alternative to CMOS due to extremely low power dissipation. Finally, I have presented formalism for efficient simulation of time dependent transport in graphene for beyond quasi static performance analysis of the graphene based devices explored in this work.<br>text
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Wang, Yu-Wei, and 王佑瑋. "Theoretical Investigation of Optimized Nanowire Diameter and Short Channel Effects for Gate-All-Around III-V Tunnel FETs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/44732999900811713543.
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碩士<br>國立交通大學<br>電子研究所<br>105<br>This thesis investigates the diameter dependence for III-V gate-all-around homojunction and heterojunction TFET using TCAD numerical simulation. The optimized diameter has been shown due to the counterbalance of the gate control and the quantum confinement effect. In addition, model calculation for the homojunction TFET is proposed and verified with TCAD numerical simulation. Source and drain depletion is very important in modeling of TFET. The diameter dependence by model calculation also shows the same trend with TCAD numerical simulation. Finally, the short channel effect of TFET has been compared with MOSFET with considering the source-to-drain tunneling current for MOSFET. Our results indicate the scalability of MOSFET is worse than TFET due to the lowering of the tunneling barrier and the tunneling length with decreasing the gate length.
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Bhattacharjee, Shubhadeep. "Materials, Processes and Device Design for High Performance, Sub-thermionic MoS2 FETs." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/4268.
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The shrinking of the field-effect transistor (FET), commonly termed CMOS scaling, has revolutionised the semiconductor industry and impacted most aspects of human life. However, this decades-long successful trend of scaling the FET is now facing serious fundamental and technological challenges resulting in diminishing economic returns. The first challenge is that, as device dimensions shrink, electric fields in close proximity start to interfere with each other and disrupt the transistor’s operations. This phenomenon is called the short channel effect (SCE). Second, concurrent (quadratic) reduction in power consumption, an important aspect of scaling, is not possible because of the inability to reduce supply voltage below 1 V. This is primarily because the fundamental nature of charge transport governed by Boltzmann’s statistics restricts the sub-threshold swing (SS, abruptness between OFF to ON transitions) of FETs to the thermionic limit of 60 mV/dec at room temperature. Hence, as we cram in more transistors into the same footprint, energy dissipation and heat management have become fundamental bottlenecks. Clearly, the road ahead needs breakthroughs in new materials and device design.
In this thesis, we attempt to tackle both these challenges (SCE and power consumption) by developing high performance, sub-thermionic (SS<60 mV/dec) transistors on 2D semiconductors. Excellent electrostatics inherent to 2D semiconductors make them promising candidates for mitigating SCE, with recent demonstrations of sub-10 nm channel length molybdenum disulphide (MoS2) FETs. However, the development of sub-thermionic transistors on 2D semiconductors has been stymied by inefficient contacts, doping and dielectric integration, which motivates the initial portion of this work. First, we demonstrate how a facile sulfur-based solution can be employed to engineer surface states between MoS2/metal contacts, resulting in substantial reduction in Schottky barrier height. This enables record performance due to a ~6x/10x (Ni/Pd) reduction in contact resistance, along with complete mitigation in contact variability. In addition, through an empirical model we can predict the intrinsic limit of contact resistance in multilayer TMDs. Second, we develop an air-stable, area-selective, CMOS-compatible counterdoping strategy through vacancy engineering, enabling p-FETs and in-plane p/n junction photodioides. Third, we lay a two-part focus on dielectrics. In the first part, we examine the interplay of different scattering mechanisms in 2D charge transport and demonstrate ‘ideal’ nitride dielectric environments for large performance gains (field-effect mobility ~ 73 cm2V-1s-1). In the second part, we
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break the paradigm of atomic layer deposition and employ functionalisation-free e-beam evaporated top gate high-κ HfO2 to achieve near-perfect SS~60 mV/dec operation. Finally, leveraging on the insights from the previous sections, we demonstrate, for the first time, sub-thermionic transport through tunable Schottky contacts in dual gated MoS2 FETs. Two device configurations, the GT3FET and DVATFET, are expounded. The GT3FET has the flexibility to operate either in the sub-thermionic tunnel regime, yielding steep SS<60 mV/dec OR thermionic high mobility regime. Combining the best of both tunnelling and thermionic regimes in the same operation cycle, the DVATFET, the closest to an ‘ideal transistor’, registers SS~29 mV/dec (3 dec) AND high mobility (100 cm2V-1s-1). This work is envisioned to pave a new path in the development of sub-thermionic, high performance FETs operating in the sub-0.5 V ‘green computing’ regime.<br>MeiTY Visvesvariaya PhD Fellowship
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Lin, Po-Shao, and 林柏劭. "A Study on Performance Evaluation of Fin Epitaxial Tunnel Layer Tunnel FET and Performance Improvement of n-type Epitaxial Tunnel Layer Tunnel FET." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/tf69y7.
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碩士<br>國立交通大學<br>電子研究所<br>105<br>Epitaxial tunnel layer (ETL) tunnel FET (TFET) has been considered to be one of the promising devices in ultra-low power applications. In this study, the performance of the planar ETL TFET and fin ETL TFET for both n-type and p-type, respectively, are evaluated by Sentaurus TCAD simulation. In addition, TFET that is doped by solid-phase diffusion (SPD) instead of ions implantation was proposed and fabricated.
In the previous research, the n-type and p-type ETL TFET show the steep subthreshold swing and high on-state current in the planar structure by TCAD simulation. However, the improvement of the fin structure is not significant in the n-type TFETs (nTFET) in this study. The stronger electrostatic control caused by the fin structure would lead to the Si-to-Ge and Si-to-Si tunneling leakage current at low gate bias. The increased off-state current degrades the subthreshold slope of the fin nTFETand causes the on-state current of the planar nTFET 35% higher than that of the fin nTFET after shifting to Ioff = 1 pA/μm at Vg = 0 V. But the degradation of subthreshold swing is not observed in p-type fin TFET (fin pTFET) because there is only one tunneling path which is Ge-to-Si tunneling at the subthreshold region. Consequently, the planar pTFET shows 40% lower on-state current than the fin pTFET.
In order to improve the epitaxial quality of Ge ETL, SPD was applied to form a defect-free p+ junction in the SPD TFET. The SPD TFET was fabricated and discussed for both n-type and p-type. The severe reverse leakage current of nTFET operation in previous research has been suppressed from 10-8 A/μm to 10-12 A/μm successfully though the Ge ETL is non-uniform. But the SPD nTFET still suffers from the low on-state current because of the insufficient concentration of the p+ junction and the poor Ge ETL. The temperature dependence of the on-state current shows that the transport mechanism in the SPD nTFET is dominated by trap assisted tunneling (TAT).
Though fin structure improves the on-state current of the fin pTFET, it degrades the subthreshold swing and the on-state current of the fin nTFET as well. The planar nTFET is preferred to be applied in low-power circuits optimized for n-type operation, and the fin pTFET is preferred in the circuits optimized for p-type operation. In the SPD TFET, theconcentration of the p+ junction should be increased to improve the efficiency of band to band tunneling (BTBT). Besides, an ultra-thin uniform Ge layer is necessary to suppress the TAT current. If the above suggestions could be achieved, the performance of the SPD TFET will improve further more.
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Wang, Pei-Yu, and 王培宇. "A Study on Tunnel FET with Epitaxial Tunnel Layer Structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/90836541544090748423.
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博士<br>國立交通大學<br>電子工程學系 電子研究所<br>104<br>In this dissertation, tunnel field-effect-transistor (TFET) utilizing band-to-band tunneling (BTBT) as the operation mechanism is studied. To realize the basic characteristics and the design issues for the novel device, the effects of the source junction profiles and the trap-assisted tunneling (TAT) on the bulk TFET are investigated. To further improve the TFET performance, a CMOS process compatible TFET with epitaxial tunnel layer (ETL) structure is proposed. Various device parameters of complementary ETL TFETs (CTFETs) are studied and discussed in detail by the TCAD simulation. The inverter characteristics based on the proposed CTFETs are also presented and compared with the inverter based on complementary fully depleted silicon-on-insulator MOSFET (CMOSFETs). Moreover, complementary Ge ETL TFETs are also fabricated and discussed.
The effects of source junction profiles and the TAT on the bulk TFET are firstly investigated. By comparing with different source junction profiles, it indicates that the doping concentrations and profiles near the gate dielectric interface have the largest influence on TFET characteristics. The tunneling efficiency and orientation are also affected by the source junction profiles. Because the defects located within the depletion region have the largest effect on the device characteristics, the defects located near the gate interface and the junction edge degrade the TFET characteristics the most.
After realizing the basic characteristics and design issues of TFET devices, a CMOS process compatible TFET with ETL structure is proposed to improve the TFET performance. Considering the process integration and material properties, Ge/Si hetero-material system is used to demonstrate the concept of the ETL TFET. Excellent device performance of Ge ETL pTFET is achieved by the structural engineering and the ETL band engineering.
To achieve the configuration of complementary TFETs, Ge ETL nTFET is investigated. Because the Ge/Si hetero-material system with the valence band offset is applied, the concept of the suppression of the low electric field BTBT (LE BTBT) can apply on the Ge ETL nTFET. The LE BTBT suppression concept is illustrated and discussed by the TCAD simulation. The S.S. characteristic of Ge ETL nTFET can be further improved.
The TFET-based inverter are also studied and compared with the MOSFET-based inverter. Better speed performance can be achieved as the VDD is below 0.4 V. However, high power consumption on the TFET-based inverter is observed due to the large parasitic capacitance of CTFETs. According to the power-delay analysis, TFET-based inverter exhibits not only better performance but also less power consumption as it is operated at 0.2 V.
Finally, complementary Ge ETL TFETs are fabricated and discussed. The fabricated Ge ETL pTFET exhibits high tunneling current, ultralow OFF-state current, and good average subthreshold swing (S.S. ~100 mV/decade up to 10 nA / μm). The gate-to-source (CGS) capacitance is also investigated. The origin and the possible influence of the CGS are also discussed.
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Kumar, S., and K. K. Majhi. "Atlas simulation based study of SOI tunnel fet." Thesis, 2014. http://ethesis.nitrkl.ac.in/5615/1/e-63.pdf.
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It is observed that there are basically two limitations with the conventional mosfet, especially sub-threshold swing swings. Its minimum value being 60 mv/decade. But we cannot decrease it lesser. In order to decrease sub-threshold further, we use tunnel fet to reduce swing to some-what less value than conventional mosfet. It works on tunnelling effect.
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Teng, Chien-Hong, and 鄧建鴻. "TCAD Design of InAs Gate-All-Around Nanowire Tunnel FET Structures." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/g73uyt.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing.
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Medhi, S. "Atlas based simulation study of junctionless double gate (DG) tunnel FET." Thesis, 2014. http://ethesis.nitrkl.ac.in/5613/1/E-62.pdf.
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Tunnel Field Effect Transistor has recently attracted the attention of many researchers through its high Ion/Ioff ratio and a very less subthreshold slope. In this work Junction-less double gate tunnel field effect transistor’s performance has been studied which has been designed using charge plasma concept which can form the source and drain regions without the need for any doping by choosing appropriate work functions for the source and drain metal electrodes. A very important parameter of this device has been studied, i.e. the threshold voltage of this device. It has been seen that the variation of the threshold voltage with respect to the varying channel length of the device in almost nil. Also using it has been found that this device has a subthreshold slope of 56.7mV/decade with channel length of 50nm which is much lesser compared to the 60mV/decade subthreshold slope of a MOSFET, proving that this device can be used for switching performance in the future. Though the performance of the junction-less double gate TFET does not vary much compared to doped double gate Tunnel Field Effect Transistor, it is expected to be removed from all problems associated with random dopant fluctuations. Also its fabricating is possible on single crystal silicon-on-glass substrates which is formed by wafer scale epitaxial transfer.
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Lin, Yu-cheng, and 林鈺城. "Investigation of Drain Lapping Effect on Tunnel-FET With Poly-Si Channel Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/60553590438101130651.
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碩士<br>國立中山大學<br>電機工程學系研究所<br>104<br>The purpose of the research was to study the drain lapping effect of tunneling field-effect transistors (TFETs) with polycrystalline-silicon (poly-Si) channel.
The transfer characteristics of source to gate overlap 2m and different drain to gate lapping length indicated that overlap is not sensitive to overlap length and measurement temperature. For this reason, the TFETs with poly-Si channel device have strong immunity against the short channel effect.
When the tunneling field-effect transistors reverse turn on, the carrier transport behavior starts with tunneling of channel/drain junction. However, the underlap region of drain to gate builds the intrinsic depletion region between the channel and drain. The underlap structure can reduce the ambipolar current of tunneling field-effect transistors. There are many traps at the poly-Si intrinsic depletion region which make the carrier mobility degradation. By the higher measurement temperature, the transfer characteristics indicated that there is another reason to lead the current decrease obviously. The recombination current is significant effect of this case.
The TFETs with poly-Si channel with lapping structure have potential to study, in order to find the best carrier transport behavior.
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Chang, Kang, and 張綱. "Impacts of Ammonia Plasma Treatment on Tunnel-FET With Poly-Si Channel Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/13814733054789780118.
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碩士<br>國立中山大學<br>電機工程學系研究所<br>104<br>To obtain the faster operation speed and lower cost in fabrication，Channel length is continuously scaling down. However, negligible short channel effect(SCE) are observed and lead to increased of leakage current and reduce gate control ability. Tunnel Field-effect transistor is proposed to replace MOSFET in future. Unlike traditional inversion mode transistors, band-to-band tunneling is the mainly carrier transport mechanism. The subthreshold swing(S.S.) of T-FET can overcome the limitation of 60mV/dec of MOSFET.T-FET can also suppressed the leakage current by the high energy barrier and perform a better SCE immunity. T-FET is considered a promising candidate for next generation low power applications.
This thesis is mainly study for T-FET with Polycrystalline-Si channel, the channel film and the surface oxide interface of channel are rich with defects, lots of dangling bonds and strain bonds are localize in the defect. Both of them would degrade S.S. and increase leakage current. In this thesis,NH3 plasma is used to passivate the trap state. Both grain boundary trap state and interface trap can be effectively reduce by NH3 surface plasma treatment. Significant performance improvement has been observed after NH3 plasma surface treatment. Moreover, T-FET which passivated by NH3 plasma show lower
degradation after positive bias stress for 1000 sec, it indicate that TFET can perform higher reliability by NH3 plasma surface treatment. As a result, Poly-Si T-FET with NH3 plasma surface treatment can obtain better propertied and suitable to be used in LCD, three Dimensional-integrated Circuit or other consumer electronic.
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Hsu, Chie-Wei, and 徐誌緯. "Simulation and Investigation of Random Variations for III-V Broken-Gap Heterojunction Tunnel FET." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/75704934585062201395.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>103<br>This thesis compares and investigates the impacts of metal-gate work-function variation (WFV) and source random-dopant-fluctuation (source RDF) for III-V broken-gap heterojunction TFET (HTFET), homojunction TFET and FinFET devices using 3-D atomistic Monte Carlo simulation. Our study indicates that the HTFET exhibts higher susceptibility to WFV near OFF state due to its broken-gap nature. For ON current variation, both the HTFET and homojunction TFET show better immunity to WFV than the III-V FinFET. Device design using source-side underlap to mitigate the impact of WFV on HTFET is also assessed. Under source RDF, the HTFET exhibits larger current variations than the homojunction TFET and FinFET. The impact of source RDF increases with decreasing source doping for HTFET near OFF state.
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Gupta, Akancha, and 古璦卡. "Design of Low Voltage Vertical Channel-Tunnel FET (VC-TFET) Using Ge/SiGe Materials." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/k3s7eq.
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碩士<br>國立交通大學<br>電機資訊國際學程<br>107<br>Abstract
In this thesis, tunneling field-effect-transistor (TFET) based on the mechanism of band-to-band tunneling (BTBT), has been studied extensively. TFET is considered as a potential low voltage and low power transistors in certain applications for next generation transistors. Since the operating mechanism of TFET and MOSFET are different, hence, TFET is able to avoid many of the reliability and short channel issues. TFFT has the capability of achieving the sub-threshold slope of less than 60 mV/decade and small leakage current. These characteristics allow the voltage scaling and also reduce the power consumption for low power application. TFET still has some issues such as low on-state drive current value and larger gate-to-drain capacitance.
To further improve the TFET performance, a novel TFET device with vertical source-channel overlap region is proposed. Ge and SiGe materials are used for the structural modelling of VC-TFET. Various design parameters of vertical channel Tunnel FET (VC-TFET) are discussed and studied in detail by using the TCAD simulation. By modulating the important device parameters to optimize the device, the electrical characteristics with improved ON-state drive current, reduced OFF-state leakage current and steeper sub-threshold swing have been achieved.
After introducing the fundamental characteristics and device design concept of TFET device, the capacitance characteristics and inverter characteristics of the VC-TFET are also discussed in this work. Another critical issue is large gate-to-drain capacitance, Cgd in TFET, which can degrade the circuit delay. The proposed vertical channel TFET device design can reduce the Cgd value which result in lower circuit delay. Novel SRAM circuit topologies based on the proposed VC-TFET device are also proposed and discussed extensively. Better static noise margin can be achieved for lower VDD value. The proposed SRAM topologies based on VC-TFET device design give better noise-margin as compared to the conventional CMOS SRAM. These results show that the proposed VC-TFET is a potential device design for low voltage and low power applications.
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Lee, Ko-Chun, and 李克駿. "Investigation and Comparison of Important Analog Figures of Merit for Tunnel FET and FinFET Considering Random Variations." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/01098490544975302839.
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碩士<br>國立交通大學<br>電子工程學系 電子研究所<br>102<br>This thesis investigates and compares the impacts of metal-gate work function variation (WFV) and fin line edge roughness (fin LER) on the important analog FOMs (figures of merit) for TFET and FinFET devices using atomistic TCAD simulations. Our study indicates that under similar devices structure and comparable IOFF, the variability comparison between TFET and FinFET may yield different results depending on the dominant variation source for a given analog FOM. Under WFV, TFET exhibits better immunity to WFV than FinFET regarding gm/ID, Rout and intrinsic gain. For fT, however, the comparison result depends on drain bias. Under fin LER, TFET exhibits comparable immunity with FinFET in terms of gm/ID, Rout and intrinsic gain. However, TFET shows worse gm and fT immunity to fin LER than FinFET.
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Chen, Yin-Nien, and 陳盈年. "Design and Analysis of Nanoscale FinFET and Tunnel FET Devices for Ultra-Low-Power SRAM, Logic and Analog Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/03420513770720030664.
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博士<br>國立交通大學<br>電子工程學系 電子研究所<br>104<br>The goal of this dissertation is to provide an extensive assessment of nanoscale FinFET and TFET devices for ultra-low-power application in SRAM, logic and analog. Device-circuit interactions and co-optimizations are considered to demonstrate the advantages and concerns of these emerging devices based circuits from both the device and circuit point of view. Through our analysis, impacts of device characteristics and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAMs, on the power/performance of analog circuits are evaluated to offer insights for both our proposed innovative circuit designs and for future low-voltage circuit designs.
With superior electrostatic integrity and immune to random dopant fluctuation, FinFET device serves a promising role to replace conventional bulk MOSFET device. In addition, the possible adoption of the independent-gate control facilitates FinFET device characteristics and circuit functions. We extensively examine the stability and performance of our proposed Independently-controlled-Gate (IG) 7T FinFET SRAM cell with the conventional 6T FinFET SRAM cell and IG 6T Column-Decoupled FinFET SRAM cell. Through our analysis, our proposed IG 7T FinFET SRAM cell which exploits the independently-controlled-gate (IG) FinFET devices for reading transistor to decouple read/write paths and for access transistors to form cross-point structure provides comparable Write SNM (WSNM) and significant improvement in Read SNM (RSNM) and Half-Select SNM (HSSNM). In addition, with the 3D atomistic TCAD simulator generated Fin Line-Edge-Roughness (Fin LER) pattern, the impacts of the intrinsic device variability on the cell Read stability and Read Performance are extensively investigated. The results indicate that although the variability of independently-controlled-gate device is slightly larger compared to tied-gate device, our proposed cell provides the best μ/σ in RSNM and no Read failure events happened while other two counterparts encounter severe Read failure events due to leakage current from unselected cells flipping the storage data, revealing that our proposed cell is suitable for robust low Vmin SRAM application.
Utilizing band-to-band tunneling as the major transport mechanism, Tunnel FET (TFET) device with capability to surmount the thermionic limitation and to provide superior switching characteristics is regarded as the potential candidate for ultra-low voltage digital applications. Through our comprehensive analysis of the TFET device characteristics, it is found that the pronounced Miller capacitance (CGD) in TFET device undermines the steep-slope advantages and degrades both the switching delay and switching energy. The impacts of several device designs including the Dual Oxide (DOX), Drain-Side Underlap (Dund) and Dual Metal Work Function (DWF) on mitigating the Miller capacitance while maintain the switching characteristics of TFET device are comprehensively investigated and compared. Our results indicate that TFET device with DOX design provides superior reduction in Cinv and C¬gd while retaining comparable Ion-Ioff characteristics among the three design techniques. On the other hand, to enable MOSFET devices for high-speed low-power operation with extensively reduced supply voltage, advanced assist-circuit such as using the dual-supply dual-VT technique is indispensable at the cost of more complicated assist-circuits and needs of on-chip level shifter to generate dual supplies. We use TCAD mixed-mode simulations to comprehensively investigate the feasibility of sub-0.2V high-speed low-power circuits with the four topologies, nominal MOSFET-based circuits, MOSFET-based circuit with dual supply, dual-VT assisted circuits, nominal TFET-based circuits and TFET-based circuits with DOX design. The delay, dynamic energy, and Standby power of the logic circuits including NAND, Inverter, BUS Driver and Latch are comprehensively analyzed and compared. The results indicate that DOX TFET would be the best candidate in considering both the energy-delay product (EDP) and leakage power for NAND, Inverter and Latch circuits. While for Bus Driver in which the largest delay would take place among all logic blocks investigated, both the nominal and DOX TFET-based circuits outperform the nominal MOSFET-based circuits in EDP by about two orders of magnitude and consume comparable Standby power, revealing the potential of TFET device to achieve high-speed low-power circuit operation at VDD = 0.2V.
In addition to logic circuits, various TFET SRAM cells including conventional 7T/8T SRAM cell, 6T SRAM cell with assisted footer and our proposed cells to circumvent the difficulties implementing TFET with conventional 6T SRAM topology are statistically examined and compared. The results indicate that our proposed 7T Drive-Less (DL) TFET SRAM cell with the utilization of 4T DL SRAM as the basis along with the independent gate control can effectively improve the stability of the bit cell in Hold, Read and Write mode with adequate bit cell area compared with other counterparts. On the other hand, with the process compatibility in TFET and CMOS device fabrication, we propose a mixed TFET-MOSFET 8T SRAM cell to exploit merits of both TFET and MOSFET devices. The detailed analysis on stability, performance and effectiveness of using different write-assist schemes are extensively demonstrated. Through our comprehensive study, our proposed mixed TFET-MOSFET 8T SRAM cell provides significant improvement in stability, performance and Vmin, exhibiting the chance to stand for robust ultra-low power SRAM design at the cost of slightly larger bit cell area.
The advantages of the TFET devices for analog applications are assessed to examine the potential for SoC applications. The detailed analog properties and the figure-of-merit (FOM) of TFET and FinFET devices including the transconductance (gm), output resistance (Ro), intrinsic gain (gm x Ro), intrinsic capacitance and linearity are comprehensively studied from intrinsic device physics point of view. Our analysis indicates that for cost-performance ultra-low voltage/power applications, TFET provides substantial merits in intrinsic gain compared with the FinFET device while for high-performance applications, FinFET device outperforms the TFET device at moderate and high voltages. Besides, the operational transconductance amplifier is taken as the fundamental block to investigate the opportunities and concerns of the TFET device for analog/mixed-signal circuit applications. The results indicate that for cost-performance ultra-low power application, TFET OTA provides more than two times higher unity-gain frequency (fT), and 10dB larger common-mode rejection ratio (CMRR) than FinFET OTA at comparable power consumption design.
As the continual scaling of device dimension along with the reduced supply voltages, the impacts of intrinsic device variations become the critical concerns affecting device characteristics and circuit designs. The in-depth assessment of the impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET and FinFET device characteristics are carried out through atomistic 3D TCAD simulations. Look-up table based Verilog-A model calibrated with TCAD results is built for each variation source and incorporates with HSPICE simulations to efficiently investigate impacts of Work-Function Variation and Fin Line-Edge Roughness on TFET SRAMs including our proposed mixed TFET-MOSFET 8T SRAM cell, conventional FinFET 8T SRAM cell and TFET 8T SRAM cell. For the first time, the feasibility/issues of each SRAM cell for ultra-low voltage operation considering intrinsic device variability are addressed. Our results indicate that our proposed mixed cell with exploiting merits of both devices provides superior stability and insusceptibility to intrinsic device variations, revealing its viability and robustness to operate at ultra-low voltages.
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Su, Yen-So, and 蘇彥守. "Design and Simulation of Improved Swing and Ambipolar Effect for Tunnel FET by Band Engineering Using Metal at Drain Side." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bfs697.
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Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. https://etd.iisc.ac.in/handle/2005/792.
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The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries.
Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.
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Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. http://hdl.handle.net/2005/792.
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The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries.
Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.
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Fan, Ming-Long, and 范銘隆. "Design and Analysis of Nanoscale FinFET, Tunnel FET and Hetero-Channel 3D Integrated Ultra-Thin-Body Devices for Ultra-Low-Power SRAM and Logic Circuits." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/25878819945473509609.
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博士<br>國立交通大學<br>電子工程學系 電子研究所<br>103<br>This dissertation provides an extensive assessment of nanoscale FinFET, Tunnel FET (TFET) and hetero-channel 3D integrated Ultra-Thin-Body (UTB) MOSFET for ultra-low-power applications. Device-circuit interactions and co-optimizations are considered to demonstrate the potential and concerns of these emerging devices from the device/circuit point of view. Through our analysis, the impacts of device variability and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAM cells are evaluated to offer insights for future low-voltage circuit designs.
With the superior electrostatic integrity and variability immunity of FinFET devices, the Static Noise Margin (SNM) of subthreshold FinFET SRAM cells is investigated using an analytical SNM model. Examination of the stabilities of several novel 6T FinFET cells using independent-gate technique indicates significant improvements in nominal READ SNM (RSNM) in these cells. However, the WRITE ability is found to be degraded and limits the cell robustness for certain cells in the subthreshold region. The READ/WRITE word-line voltage control technique is found to be more effective than transistor sizing in enhancing the stability of subthreshold FinFET SRAM cell. In addition, a model-assisted approach is developed to account for multiple variation sources simultaneously and efficiently when investigating the impact of device variability on the cell stability. Compared with Work-Function Variation (WFV), our results indicate that fin Line-Edge-Roughness (fin LER) dominates the overall subthreshold drain current fluctuation. With the established model approach, two recently introduced 4T and conventional 6T FinFET SRAM cells are statistically examined. Because of the reduced READ disturb, the 4T cells exhibit better nominal RSNM and the nearly ideal VWRITE,0 and VWRITE,1 of 4T cells promise the positive nominal WRITE SNM (WSNM) for selected cells. Under identical cell area, 4T SRAM cells with fewer transistors have the flexibility to increase device size (reduced σRSNM) and outperform the 6T counterpart. On the other hand, because of its vertical topology and difference in the degree of quantum confinement, the conventional sidewall conducting (110) surface orientation of FinFET can be rotated by layout to improve cell variability. It is found that NFET with (110) orientation shows larger fin LER induced threshold-voltage variation than the (100) one, while PFET exhibits the opposite trend. Therefore, with optimal orientations, significant μ/σ ratio improvement in RSNM can be achieved by using SRAM cell with (PU,PD,PG) = (110,100,100), revealing the potential of 6T FinFET cells with appropriate optimization for emerging subthreshold FinFET SRAM applications.
In addition to cell, the viability and merits of small-signal differential sensing and large-signal single-ended sensing schemes for FinFET SRAM are investigated under the influence of variability. The local random variation of selected cell, leakage (and its variation) from unselected cells on the selected bit-line, and variation of sense amplifier offset voltage (VOS) and trip voltage (VTRIP) are considered simultaneously. For differential sensing scheme, the subthreshold sensing margin is severely degraded by the variation in bit-line voltage and sufficient time before enabling the sense amplifier is required. For large-signal sensing scheme, we show that there is large disparity between the sense “0” margin and sense “1” margin with significantly worse sense “0” margin limiting the affordable number of cells per bit-line and performance. Using our statistical model-based approach, it is observed that the VOS of Current-Latch Sense Amplifier (CLSA) calculated solely from threshold-voltage mismatch underestimates the actual variation and is shown to be optimistic. Compared with the conventional BULK MOSFET, FinFET enhances the feasibility of differential sensing in subthreshold SRAM applications.
Under low-VDD design, the importance of Random Telegraph Noise (RTN) increases and threats the functionality of circuits. We analyze the impact of single-trap-induced RTN on FinFET devices, 6T SRAM cell, and several logic circuits. Our result indicates that the charged interface trap located near the bottom and middle region between source/drain results in most significant impact. Besides, Equivalent Oxide Thickness (EOT) scaling and higher operating temperature are found to improve the immunity to RTN. The larger variability and surface conduction of planar BULK MOSFET lead to broader dispersion and larger worst-case RTN degradation than the FinFET with smaller variability and volume conduction. In the presence of RTN, ~ 24% - 27% and ~ 13% - 15% additional variations in the leakage and delay, respectively, are observed at VDD = 0.4V for the FinFET inverter, Two-Way NAND and Two-To-One multiplexer.
Using band-to-band tunneling as major conduction mechanism, Tunnel FET (TFET) with capability to surmount the thermionic limitation and provide superior switching characteristics is regarded as promising candidate for ultra-low-voltage operation. We extensively investigate the impacts of single acceptor-type or donor-type interface trap induced RTN on TFET device, SRAM circuits and its interaction with WFV. In our analysis, significant RTN amplitude is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. Moreover, several device parameters which can improve the TFET subthreshold characteristics (e.g. thinner EOT, fin width or longer channel length) are found to increase the susceptibility to RTN. Under WFV, TFET exhibits weaker correlation between ION and IOFF than that in the FinFET. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of trap and composition/orientation of metal-gate grain. In addition, our analysis indicates that ~ 16% extra variation (at VDD = 0.3V) in the stability of standard 8T SRAM cell and ~80mV additional VOS variation (at VDD = 0.5V) for the CLSA circuit are observed.
The advantages of hetero-channel logic circuits and 6T/8T SRAM cells for low-power applications are comprehensively evaluated with monolithic 3D integration. With adequate 3D layout design, minimum leakage, equivalent to the planar 2D circuits with dual backgate biases (VBS), is achievable. Furthermore, with interlayer coupling, substantial performance improvements over the 2D counterparts are found for monolithic 3D inverters, Two-Way NAND, multiplexer, static latch and D Flip-Flop, especially for GeOI logic circuits operating in low VDD. Besides, various bit-cell layouts with different gate alignments of transistors from distinct layers are investigated for the evaluation of cell stability/performance of two-tier 6T/8T SRAM cells. Our studies indicate that stacking the NFET tier over the PFET layer results in larger design margins for cell robustness and performance. The larger improvements over the 2D counterparts make hetero-channel 3D integrated MOSFET a suitable candidate for monolithic 3D applications.
For III-V UTB Heterojunction TFET (HTFET), the impact of VBS on the drain current and implications/designs for monolithic 3D SRAM cells are assessed. Compared with homojunction TFET and conventional MOSFET, our results indicate that HTFET exhibits significantly higher IOFF modulation efficiency and the influence of VBS rapidly decreases with increasing gate voltage. In addition, it is observed that the change of source available states with VBS determines the ID modulation efficiency of p-type HTFET. Depending on the source doping and operating VG, the ID of HTFET under forward VBS can be anomalously smaller than that at VBS = 0V. With the difference in the efficiency of interlayer coupling, the standard all-TFET and our proposed hybrid 8T SRAM cells are optimized with layouts and compared in 2D/3D integrations.
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Hanna, Amir. "Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors." Diss., 2016. http://hdl.handle.net/10754/621933.
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This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more
than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V.
This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in
field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation delay times when compared to their planar counterparts. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts. Finally, a WC based pass transistor logic multiplexer circuit is demonstrated, which has shown more than 5× faster high-to-low propagation delay compared to its planar counterpart at a similar peak-to-peak output voltage.
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(7025126), Ahmedullah Aziz. "Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics." Thesis, 2019.
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<p>Phase
transition materials (PTM) have garnered immense interest in concurrent
post-CMOS electronics, due to their unique properties such as - electrically
driven abrupt resistance switching, hysteresis, and high selectivity. The phase
transitions can be attributed to diverse material-specific phenomena, including-
correlated electrons, filamentary ion diffusion, and dimerization. In this
research, we explore the application space for these materials through
extensive device-circuit co-design and propose new ideas harnessing their unique
electrical properties. The abrupt transitions and high selectivity of PTMs
enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a
promising post-CMOS transistor. We explore device-circuit co-design methodology
for Hyper-FET and identify the criterion for material down-selection. We evaluate
the achievable voltage swing, energy-delay trade-off, and noise response for
this novel device. In addition to the application in low power logic device,
PTMs can actively facilitate non-volatile memory design. We propose a PTM
augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase
transitions to boost the sense margin and stability of stored data,
simultaneously. We show that such selective transitions can also be used to
improve other MRAM designs with separate read/write paths, avoiding the possibility
of read-write conflicts. Further, we analyze the application of PTMs as
selectors in cross-point memories. We establish a general simulation framework for
cross-point memory array with PTM based <i>selector</i>.
We explore the biasing constraints, develop detailed design methodology, and
deduce figures of merit for PTM selectors. We also develop a computationally
efficient compact model to estimate the leakage through the sneak paths in a
cross-point array. Subsequently, we present a new sense amplifier design utilizing
PTM, which offers built-in tunable reference with low power and area demand.
Finally, we show that the hysteretic characteristics of unipolar PTMs can be
utilized to achieve highly efficient rectification. We validate the idea by demonstrating
significant design improvements in a <i>Cockcroft-Walton
Multiplier, </i>implemented with TS
based rectifiers. We emphasize the need to explore other PTMs with high
endurance, thermal stability, and faster switching to enable many more
innovative applications in the future.</p></div></div>