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Artykuły w czasopismach na temat „Tunnel FETs”

Autor: Grafiati

Data publikacji: 6 września 2023

Data aktualizacji: 31 lipca 2025

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1

Lind, Erik, Elvedin Memisevic, Anil W. Dey, and Lars-Erik Wernersson. "III-V Heterostructure Nanowire Tunnel FETs." IEEE Journal of the Electron Devices Society 3, no. 3 (2015): 96–102. http://dx.doi.org/10.1109/jeds.2015.2388811.

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2

Pandey, Rahul, Saurabh Mookerjea, and Suman Datta. "Opportunities and Challenges of Tunnel FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 12 (2016): 2128–38. http://dx.doi.org/10.1109/tcsi.2016.2614698.

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3

Sedighi, Behnam, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, and Michael Niemier. "Analog Circuit Design Using Tunnel-FETs." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 1 (2015): 39–48. http://dx.doi.org/10.1109/tcsi.2014.2342371.

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4

Moselund, K. E., H. Schmid, C. Bessire, M. T. Bjork, H. Ghoneim, and H. Riel. "InAs–Si Nanowire Heterojunction Tunnel FETs." IEEE Electron Device Letters 33, no. 10 (2012): 1453–55. http://dx.doi.org/10.1109/led.2012.2206789.

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5

Ortiz-Conde, Adelmo, Francisco J. García-Sánchez, Juan Muci, et al. "Threshold voltage extraction in Tunnel FETs." Solid-State Electronics 93 (March 2014): 49–55. http://dx.doi.org/10.1016/j.sse.2013.12.010.

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6

Wu, Jianzhi, Jie Min, and Yuan Taur. "Short-Channel Effects in Tunnel FETs." IEEE Transactions on Electron Devices 62, no. 9 (2015): 3019–24. http://dx.doi.org/10.1109/ted.2015.2458977.

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7

Verhulst, Anne S., William G. Vandenberghe, Karen Maex, Stefan De Gendt, Marc M. Heyns, and Guido Groeseneken. "Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates." IEEE Electron Device Letters 29, no. 12 (2008): 1398–401. http://dx.doi.org/10.1109/led.2008.2007599.

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8

Huang, Jun Z., Pengyu Long, Michael Povolotskyi, Gerhard Klimeck, and Mark J. W. Rodwell. "P-Type Tunnel FETs With Triple Heterojunctions." IEEE Journal of the Electron Devices Society 4, no. 6 (2016): 410–15. http://dx.doi.org/10.1109/jeds.2016.2614915.

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9

Avedillo, M. J., and J. Núñez. "Improving speed of tunnel FETs logic circuits." Electronics Letters 51, no. 21 (2015): 1702–4. http://dx.doi.org/10.1049/el.2015.2416.

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10

Pandey, Rahul, Bijesh Rajamohanan, Huichu Liu, Vijaykrishnan Narayanan, and Suman Datta. "Electrical Noise in Heterojunction Interband Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 2 (2014): 552–60. http://dx.doi.org/10.1109/ted.2013.2293497.

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11

Dayeh, Shadi A., and S. Tom Picraux. "Axial Ge/Si Nanowire Heterostructure Tunnel FETs." ECS Transactions 33, no. 6 (2019): 373–78. http://dx.doi.org/10.1149/1.3487568.

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12

Richter, S., S. Blaeser, L. Knoll, et al. "Silicon–germanium nanowire tunnel-FETs with homo- and heterostructure tunnel junctions." Solid-State Electronics 98 (August 2014): 75–80. http://dx.doi.org/10.1016/j.sse.2014.04.014.

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13

Gudlavalleti, R. H., B. Saman, R. Mays, et al. "Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations." International Journal of High Speed Electronics and Systems 28, no. 03n04 (2019): 1940026. http://dx.doi.org/10.1142/s0129156419400263.

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Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is depos

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14

KARMAKAR, SUPRIYA, JOHN A. CHANDY, and FAQUIR C. JAIN. "APPLICATION OF 25 NM QUANTUM DOT GATE FETs TO THE DESIGN OF ADC AND DAC CIRCUITS." International Journal of High Speed Electronics and Systems 20, no. 03 (2011): 653–68. http://dx.doi.org/10.1142/s0129156411006945.

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This paper describes design of analog-to-digital converters (ADCs) and digital-to-analog onverters (DACs) using field-effect transistors that exhibit three states in their transfer characteristics. An intermediate state " i " has been observed in the transfer characteristics (drain current-gate voltage) of FETs when two layers of cladded quantum dots (e.g. SiO x - Si and GeO x - Ge ) are introduced in the gate region above the tunnel insulator between the source and drain regions. Three states in such a transistor, defined as quantum dot gate field-effect transistor (QDG-FET) include two stabl

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15

Aghanejad Ahmadchally, Alireza, and Morteza Gholipour. "Investigation of 6-armchair graphene nanoribbon tunnel FETs." Journal of Computational Electronics 20, no. 3 (2021): 1114–24. http://dx.doi.org/10.1007/s10825-021-01709-4.

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16

Zhang, Qin, Yeqing Lu, Curt A. Richter, Debdeep Jena, and Alan Seabaugh. "Optimum Bandgap and Supply Voltage in Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 8 (2014): 2719–24. http://dx.doi.org/10.1109/ted.2014.2330805.

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17

Ilatikhameneh, Hesameddin, Gerhard Klimeck, and Rajib Rahman. "Can Homojunction Tunnel FETs Scale Below 10 nm?" IEEE Electron Device Letters 37, no. 1 (2016): 115–18. http://dx.doi.org/10.1109/led.2015.2501820.

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18

Chen, Hongwei, Li Yuan, Qi Zhou, Chunhua Zhou, and Kevin J. Chen. "Normally-off AlGaN/GaN power tunnel-junction FETs." physica status solidi (c) 9, no. 3-4 (2012): 871–74. http://dx.doi.org/10.1002/pssc.201100338.

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19

Pala, Marco G., and David Esseni. "Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs—Part I: Model Description and Single Trap Analysis in Tunnel-FETs." IEEE Transactions on Electron Devices 60, no. 9 (2013): 2795–801. http://dx.doi.org/10.1109/ted.2013.2274196.

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20

Taniyama, Keita, Yuki Takeda, Yuki Azuma, Ziye Zheng, Junichi Motohisa, and Katsuhiro Tomioka. "Selective-Area Growth of InGaAs Nanowires on SOI and the Vertical Transistor Application." ECS Transactions 114, no. 2 (2024): 165–70. http://dx.doi.org/10.1149/11402.0165ecst.

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The gate-all-around (GAA) structure avoids the problems inherent in miniaturizing field-effect transistors (FETs), such as off-state leakage current and short-channel effects. Among GAA structures, vertical GAA (VGAA) structures are expected as promising building blocks for future three-dimensional integrated circuit applications. The vertical III-V nanowires (NWs) on Si are expected as the fast channel materials for the VGAA structures on Si platforms. Thus, the combination of the VGAA structure with III-V NWs on Si significantly enhances on-state current while maintaining good gate controlla

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21

Chen, Yi-Ju, and Bing-Yue Tsui. "Bandgap engineering of Si1− x Ge x epitaxial tunnel layer for tunnel FETs." Japanese Journal of Applied Physics 57, no. 8 (2018): 084201. http://dx.doi.org/10.7567/jjap.57.084201.

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22

Zhao, Q. T., S. Richter, L. Knoll, et al. "(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics." ECS Transactions 66, no. 4 (2015): 69–78. http://dx.doi.org/10.1149/06604.0069ecst.

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23

Mallik, A. "Tunnel FETs for Mixed-Signal System-On-Chip Applications." ECS Transactions 53, no. 5 (2013): 93–104. http://dx.doi.org/10.1149/05305.0093ecst.

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24

Conzatti, F., M. G. Pala, and D. Esseni. "Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs." IEEE Electron Device Letters 33, no. 6 (2012): 806–8. http://dx.doi.org/10.1109/led.2012.2192091.

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25

Jiang, Zhi, Yiqi Zhuang, Cong Li, Ping Wang, and Yuqi Liu. "Vertical-dual-source tunnel FETs with steeper subthreshold swing." Journal of Semiconductors 37, no. 9 (2016): 094003. http://dx.doi.org/10.1088/1674-4926/37/9/094003.

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26

Fiore, Antonio, Jacopo Franco, Moonju Cho, et al. "Single Defect Discharge Events in Vertical-Nanowire Tunnel-FETs." IEEE Transactions on Device and Materials Reliability 17, no. 1 (2017): 253–58. http://dx.doi.org/10.1109/tdmr.2017.2655623.

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27

Conzatti, F., M. G. Pala, D. Esseni, E. Bano, and L. Selmi. "Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs." IEEE Transactions on Electron Devices 59, no. 8 (2012): 2085–92. http://dx.doi.org/10.1109/ted.2012.2200253.

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28

Zhang, Lining, Xinnan Lin, Jin He, and Mansun Chan. "An Analytical Charge Model for Double-Gate Tunnel FETs." IEEE Transactions on Electron Devices 59, no. 12 (2012): 3217–23. http://dx.doi.org/10.1109/ted.2012.2217145.

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29

Gupta, Sumeet Kumar, Jaydeep P. Kulkarni, Suman Datta, and Kaushik Roy. "Heterojunction Intra-Band Tunnel FETs for Low-Voltage SRAMs." IEEE Transactions on Electron Devices 59, no. 12 (2012): 3533–42. http://dx.doi.org/10.1109/ted.2012.2221127.

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30

Boucart, Kathy, and Adrian Mihai Ionescu. "A new definition of threshold voltage in Tunnel FETs." Solid-State Electronics 52, no. 9 (2008): 1318–23. http://dx.doi.org/10.1016/j.sse.2008.04.003.

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31

Najmzadeh, M., K. Boucart, W. Riess, and A. M. Ionescu. "Asymmetrically strained all-silicon multi-gate n-Tunnel FETs." Solid-State Electronics 54, no. 9 (2010): 935–41. http://dx.doi.org/10.1016/j.sse.2010.04.037.

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32

Hutin, L., R. P. Oeflein, J. Borrel, et al. "Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs." Solid-State Electronics 115 (January 2016): 160–66. http://dx.doi.org/10.1016/j.sse.2015.08.007.

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33

Ding, Lili, Elena Gnani, Simone Gerardin, et al. "Total Ionizing Dose Effects in Si-Based Tunnel FETs." IEEE Transactions on Nuclear Science 61, no. 6 (2014): 2874–80. http://dx.doi.org/10.1109/tns.2014.2367548.

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34

Dong, Yunpeng, Lining Zhang, Xiangbin Li, Xinnan Lin, and Mansun Chan. "A Compact Model for Double-Gate Heterojunction Tunnel FETs." IEEE Transactions on Electron Devices 63, no. 11 (2016): 4506–13. http://dx.doi.org/10.1109/ted.2016.2604001.

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35

Huang, Jun Z., Pengyu Long, Michael Povolotskyi, Gerhard Klimeck, and Mark J. W. Rodwell. "Scalable GaSb/InAs Tunnel FETs With Nonuniform Body Thickness." IEEE Transactions on Electron Devices 64, no. 1 (2017): 96–101. http://dx.doi.org/10.1109/ted.2016.2624744.

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36

Mori, Yoshiaki, Shingo Sato, Yasuhisa Omura, Avik Chattopadhyay, and Abhijit Mallik. "On the definition of threshold voltage for tunnel FETs." Superlattices and Microstructures 107 (July 2017): 17–27. http://dx.doi.org/10.1016/j.spmi.2017.04.002.

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37

Panda, Subhrasmita, Sidhartha Dash, and Guru Prasad Mishra. "Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs." Journal of Computational Electronics 15, no. 4 (2016): 1326–33. http://dx.doi.org/10.1007/s10825-016-0907-1.

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38

Roy, T., Z. R. Hesabi, C. A. Joiner, A. Fujimoto, and E. M. Vogel. "Barrier engineering for double layer CVD graphene tunnel FETs." Microelectronic Engineering 109 (September 2013): 117–19. http://dx.doi.org/10.1016/j.mee.2013.02.090.

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39

Chen, Yi-Hsuan, William Cheng-Yu Ma, Jer-Yi Lin, et al. "Impact of Crystallization Method on Poly-Si Tunnel FETs." IEEE Electron Device Letters 36, no. 10 (2015): 1060–62. http://dx.doi.org/10.1109/led.2015.2468060.

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40

Dharmireddy, Ajay Kumar, Dr Sreenivasa Rao Ijjada, and Dr I. Hema Latha. "Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET." International Journal of Electrical and Electronics Research 10, no. 4 (2022): 806–10. http://dx.doi.org/10.37391/ijeer.100407.

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High speed and low power dissipation devices are expected from future generation technology of Nano-electronic devices. Tunnel field effect transistor (TFET) technology is unique to the prominent devices in low power applications. To minimize leakage currents, the tunnel switching technology of TFETs is superior to conventional MOS FETs. The gate coverage area of different fin shape hybrid tunnel field-effect transistors is more impacted on electric characteristics of drive current, leakage current and subthreshold slope. In this paper design various fin patterns of hybrid TFET devices and sho

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41

Xu, Hui Fang, Yue Hua Dai, Bang Gui Guan, and Yong Feng Zhang. "Two-dimensional analytical model for asymmetric dual-gate tunnel FETs." Japanese Journal of Applied Physics 56, no. 1 (2016): 014301. http://dx.doi.org/10.7567/jjap.56.014301.

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42

Tomioka, K., T. Fukui, and J. Motohisa. "(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions." ECS Transactions 69, no. 10 (2015): 109–18. http://dx.doi.org/10.1149/06910.0109ecst.

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43

Wang, Hao, Sheng Chang, Jin He, Qijun Huang, and Feng Liu. "The Dual Effects of Gate Dielectric Constant in Tunnel FETs." IEEE Journal of the Electron Devices Society 4, no. 6 (2016): 445–50. http://dx.doi.org/10.1109/jeds.2016.2610478.

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44

Tomioka, K., and T. Fukui. "(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions." ECS Transactions 61, no. 3 (2014): 81–89. http://dx.doi.org/10.1149/06103.0081ecst.

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45

Kim, Jang Hyun, Sang Wan Kim, Hyun Woo Kim, and Byung‐Gook Park. "Vertical type double gate tunnelling FETs with thin tunnel barrier." Electronics Letters 51, no. 9 (2015): 718–20. http://dx.doi.org/10.1049/el.2014.3864.

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46

Chen, Cheng, Qianqian Huang, Jiadi Zhu, Yang Zhao, Lingyi Guo, and Ru Huang. "New Understanding of Random Telegraph Noise Amplitude in Tunnel FETs." IEEE Transactions on Electron Devices 64, no. 8 (2017): 3324–30. http://dx.doi.org/10.1109/ted.2017.2712714.

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47

Ahmed, Sheikh Z., Daniel S. Truesdell, Yaohua Tan, Benton H. Calhoun, and Avik W. Ghosh. "A comprehensive analysis of Auger generation impacted planar Tunnel FETs." Solid-State Electronics 169 (July 2020): 107782. http://dx.doi.org/10.1016/j.sse.2020.107782.

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48

Zhang, Lining, and Mansun Chan. "SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports." IEEE Transactions on Electron Devices 61, no. 2 (2014): 300–307. http://dx.doi.org/10.1109/ted.2013.2295237.

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49

Gholizadeh, Mahdi, and Seyed Ebrahim Hosseini. "A 2-D Analytical Model for Double-Gate Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 5 (2014): 1494–500. http://dx.doi.org/10.1109/ted.2014.2313037.

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50

Ghosh, Krishnendu, and Uttam Singisetti. "RF Performance and Avalanche Breakdown Analysis of InN Tunnel FETs." IEEE Transactions on Electron Devices 61, no. 10 (2014): 3405–10. http://dx.doi.org/10.1109/ted.2014.2344914.

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