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Gotowe bibliografie tematyczne / Xilinx.Floating Point Subtractor

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Gotowa bibliografia na temat „Xilinx.Floating Point Subtractor”

Autor: Grafiati

Data publikacji: 3 czerwca 2025

Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "Xilinx.Floating Point Subtractor"

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Ms., Anuja A. Bhat* &. Prof. Mangesh N. Thakare. "DESIGN OF FLOATING POINT MULTIPLIER BASED ON BOOTH ALGORITHM USING VHDL." INTERNATIONAL JOURNAL OF RESEARCH SCIENCE & MANAGEMENT 4, no. 5 (2017): 55–62. https://doi.org/10.5281/zenodo.572573.

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In this paper, we have presented of High Speed, low power and less delay 32-bit IEEE 754 Floating Point Subtractor and Multiplier using Booth Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this research is to reduce delay, power and to increase the speed. The coding is done in VHDL, synthesis and simulation has been done using Xilinx ISE simulator.

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Ms., Anuja A. Bhat* &. Prof. Rutuja Warbhe. "DESIGN OF FLOATING POINT MULTIPLIER BASED ON BOOTH ALGORITHM USING VHDL." INTERNATIONAL JOURNAL OF RESEARCH SCIENCE & MANAGEMENT 4, no. 5 (2017): 123–30. https://doi.org/10.5281/zenodo.580862.

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In this paper, high Speed, low power and less delay 32-bit IEEE 754 Floating PointSubtractor andMultiplierispresented using Booth Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this researchis to reduce delay, power and to increase the speed.The coding is done in VHDL, synthesis and simulationhas been done using Xilinx ISE simulator. The modules des

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Xiao, Feibao, Feng Liang, Bin Wu, Junzhe Liang, Shuting Cheng, and Guohe Zhang. "Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and SquareRoot." Electronics 9, no. 10 (2020): 1622. http://dx.doi.org/10.3390/electronics9101622.

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As a substitute for the IEEE 754-2008 floating-point standard, Posit, a new kind of number system for floating-point numbers, was put forward recently. Hitherto, some studies have proven that Posit is a better floating-point style than IEEE 754-2008 in some fields. However, most of these studies presented the advantages of Posit from the arithmetical aspect, but none of them suggested it had a better hardware implementation than that of IEEE 754-2008. In this paper, we propose several hardware implementations that contain the Posit adder/subtractor, multiplier, divider, and square root. Our go

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Naginder, Singh, and Parihar Kapil. "Comparative study of single precision floating point division using different computational algorithms." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 3 (2023): 336–44. https://doi.org/10.11591/ijres.v12.i3pp336-344.

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This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed an

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Singh, Naginder, and Kapil Parihar. "Comparative study of single precision floating point division using different computational algorithms." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 3 (2023): 336. http://dx.doi.org/10.11591/ijres.v12.i3.pp336-344.

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<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computatio

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Teymourzadeh, Rozita. "On-chip Implementation of High Resolution High Speed Low Area Floating point Adder Subtractor for OFDM Applications." American Journal of Engineering and Applied Sciences ISSN: 1941-7020. 3, no. 1 (2010): 25–30. https://doi.org/10.5281/zenodo.1239895.

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Fast Fourier transform (FFT) is widely applied in OFDM trance-receiver communications system. Hence Efficient FFT algorithm is always considered. This paper proposed FPGA realization of high-resolution high-speed low latency floating point adder/subtractor for FFT in OFDM trance-receiver. The design was implemented for 32 bit pipelined adder/subtractor which satisfied IEEE-754 Standard for Floating-point Arithmetic. The design was focused on the trade-off between the latency and speed improvement as well as resolution and silicon area for the chip implementation. In order to reduce the critica

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Bhagya, Prof, Ramanagowda G. S, Rohan S, Soundarya D. R, and Yogitha K. "Implementation of Pipelined Multi_Precision (1, 2 and 4) Floating-point Arithmetic Operations." International Journal for Research in Applied Science and Engineering Technology 11, no. 4 (2023): 3141–43. http://dx.doi.org/10.22214/ijraset.2023.50739.

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Abstract: The implementation of pipelined multi-precision-based arithmetic operations are carried out. In the existing system, the floating-point operation is based on single precision and is implemented on a divider. The proposed design has been implemented using single, double and quad precision using the universal piece-wise linear (PWL) approximation method and a modified Goldschmidt algorithm. The proposed design performs addition, subtraction, multiplication, and division using the universal PWL method to reduce maximum error. Small multipliers are used in the modified Goldschmidt algori

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Baesler, Malte, and Sven-Ole Voigt. "Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs." International Journal of Reconfigurable Computing 2013 (2013): 1–16. http://dx.doi.org/10.1155/2013/453173.

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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the q

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ÖZKILBAÇ, Bahadır. "Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform." Brilliant Engineering 1, no. 1 (2019): 26–32. http://dx.doi.org/10.36937/ben.2020.001.005.

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FPGAs have capabilities such as low power consumption, multiple I/O pins, and parallel processing. Because of these capabilities, FPGAs are commonly used in numerous areas that require mathematical computing such as signal processing, artificial neural network design, image processing and filter applications. From the simplest to the most complex, all mathematical applications are based on multiplication, division, subtraction, addition. When calculating, it is often necessary to deal with numbers that are fractional, large or negative. In this study, the Arithmetic Logic Unit (ALU), which use

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Prahlada, P. Udupa, and B. Ramesh K. "VLSI Design and Verification of a Multi-Function Arithmetic Logic Unit." Journal of VLSI Design and its Advancement 7, no. 3 (2024): 37–47. https://doi.org/10.5281/zenodo.13709349.

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<em>Exploring an ALU Design in the VLSI Domain - Within modern processors like CPUs, FPUs, and GPUs, the Arithmetic Logic Unit (ALU) serves as a critical building block. In this review paper, we delve into the Very Large Scale Integration (VLSI) design of an ALU, exploring its functionality through meticulous simulation and testing. Leveraging the Xilinx ISE design suite 14.7, the study validates the proposed ALU's gate-level and chip-level implementation, ensuring its ability to execute nine essential operations: addition, subtraction, multiplication, shifting, comparison, AND, OR, NOT, and X

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Rozprawy doktorskie na temat "Xilinx.Floating Point Subtractor"

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Liu, Qiong. "Design of an IEEE double precision floating-point adder/subtractor in GaAs technology /." Title page, table of contents and abstract only, 1995. http://web4.library.adelaide.edu.au/theses/09ENS/09ensl793.pdf.

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Hussain, Sajid. "Verification and FPGA implementation of a floating point SIMD processor for MIMO processing." Thesis, Linköpings universitet, Datorteknik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-64077.

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The rapidly increasing capabilities of digital electronics have increased the demand of Software Defined Radio (SDR), which were not possible in the special purpose hardware. These enhanced capabilities come at the cost of time due to complex operations involved in multi-antenna wireless communications, one of those operations is complex matrix inversion. This thesis presents the verification and FPGA implementation of a SIMD processor, which was developed at Computer Engineering division of Linköping university, Sweden. This SIMD processor was designed specifically for performing complex matr

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Lee, Barry Roland. "Comparison of logarithmic and floating-point number systems implemented on Xilinx Virtex-II field-programmable gate arrays." Thesis, Cardiff University, 2004. http://orca.cf.ac.uk/55943/.

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The aim of this thesis is to compare the implementation of parameterisable LNS (logarithmic number system) and floating-point high dynamic range number systems on FPGA. The Virtex/Virtex-II range of FPGAs from Xilinx, which are the most popular FPGA technology, are used to implement the designs. The study focuses on using the low level primitives of the technology in an efficient way and so initially the design issues in implementing fixed-point operators are considered. The four basic operations of addition, multiplication, division and square root are considered. Carry- free adders, ripple-c

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Štrympl, Martin. "Výpočet vlastních čísel a vlastních vektorů hermitovské matice." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242085.

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This project deals with computation of eigenvalues and eigenvectors of Hermitian positive-semidefinite complex square matrix of order 4. The target is an implementation of computation in language VHDL to field-programmable gate array of type Xilinx Zynq-7000. This master project deals with algorithms used for computation of eigenvalues and eigenvectors of positive-semidefinite symmetric real square and positive-semidefinite complex Hermitian matrix and the analysis of algorithms by AnalyzeAlgorithm program assembled for this purpose. The closing part of this project describes implementation of

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Liu, Qiong. "Design of an IEEE double precision floating-point adder/subtractor in GaAs technology." Thesis, 1995. http://hdl.handle.net/2440/122410.

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This project aims to produce a 64-bit floating-point double precision adder/subtractor of a Solid Modelling accelerator in Gallium Arsenide technology, which is used to reduce computational time and to increase accuracy of algorithms. Addition is the most fundamental and the simplest operation in any computer arithmetic operation. According to the IEEE 754 Standard Format, the resulting architecture based on the addition/subtraction algorithm is mainly divided into two portions - the exponent and the mantissa. In logic design, there are three major difficult circuits including a mantissa shift

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Części książek na temat "Xilinx.Floating Point Subtractor"

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Gowreesrinivas, K. V., and P. Samundiswary. "Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3828-5_51.

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Ravi, T. "Architectural Design of 8-Bit Floating-Point Synchronous Adder and Subtractor for RISC ALU." In Emerging Research in Computing, Information, Communication and Applications. Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-0287-8_21.

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Bazil Raj, A. Arockia. "Floating-Point Computations with Very-High-Speed Integrated Circuit Hardware Description Language and Xilinx System Generator (SysGen) Tools." In FPGA-Based Embedded System Developer's Guide. CRC Press, 2018. http://dx.doi.org/10.1201/9781315156200-10.

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Groothuis Marcel A., van Zuijlen Jasper J.P., and Broenink Jan F. "FPGA based Control of a Production Cell System." In Concurrent Systems Engineering Series. IOS Press, 2008. https://doi.org/10.3233/978-1-58603-907-3-135.

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Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control software for this system is designed in gCSP using a reusable layered CSP based software structure. gCSP is extended with automatic Handel-C code generation for configuring the FPGA. Many motion control systems use floating point calculations for the loop controllers. Low cost general purpose FPGAs d

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Calore, Enrico, and Sebastiano Fabio Schifano. "Energy-Efficiency Evaluation of FPGAs for Floating-Point Intensive Workloads." In Parallel Computing: Technology Trends. IOS Press, 2020. http://dx.doi.org/10.3233/apc200085.

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In this work we describe a method to measure the computing performance and energy-efficiency to be expected of an FPGA device. The motivation of this work is given by their possible usage as accelerators in the context of floating-point intensive HPC workloads. In fact, FPGA devices in the past were not considered an efficient option to address floating-point intensive computations, but more recently, with the advent of dedicated DSP units and the increased amount of resources in each chip, the interest towards these devices raised. Another obstacle to a wide adoption of FPGAs in the HPC field

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Streszczenia konferencji na temat "Xilinx.Floating Point Subtractor"

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Minchola, Carlos, Martin Vazquez, and Gustavo Sutter. "A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor." In 2011 VII Southern Conference on Programmable Logic (SPL). IEEE, 2011. http://dx.doi.org/10.1109/spl.2011.5782657.

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Veeramachaneni, Sreehari, and M. B. Srinivas. "Floating point adder/subtractor units realization by efficient arithmetic circuits." In 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2015. http://dx.doi.org/10.1109/prime.2015.7251380.

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Hamid, Lamiaa Sayed Abdel, Khaled Shehata, Hassan El-Ghitani, and Mohamed ElSaid. "Design of Generic Floating Point Multiplier and Adder/Subtractor Units." In 2010 12th International Conference on Computer Modelling and Simulation. IEEE, 2010. http://dx.doi.org/10.1109/uksim.2010.117.

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Bommana, Ashish Reddy, and Srinivas Boppu. "A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization." In 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2022. http://dx.doi.org/10.1109/mcsoc57363.2022.00056.

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Farmahini-Farahani, Amin, Charles Tsen, and Katherine Compton. "FPGA implementation of a 64-Bit BID-based decimal floating-point adder/subtractor." In 2009 International Conference on Field-Programmable Technology (FPT). IEEE, 2009. http://dx.doi.org/10.1109/fpt.2009.5377636.

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Kadlec, Jiri. "Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators." In 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). IEEE, 2015. http://dx.doi.org/10.1109/samos.2015.7363690.

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Rahman, Atul, Abdullah-Al-Kafi, Mr Khalid, A. T. M. Saiful Islam, and Mahmudur Rahman. "Optimized hardware architecture for implementing IEEE 754 standard double precision floating point adder/subtractor." In 2014 17th International Conference on Computer and Information Technology (ICCIT). IEEE, 2014. http://dx.doi.org/10.1109/iccitechn.2014.7073135.

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Montano, Victor, and Manuel Jimenez. "Design and implementation of a scalable floating-point FFT IP core for Xilinx FPGAs." In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2010. http://dx.doi.org/10.1109/mwscas.2010.5548751.

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Alouane, Asma, Asma Ben Rhouma, and Adel Khedher. "A self control strategy for a delta inverter fed BDCM drive using Xilinx system generator with fixed point/floating point mode." In 2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA). IEEE, 2016. http://dx.doi.org/10.1109/sta.2016.7952033.

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Shirke, Milind, Sajish Chandrababu, and Yogindra Abhyankar. "Implementation of IEEE 754 compliant single precision floating-point adder unit supporting denormal inputs on Xilinx FPGA." In 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI). IEEE, 2017. http://dx.doi.org/10.1109/icpcsi.2017.8392326.

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