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McDaniel, Larry T. III. "An Investigation of Differential Power Analysis Attacks on FPGA-based Encryption Systems". Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/33451.
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Hardware devices implementing cryptographic algorithms are finding their way into many applications. As this happens, the ability to keep the data being processed or stored on the device secure grows more important. Power analysis attacks involve cryptographic hardware leaking information during encryption because power consumption is correlated to the key used for encryption. Power analysis attacks have proven successful against public and private key cryptosystems in a variety of form factors. The majority of the countermeasures that have been proposed for this attack are intended for software implementations on a microcontroller. This project focuses on the development of a VHDL tool for investigating power analysis attacks on FPGAs and exploring countermeasures that might be used.
The tool developed here counted the transitions of CLB output signals to estimate power and was used to explore the impact of possible gate-level countermeasures to differential power analysis. Using this tool, it was found that only a few nodes in the circuit have a high correlation to bits of the key. This means that modifying only a small portion of the circuit could dramatically increase the difficulty of mounting a differential power analysis attack on the hardware. Further investigation of the correlation between CLB outputs and the key showed that a tradeoff exists between the amount of space required for decorrelation versus the amount of decorrelation that is desired, allowing a designer to determine the amount of correlation that can be removed for available space. Filtering of glitches on CLB output signals slightly reduced the amount of correlation each CLB had. Finally, a decorrelation circuit was proposed and shown capable of decorrelating flip-flop outputs of a CLB, which account for less than 10% of the CLB outputs signals.Master of Science
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Manchanda, Antarpreet Singh. "Design Methodology for Differential Power Analysis Resistant Circuits". University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377866652.
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Belaïd, Sonia. "Security of cryptosystems against power-analysis attacks". Thesis, Paris, Ecole normale supérieure, 2015. http://www.theses.fr/2015ENSU0032/document.
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Les attaques par canaux auxiliaires sont les attaques les plus efficaces contre les systèmes cryptographiques. Alors que les attaques classiques n’exploitent que les entrées et sorties des algorithmes cryptographiques, les attaques par canaux auxiliaires utilisent également les fuites physiques du composant sous-jacent. Dans cette thèse, nous nous intéressons aux attaques par canaux auxiliaires qui exploitent la consommation de courant des composants pour retrouver les clefs secrètes. Ces attaques sont désignées par le terme attaques par analyse de courant. La majorité des attaques par analyse de courant existantes repose sur l’observation de variables dépendant uniquement de quelques bits de secret avec la stratégie diviser-pour-régner. Dans cette thèse, nous exhibons de nouvelles attaques qui exploitent l’observation de variables intermédiaires largement dépendantes de grands secrets. Notamment, nous montrons qu’en observant uniquement la fuite physique du résultat d’une multiplication de Galois entre une clef secrète de 128 bits et plusieurs messages connus, nous pouvons en déduire un système d’équations avec erreurs puis retrouver cette clef secrète. En parallèle, nous nous intéressons aux deux contre-mesures algorithmiques les plus répandues contre ces attaques par analyse de courant : les fonctions intrinsèquement résistantes aux fuites physiques et les schémas de masquage. Dans un premier temps, nous définissons un schéma de chiffrement résistant aux fuites physiques qui repose sur un rafraîchissement régulier de la clef secrète. Nous prouvons la sécurité de ce schéma dans le modèle de cryptographie résistante aux fuites (en anglais, leakage-resilient cryptography). Dans un second temps, nous construisons, à l’aide des méthodes formelles, un outil permettant de vérifier automatiquement la sécurité d’implémentations masquées. Nous exhibons également de nouvelles propriétés de sécurité, ainsi que des propriétés de composition qui nous permettent de générer une implémentation masquée à n’importe quel ordre à partir d’une implémentation non protégée. Finalement, nous présentons une étude de comparaison entre ces deux contre-mesures algorithmiques dans le but d’aider les experts industriels à déterminer la meilleure protection à intégrer dans leurs produits en fonction de leurs contraintes en termes de sécurité et de performancesSide-channel attacks are the most efficient attacks against cryptosystems. While the classical blackbox attacks only exploit the inputs and outputs of cryptographic algorithms, side-channel attacks also get use of the physical leakage released by the underlying device during algorithms executions. In this thesis, we focus on one kind of side-channel attacks which exploits the power consumption of the underlying device to recover the algorithms secret keys. They are gathered under the term power-analysis attacks. Most of the existing power-analysis attacks rely on the observations of variables which only depend on a few secret bits using a divide-and-conquer strategy. In this thesis, we exhibit new kinds of attacks which exploit the observation of intermediate variables highly dependent on huge secrets. In particular, we show how to recover a 128-bit key by only recording the leakage of the Galois multiplication’s results between several known messages and this secret key. We also study two commonly used algorithmic countermeasures against side-channel attacks: leakage resilience and masking. On the one hand, we define a leakage-resilient encryption scheme based on a regular update of the secret key and we prove its security. On the other hand, we build, using formal methods, a tool to automatically verify the security of masked algorithms. We also exhibit new security and compositional properties which can be used to generate masked algorithms at any security order from their unprotected versions. Finally, we propose a comparison between these two countermeasures in order to help industrial experts to determine the best protection to integrate in their products, according to their constraints in terms of security and performances
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Lomne, Victor. "Power and Electro-Magnetic Side-Channel Attacks : threats and countermeasures". Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20220.
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En cryptographie classique, un algorithme de chiffrement est considéré comme une boîte noire, et un attaquant n'a accès qu'aux textes clairs et chiffrés. Mais un circuit cryptographique émet aussi des informations sensibles lors d'une opération cryptographique, comme sa consommation de courant ou ses émissions électro-magnétiques. Par conséquent, différentes techniques, appelées attaques par canaux auxiliaires, permettent d'exploiter ces fuites d'informations physiques pour casser des algorithmes cryptographiques avec une complexité très faible en comparaison avec les méthodes de la cryptanalyse classique. Dans ce travail, les attaques par canaux auxiliaires basées sur la consommation de courant ou les émissions électro-magnétiques sont d'abord étudiées d'un point de vue algorithmique, et différentes améliorations sont proposées. Ensuite, une attention particulière est consacrée à l'exploitation du canal auxiliaire électro-magnétique, et un flot de simulation des radiations magnétiques des circuits intégrés est proposé et validé sur deux microcontrôleurs. Finalement, certaines contremesures permettant de protéger les algorithmes de chiffrement contre ces menaces, basées sur des styles de logique équilibrées, sont présentées et évaluéesIn cryptography, a cipher is considered as a black-box, and an attacker has only access to plaintexts and ciphertexts. But a real world cryptographic device leaks additionnal sensitive informations during a cryptographic operation, such as power consumption or electro-magnetic radiations. As a result, several techniques, called Side-Channel Attacks, allow exploiting these physical leakages to break ciphers with a very low complexity in comparison with methods of classical cryptanalysis. In this work, power and electro-magnetic Side-Channel Attacks are firstly studied from an algorithmic point-of-view, and some improvements are proposed. Then, a particular attention is given on the exploitation of the electro-magnetic side-channel, and a simulation flow predicting magnetic radiations of ICs is proposed and validated on two microcontrollers. Finally, some countermeasures allowing to protect ciphers against these threats, based on balanced logic styles, are presented and evaluated
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Carmona, Manuel Bejarano. "A simple and low cost platform to perform Power Analysis Attacks". Thesis, Blekinge Tekniska Högskola, Sektionen för ingenjörsvetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5811.
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Power Analysis Attacks use the fact that power consumption in modern microprocessors and cryptographic devices depends on the instructions executed on them and so, it varies with time. This leak- age is mainly used to deduce cryptographic keys as well as algorithms by direct observation of power traces. Power Analysis is a recent field of study that has been developed for the last decade. Since then, the techniques used have evolved into more complex forms, that some- times require a variety of skills that makes the subject difficult to start with. Nowadays it is changeling to tackle the problem without expen- sive equipment; what is more, the off-the-shelf solutions to do Power Analysis Attacks are rare and expensive. This thesis aim to provide a low cost and open platform as an entry point to Power Analysis for a price under 10 USD. Besides that, it is designed to be able to per- form Simple Power Analysis and Differential Power Analysis attacks to a 8 bit microcontroller, including the software needed to automate the process of taking the measurements. Finally, the platform can be extended to cover a wide range of microcontrollers, microprocessors and cryptographic devices by simple insertion in a bread board, which makes it the perfect device for new comers to the field.
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RAMMOHAN, SRIVIDHYA. "REDUCED COMPLEMENTARY DYNAMIC AND DIFFERENTIAL CMOS LOGIC: A DESIGN METHODOLOGY FOR DPA RESISTANT CRYPTOGRAPHIC CIRCUITS". University of Cincinnati / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1179459225.
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Perera, Kevin. "An Automatable Workflow to Analyze and Secure Integrated Circuits Against Power Analysis Attacks". Case Western Reserve University School of Graduate Studies / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=case1491319301653169.
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Yu, Weize. "Exploiting On-Chip Voltage Regulators as a Countermeasure Against Power Analysis Attacks". Scholar Commons, 2017. http://scholarcommons.usf.edu/etd/6986.
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Non-invasive side-channel attacks (SCA) are powerful attacks which can be used to obtain the secret key in a cryptographic circuit in feasible time without the need for expensive measurement equipment. Power analysis attacks (PAA) are a type of SCA that exploit the correlation between the leaked power consumption information and processed/stored data. Differential power analysis (DPA) and leakage power analysis (LPA) attacks are two types of PAA that exploit different characteristics of the side-channel leakage profile. DPA attacks exploit the correlation between the input data and dynamic power consumption of cryptographic circuits. Alternatively, LPA attacks utilize the correlation between the input data and leakage power dissipation of cryptographic circuits.
There is a growing trend to integrate voltage regulators fully on-chip in modern integrated circuits (ICs) to reduce the power noise, improve transient response time, and increase power efficiency. Therefore, when on-chip voltage regulation is utilized as a countermeasure against power analysis attacks, the overhead is low. However, a one-to-one relationship exists between the input power and load power when a conventional on-chip voltage regulator is utilized. In order to break the one-to-one relationship between the input power and load power, two methodologies can be considered: (a) selecting multi-phase on-chip voltage regulator and using pseudo-random number generator (PRNG) to scramble the activation or deactivation pattern of the multi-phase voltage regulator in the input power profile, (b) enabling random voltage/scaling on conventional on-chip voltage regulators to insert uncertainties to the load power profile.
In this dissertation, on-chip voltage regulators are utilized as lightweight countermeasures against power analysis attacks. Converter-reshuffling (CoRe) technique is proposed as a countermeasure against DPA attacks by using a PRNG to scramble the input power profile. The time-delayed CoRe technique is designed to eliminate machine learning-based DPA attacks through inserting a certain time delay. The charge-withheld CoRe technique is proposed to enhance the entropy of the input power profile against DPA attacks with two PRNGs. The security-adaptive (SA) voltage converter is designed to sense LPA attacks and activate countermeasure with low overhead. Additionally, three conventional on-chip voltage regulators: low-dropout (LDO) regulator, buck converter, and switched-capacitor converter are combined with three different kinds of voltage/frequency scaling techniques: random dynamic voltage and frequency scaling (RDVFS), random dynamic voltage scaling (RDVS), and aggressive voltage and frequency scaling (AVFS), respectively, against both DPA and LPA attacks.
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Rathnala, Prasanthi. "Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation". Thesis, University of Derby, 2017. http://hdl.handle.net/10545/621716.
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Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations. The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.
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Houssain, Hilal. "Elliptic curve cryptography algorithms resistant against power analysis attacks on resource constrained devices". Thesis, Clermont-Ferrand 2, 2012. http://www.theses.fr/2012CLF22286/document.
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Les systèmes de cryptographie à base de courbe elliptique (ECC) ont été adoptés comme des systèmes standardisés de cryptographie à clé publique (PKC) par l'IEEE, ANSI, NIST, SEC et WTLS. En comparaison avec la PKC traditionnelle, comme RSA et ElGamal, l'ECC offre le même niveau de sécurité avec des clés de plus petites tailles. Cela signifie des calculs plus rapides et une consommation d'énergie plus faible ainsi que des économies de mémoire et de bande passante. Par conséquent, ECC est devenue une technologie indispensable, plus populaire et considérée comme particulièrement adaptée à l’implémentation sur les dispositifs à ressources restreintes tels que les réseaux de capteurs sans fil (WSN). Le problème majeur avec les noeuds de capteurs chez les WSN, dès qu'il s'agit d’opérations cryptographiques, est les limitations de leurs ressources en termes de puissance, d'espace et de temps de réponse, ce qui limite la capacité du capteur à gérer les calculs supplémentaires nécessaires aux opérations cryptographiques. En outre, les mises en oeuvre actuelles de l’ECC sur WSN sont particulièrement vulnérables aux attaques par canaux auxiliaires (SCA), en particulier aux attaques par analyse de consommation (PAA), en raison de l'absence de la sécurité physique par blindage, leur déploiement dans les régions éloignées et le fait qu’elles soient laissées sans surveillance. Ainsi, les concepteurs de crypto-processeurs ECC sur WSN s'efforcent d'introduire des algorithmes et des architectures qui ne sont pas seulement résistants PAA, mais également efficaces sans aucun supplément en termes de temps, puissance et espace. Cette thèse présente plusieurs contributions dans le domaine des cryptoprocesseurs ECC conscientisés aux PAA, pour les dispositifs à ressources limitées comme le WSN. Premièrement, nous proposons deux architectures robustes et efficaces pour les ECC conscientisées au PAA. Ces architectures sont basées sur des algorithmes innovants qui assurent le fonctionnement de base des ECC et qui prévoient une sécurisation de l’ECC contre les PAA simples (SPA) sur les dispositifs à ressources limitées tels que les WSN. Deuxièmement, nous proposons deux architectures additionnelles qui prévoient une sécurisation des ECC contre les PAA différentiels (DPA). Troisièmement, un total de huit architectures qui incluent, en plus des quatre architectures citées ci-dessus pour SPA et DPA, deux autres architectures dérivées de l’architecture DPA conscientisée, ainsi que deux architectures PAA conscientisées. Les huit architectures proposées sont synthétisées en utilisant la technologie des réseaux de portes programmables in situ (FPGA). Quatrièmement, les huit architectures sont analysées et évaluées, et leurs performances comparées. En plus, une comparaison plus avancée effectuée sur le niveau de la complexité du coût (temps, puissance, et espace), fournit un cadre pour les concepteurs d'architecture pour sélectionner la conception la plus appropriée. Nos résultats montrent un avantage significatif de nos architectures proposées par rapport à la complexité du coût, en comparaison à d'autres solutions proposées récemment dans le domaine de la rechercheElliptic Curve Cryptosystems (ECC) have been adopted as a standardized Public Key Cryptosystems (PKC) by IEEE, ANSI, NIST, SEC and WTLS. In comparison to traditional PKC like RSA and ElGamal, ECC offer equivalent security with smaller key sizes, in less computation time, with lower power consumption, as well as memory and bandwidth savings. Therefore, ECC have become a vital technology, more popular and considered to be particularly suitable for implementation on resource constrained devices such as the Wireless Sensor Networks (WSN). Major problem with the sensor nodes in WSN as soon as it comes to cryptographic operations is their extreme constrained resources in terms of power, space, and time delay, which limit the sensor capability to handle the additional computations required by cryptographic operations. Moreover, the current ECC implementations in WSN are particularly vulnerable to Side Channel Analysis (SCA) attacks; in particularly to the Power Analysis Attacks (PAA), due to the lack of secure physical shielding, their deployment in remote regions and it is left unattended. Thus designers of ECC cryptoprocessors on WSN strive to introduce algorithms and architectures that are not only PAA resistant, but also efficient with no any extra cost in terms of power, time delay, and area. The contributions of this thesis to the domain of PAA aware elliptic curve cryptoprocessor for resource constrained devices are numerous. Firstly, we propose two robust and high efficient PAA aware elliptic curve cryptoprocessors architectures based on innovative algorithms for ECC core operation and envisioned at securing the elliptic curve cryptoprocessors against Simple Power Analysis (SPA) attacks on resource constrained devices such as the WSN. Secondly, we propose two additional architectures that are envisioned at securing the elliptic curve cryptoprocessors against Differential Power Analysis (DPA) attacks. Thirdly, a total of eight architectures which includes, in addition to the two SPA aware with the other two DPA awareproposed architectures, two more architectures derived from our DPA aware proposed once, along with two other similar PAA aware architectures. The eight proposed architectures are synthesized using Field Programmable Gate Array (FPGA) technology. Fourthly, the eight proposed architectures are analyzed and evaluated by comparing their performance results. In addition, a more advanced comparison, which is done on the cost complexity level (Area, Delay, and Power), provides a framework for the architecture designers to select the appropriate design. Our results show a significant advantage of our proposed architectures for cost complexity in comparison to the other latest proposed in the research field
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Graff, Nathaniel. "Differential Power Analysis In-Practice for Hardware Implementations of the Keccak Sponge Function". DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1838.
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The Keccak Sponge Function is the winner of the National Institute of Standards and Technology (NIST) competition to develop the Secure Hash Algorithm-3 Standard (SHA-3). Prior work has developed reference implementations of the algorithm and described the structures necessary to harden the algorithm against power analysis attacks which can weaken the cryptographic properties of the hash algorithm. This work demonstrates the architectural changes to the reference implementation necessary to achieve the theoretical side channel-resistant structures, compare their efficiency and performance characteristics after synthesis and place-and-route when implementing them on Field Programmable Gate Arrays (FPGAs), publish the resulting implementations under the Massachusetts Institute of Technology (MIT) open source license, and show that the resulting implementations demonstrably harden the sponge function against power analysis attacks.
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Laabidi, Selma. "Méthodologie de conception de composants intégrés protégés contre les attaques par corrélation". Phd thesis, Ecole Nationale Supérieure des Mines de Saint-Etienne, 2010. http://tel.archives-ouvertes.fr/tel-00488013.
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Les circuits cryptographiques, parce qu'ils contiennent des informations confidentielles, font l'objet de manipulations frauduleuses, appelées communément attaques, de la part de personnes mal intentionnées. Plusieurs attaques ont été répertoriées et analysées. Parmi elles, les attaques DPA (Differential Power Analysis), DEMA (Differential Electromagnetic Analysis), DBA (Differential Behavior Analysis) et les attaques en probing forment la classe des attaques par corrélation et sont considérés comme les plus redoutables car elles permettent de retrouver, à moindre coût, les clefs de chiffrement des algorithmes cryptographiques. Les concepteurs de circuits sécurisés ont été donc amené à ajouter des parades, appelées contre-mesures, afin de protéger les circuits de ces attaques. Ces contremesures doivent impacter au minimum les performances et le coût du circuit. Dans cette thèse, nous nous intéressons dans un premier temps aux attaques par corrélation, le principe de ces attaques est décrit ainsi que les principales contre-mesures pour y parer. Un formalisme décrivant de manière unique ces attaques est aussi proposé. Dans un deuxième temps, nous étudions les outils d'évaluation sécuritaires qui permettent d'estimer la résistance des circuits intégrés face aux attaques par corrélation. Après un état de l'art sur les outils existants, nous décrivons notre outil basé sur une recherche de corrélations entre le modèle du concepteur et le modèle qui peut être prédit par un attaquant. L'analyse de corrélations permet de déterminer les bits les plus sensibles pour mener à bien une attaque. Cet outil est intégré dans le flot de conception permettant ainsi d'évaluer la résistance des algorithmes cryptographiques au niveau RTL (Register Transfer Level) et portes.
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Chakkaravarthy, Manoj. "BDD Based Synthesis Flow for Design of DPA Resistant Cryptographic Circuits". University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1330025314.
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Máchal, Petr. "Neprofilující útoky proudovou analýzou". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242199.
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The work is mainly concerned with the possibilities of breaking the encryption algorithm AES with using of non-template attacks. In the introduction are listed techniques of differential analysis, which are using in the present, but for the sake of completeness is there mention about simple power analysis. In the next chapters are briefly described countermeasures against power analysis and further is described the AES algorithm. Most important parts are chapters where are described attack implementation on AES-128 through correlation power analysis and mutual information analysis. These attacks exploit power traces from www pages dedicated to book Power Analysis Attacks - Revealing the Secrets of Smartcards, http://DPAbook.org and especially to power traces from DPA Contest 4.2, http://www.dpacontest.org. In conclusion is comparison of methods based on the number of power traces needed for finding the key of secret message.
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Cioranesco, Jean-Michel. "Nouvelles Contre-Mesures pour la Protection de Circuits Intégrés". Thesis, Paris 1, 2014. http://www.theses.fr/2014PA010022/document.
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Les domaines d'application de la cryptographie embarquée sont très divers et se retrouvent au croisement de toutes les applications personnelles, avec un besoin évident de confidentialité des données et également de sécurité d'accès des moyens de paiement. Les attaques matérielles invasives ont fait de tous temps partie de l'environnement industriel. L'objectif de cette thèse est de proposer de nouvelles solutions pour protéger les circuits intégrés contre ces attaques physiques. La première partie décrit les notions d'attaques par canaux cachés, d'attaques invasives et de retro-conception. Plusieurs exemples de ces types d'attaques ont pu être mis en œuvre pendant le travail de recherche de cette thèse, ils sont présentés en détail dans cette partie. La deuxième partie est consacrée à des propositions de différentes contre-mesures pour contrer des attaques par canaux cachés ayant pour vecteur la consommation de courant. La troisième partie est dédiée à la protection contre les attaques invasives en utilisant divers types de boucliers et capteurs. Nous conclurons ce manuscrit de thèse par la proposition d'un bouclier actif cryptographique inviolable ayant pour but premier de contrer Je sondage, mais aussi celui de détecter l'injection de fautes et d'être immunisé contre les analyses par consommation de courantEmbedded security applications are diverse and at the center of all personal embedded applications. They introduced an obvious need for data confidentiality and security in general. Invasive attacks on hardware have always been part of the industrial scene. The aim of this thesis is to propose new solutions in order to protect embedded circuits against some physical attacks described above. ln a first part of the manuscript, we detail the techniques used to achieve side-channel, invasive attacks and reverse engineering. I could implement several of these attacks during my thesis research, they will be detailed extensively. ln the second part we propose different hardware countermeasures against side-channel attacks. The third part is dedicated to protection strategies against invasive attacks using active shielding and we conclude this work by proposing an innovative cryptographic shield which is faulty and dpa resistant
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Jakubíková, Radka. "Realizace útoku na maskovaný šifrovací algoritmus". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-220397.
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The cryptographic algorithms are commonly used as a security item today. In some situations, the special device is used to run the cryptographic algorithm, so the data are protected against the attack from the internet. Naturally, the attack can be loaded on the device as well using the side channel attack. The data are under the great danger, because nowadays plenty of power consumption analyses exist. The side channel attack uses knowledge about the cryptographic algoritm and simple or differential analysis. The diploma thesis focuses on the differential power analysis attack for the data published under the DPA contest. This thesis covers different types of analyss and attacks, and describes the new DPACv4.2 implementation. The correlation analysis is presented for the DPACv4.2 and the possible attack is discussed at the conclusion.
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Lu, Yingxi. "Power analysis attacks and low-cost countermeasures". Thesis, Queen's University Belfast, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.527836.
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Boey, Kean Hong. "Power analysis attacks and countermeasures for block ciphers". Thesis, Queen's University Belfast, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.579577.
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In today's digital world, cryptographic algorithms are commonly used in all aspects of our daily life. Whilst most of the modem cryptographic algorithms are secure against theoretical attacks, cryptographic algorithms can be compromised by monitoring the power consumption, which is known as power analysis attacks. The differential power analysis (DPA) attack is the most powerful attack. Although several countermeasures have been proposed to defend against power analysis attacks, these countermeasure techniques are costly to develop or need to be designed for specific encryption algorithms. In this thesis, a number of techniques and practical experiments have been undertaken to explore DPA attacks in more detail. DPA attacks were performed on two block cipher encryption algorithms CAST-128 and SEED. These two block ciphers use two round keys in each round function. However, existing power analysis attack strategies are not suitable for cryptographic algorithms that use two round keys in each round function. Therefore, two attack strategies have been proposed and targeted at the SBox component, in each of the algorithms to reveal the round keys. Unlike previous research which has mostly focused on simulation-based analysis of the SBox component, this research involved a focused analysis of DPA attacks of hardware implementations of the SBox component to investigate which SBox are more secure against such attacks. Based on this analysis, some recommendations for more power resistant SBox functionality were proposed. In this research two novel countermeasures, which misalign the power traces by randomly inserting idle cycle(s) or dummy cycle(s) in between two or more consecutive operations, are proposed to counteract power analysis attacks. The proposed countermeasures can be used to increase the resistance of a cryptographic device by reducing the overall SNR by more than 94%. Both the proposed countermeasures are better in terms of area and power consumption than other countermeasure techniques.
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Hodgers, Philip Thomas. "Pre-processing techniques for electromagnetic & power analysis attacks". Thesis, Queen's University Belfast, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.602543.
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The research presented in this thesis has led to several new pre-processing techniques that enhance side-channel analysis of near-field electromagnetic (EM) and power analysis waveforms. Three new power spectral density analysis techniques have been introduced, the sliding window, the overlapping window and the variable window methods. These approaches pre-process the information in the time-shift invariant frequency domain, overcoming issues of misalignment due to acquisition error or random insertion type countermeasures. A new pattern analysis technique, that models the charge and decay profiles of AES power consumption traces, has been shown to defeat a random clocking countermeasure. The individual rounds of the algorithm are identified, enabling the targeted round to be extracted from each trace. A further optimisation is demonstrated using a round separation metric to identify prior rounds where a sufficient power consumption decay has occurred, resulting in a further reduction in the number of traces required. The attack therefore overcomes the effects of the temporal misalignment and round amplitude variation caused by the random clocking countermeasure. The novel application of a DSP implementation of a phase-sensitive detector circuit has enabled the pre-processing of side-channel information to enhance the round patterns of an AES algorithm for the purposes of re-alignment and cryptographic signature extraction. The identification of locations on a device where the encryption signature is more readily visible, leads to a more efficient targeting of attacks in a side-channel cartography attack.
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Ambrose, Jude Angelo Computer Science & Engineering Faculty of Engineering UNSW. "Power analysis side channel attacks: the processor design-level context". Publisher:University of New South Wales. Computer Science & Engineering, 2009. http://handle.unsw.edu.au/1959.4/43756.
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The rapid increase in the use of embedded systems for performing secure transactions, has proportionally increased the security threats which are faced by such devices. Side channel attack, a sophisticated security threat to embedded devices like smartcards, mobile phones and PDAs, exploits the external manifestations like processing time, power consumption and electromagnetic emission to identify the internal computations. Power analysis attack, introduced by Kocher in 1998, is used by adversaries to eavesdrop on confidential data while the device is executing a secure transaction. The adversary observes the power trace dissipated/consumed by the chip during the encryption/decryption of the AES cryptographic program and predicts the secret key used for encryption by extracting necessary information from the power trace. Countermeasures proposed to overcome power analysis are data masking, table masking, current flattening, circuitry level solutions, dummy instruction insertions, balancing bit-flips, etc. All these techniques are either susceptible to multi-order side channel attacks, not sufficiently generic to cover all encryption algorithms, or burden the system with high area cost, run-time or energy consumption. The initial solution presented in this thesis is a HW/SW based randomised instruction injection technique, which infuses random instructions at random places during the execution of an application. Such randomisation obfuscates the secure information from the power profile, not allowing the adversary to extract the critical power segments for analysis. Further, the author devised a systematic method to measure the security level of a power sequence and used it to measure the number of random instructions needed, to suitably confuse the adversary. The proposed processor model costs 1.9% in additional area for a simplescalar processor, and costs on average 29.8% in runtime and 27.1% in additional energy consumption for six industry standard cryptographic algorithms. This design is extended to a processor architecture which automatically detects the execution of the most common encryption algorithms, starts to scramble the power waveform by adding randomly placed instructions with random register accesses, and stops injecting instructions when it is safe to do so. This approach has less overheads compared to previous solutions and avoids software instrumentation, allowing programmers with no special knowledge to use the system. The extended processor model costs an additional area of 1.2%, and an average of 25% in runtime and 28.5% in energy overheads for industry standard cryptographic algorithms. Due to the possibility of removing random injections using large number of samples (due to the random nature, a large number of samples will eliminate noise), the author proposes a multiprocessor 'algorithmic' balancing technique. This technique uses a dual processor architecture where two processors execute the same program in parallel, but with complementary intermediate data, thus balancing the bitflips. The second processor works in conjunction with the first processor for balancing only when encryption is performed, and both processors carry out independent tasks when no encryption is being performed. Both DES and AES cryptographic programs are investigated for balancing and the author shows that this technique is economical, while completely preventing power analysis attacks. The signature detection unit to capture encryption is also utilised, which is used in the instruction injection approach. This multiprocessor balancing approach reduces performance by 0.42% and 0.94% for AES and DES respectively. The hardware increase is 2X only when balancing is performed. Further, several future extensions for the balancing approach are proposed, by introducing random swapping of encryption iterations between cores. FPGA implementations of these processor designs are briefly described at the end of this thesis.
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Smith, Kenneth James. "Methodologies for power analysis attacks on hardware implementations of AES /". Online version of thesis, 2009. http://hdl.handle.net/1850/10751.
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Baddam, Karthik. "Hardware level countermeasures against differential power analysis". Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/300786/.
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Hardware implementations of mathematically secure algorithms unintentionally leak side channel information, that can be used to attack the device. Such attacks, known as side channel attacks, are becoming an increasingly important aspect of designing security systems. In this thesis, power analysis attacks are discussed along with existing countermeasures. In the first part of the thesis, the theory and practice of side-channel attacks is introduced. In particular, it is shown that plain implementations of block ciphers are highly susceptible to power-analysis attacks. Dual rail precharge (DRP) circuits have already been proposed as an effective countermeasure against power analysis attacks. DRP circuits suffer from an implementation problem; balancing the routing capacitance of differential signals. In this thesis we propose a new countermeasure, path switching, to address the routing problem in DRP circuits which has very low overheads compared to existing methods. The proposed countermeasure is tested with simulations and experimentally on an FPGA board. Results from these tests show a minimum of 75 times increase in the power traces required for a first order DPA attack. Some of the existing countermeasures to address the routing problem in DRP circuits do not consider coupling capacitance between differential signals. In this thesis we propose a new method, divided backend duplication that effectively addresses balanced the routing problem of DRP circuits. The proposed countermeasure is tested with simulations and results show a minimum of 300 times increase in the power traces required for a first order DPA attack. Randomisation as a DPA countermeasure is also explored. It is found that randomising the power consumption of the cryptographic device itself has little impact on DPA. Randomising the occurrence of intermediate results, on which DPA relies on, has better effect at mitigating DPA.
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Goodwin, John. "Novel countermeasures and techniques for differential power analysis". Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/72692/.
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Research in the last few years has indicated that, despite modern algorithms being secure against all published mathematical attacks and being far too complex to break by brute force, secret key data can be gathered by monitoring the power consumption. This is known as a power analysis attack, the most successful has been differential power analysis (DPA). Several countermeasures have been proposed for preventing power analysis attacks with varying degrees of efficacy. One thing all the countermeasures have in common is their large cost in terms of performance and or cost. In this thesis several modifications to the AES algorithm are proposed that seek to inherently secure it against DPA and their effectiveness and cost are investigated. Due to the statistical nature of DPA there is no set amount of power consumption data that will always give the correct result for a given device, rather, a value for the SNR and the number of power measurements involved in the attack will equate to a probability of success. In this thesis a statistical model of the DPA attack is derived and it is used to find a method for calculating the probability that a particular attack will be successful. A more benign use for DPA is also discussed. If the signature of a specific pattern of register transitions can be detected in the power consumption of a device then designers can add hardware whose sole purpose is to be detectable in a power trace and act as a watermark to prove the presence of intellectual property.
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Yalla, Panasayya S. V. V. K. "Differential power analysis on light weight implementations of block ciphers". Fairfax, VA : George Mason University, 2009. http://hdl.handle.net/1920/5622.
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Thesis (M.S.)--George Mason University, 2009.Vita: p. 60. Thesis director: Jens-Peter Kaps. Submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Engineering. Title from PDF t.p. (viewed Nov. 11, 2009). Includes bibliographical references (p. 57-59). Also issued in print.
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Fransson, Mattias. "Power Analysis of the Advanced Encryption Standard : Attacks and Countermeasures for 8-bit Microcontrollers". Thesis, Linköpings universitet, Informationskodning, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-122718.
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The Advanced Encryption Standard is one of the most common encryption algorithms. It is highly resistant to mathematical and statistical attacks, however, this security is based on the assumption that an adversary cannot access the algorithm’s internal state during encryption or decryption. Power analysis is a type of side-channel analysis that exploit information leakage through the power consumption of physical realisations of cryptographic systems. Power analysis attacks capture intermediate results during AES execution, which combined with knowledge of the plaintext or the ciphertext can reveal key material. This thesis studies and compares simple power analysis, differential power analysis and template attacks using a cheap consumer oscilloscope against AES-128 implemented on an 8-bit microcontroller. Additionally, the shuffling and masking countermeasures are evaluated in terms of security and performance. The thesis also presents a practical approach to template building and device characterisation. The results show that attacking a naive implementation with differential power analysis requires little effort, both in preparation and computation time. Template attacks require the least amount of measurements but requires significant preparation. Simple power analysis by itself cannot break the key but proves helpful in simplifying the other attacks. It is found that shuffling significantly increases the number of traces required to break the key while masking forces the attacker to use higher-order techniques.
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Char, Srinidhi Narasimha. "Transmission gate based logic for differential power analysis resistant circcuits [sic]". Connect to this title online, 2007. http://etd.lib.clemson.edu/documents/1193079255/.
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Kathuria, Tarun. "Gate-level Leakage Assessment and Mitigation". Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/101862.
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Side-channel leakage, caused by imperfect implementation of cryptographic algorithms in
hardware, has become a serious security threat for connected devices that generate and
process sensitive data. This side-channel leakage can divulge secret information in the form of
power consumption or electromagnetic emissions. The side-channel leakage of a crytographic
device is commonly assessed after tape-out on a physical prototype.
This thesis presents a methodology called Gate-level Leakage Assessment (GLA), which
evaluates the power-based side-channel leakage of an integrated circuit at design time. By
combining side-channel leakage assessment with power simulations on the gate-level netlist,
GLA is able to pinpoint the leakiest cells in the netlist in addition to assessing the overall
side-channel vulnerability to side-channel leakage. As the power traces obtained from power
simulations are noiseless, GLA is able to precisely locate the sources of side-channel leakage
with fewer measurements than on a physical prototype. The thesis applies the methodology
on the design of a encryption co-processor to analyze sources of side-channel leakage.
Once the gate-level leakage sources are identified, this thesis presents a logic level replacement
strategy for the leakage sources that can thwart side-channel leakage. The countermeasures
presented selectively replaces gate-level cells with a secure logic style effectively removing
the side-channel leakage with minimal impact in area. The assessment methodology along
with the countermeasures demonstrated is a turnkey solution for IP module designers and
is also applicable to larger system level designs.Master of Science
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Glass, Edmund. "Power Analysis in Applied Linear Regression for Cell Type-Specific Differential Expression Detection". VCU Scholars Compass, 2016. http://scholarscompass.vcu.edu/etd/4516.
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The goal of many human disease-oriented studies is to detect molecular mechanisms different between healthy controls and patients. Yet, commonly used gene expression measurements from any tissues suffer from variability of cell composition. This variability hinders the detection of differentially expressed genes and is often ignored. However, this variability may actually be advantageous, as heterogeneous gene expression measurements coupled with cell counts may provide deeper insights into the gene expression differences on the cell type-specific level. Published computational methods use linear regression to estimate cell type-specific differential expression. Yet, they do not consider many artifacts hidden in high-dimensional gene expression data that may negatively affect the performance of linear regression. In this dissertation we specifically address the parameter space involved in the most rigorous use of linear regression to estimate cell type-specific differential expression and report under which conditions significant detection is probable. We define parameters affecting the sensitivity of cell type-specific differential expression estimation as follows: sample size, cell type-specific proportion variability, mean squared error (spread of observations around linear regression line), conditioning of the cell proportions predictor matrix, and the size of actual cell type-specific differential expression. Each parameter, with the exception of cell type-specific differential expression (effect size), affects the variability of cell type-specific differential expression estimates. We have developed a power-analysis approach to cell type by cell type and genomic site by site differential expression detection which relies upon Welch’s two-sample t-test and factors in differences in cell type-specific expression estimate variability and reduces false discovery. To this end we have published an R package, LRCDE, available in GitHub (http://www.github.com/ERGlass/lrcde.dev) which outputs observed statistics of cell type-specific differential expression, including two-sample t- statistic, t-statistic p-value, and power calculated from two-sample t-statistic on a genomic site- by-site basis.
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Balachandran, Neerajnayan. "Low power memory controller subsystem IP exploration using RTL power flow : An End-to-end power analysis and reduction Methodology". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280095.
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With FinFET based Application Specific Integrated Circuit (ASIC) designs delivering on the promises of scalability, performance, and power, the road ahead is bumpy with technical challenges in building efficient ASICs. Designers can no longer rely on the ‘auto-scaling’ power reduction that follows technology node scaling, in these times when 7nm presents itself as a ‘long-lived’ node. This leads to the need for early power analysis and reduction flows that are incorporated into the ASIC Intellectual Property (IP) design flow. This leads to a focus on power-efficient design in addition to being functionally efficient. Power inefficiency related hotspots are the leading causes of chip re-spins, and a guideline methodology to design blocks in a power-efficient manner leads to a power-efficient design of the Integrated Circuits (ICs). This alleviates the intensity of cooling requirements and the cost. The Common Memory controller is one of the leading consumers of power in the ASIC designs at Ericsson. This Thesis focusses on developing a power analysis and reduction flow for the common memory controller by connecting the verification environment of the block to low-level power analysis tools, using motivated test cases to collect power metrics, thereby leading to two main goals of the Thesis, characterization and optimization of the block for power. This work also includes an energy efficiency perspective through the Differential Energy Analysis technique, initiated by Qualcomm and Ansys, to improve the flow by improving the test cases that help uncover power inefficiencies/bugs and therefore optimize the block. The flow developed in the Thesis fulfills the goals of characterizing and optimizing the block. The characterization data is presented to provide an idea of the type of data that can be collected and useful for SoC architects and designers in planning for future designs. The characterization/profiling data collected from the blocks collectively contribute to the Electronic System-level power analysis that helps correlate the ASIC power estimate to silicon. The work also validates the flow by working on a specific sub-block, identifying possible power bugs, modifying the design and validating improved performance and thereby, validating the flow.Med FinFET-baserade applikationsspecifika integrerade kretsar (ASIC) -konstruktioner som ger löften om skalbarhet, prestanda och kraft är vägen framåt ojämn med tekniska utmaningar när det gäller att bygga effektiva ASIC: er. Formgivare kan inte längre lita på den "autoskalande" effektminskningen som följer teknisk nodskalning, i dessa tider då 7nm presenterar sig som en "långlivad" nod. Detta leder till behovet av tidig kraftanalys och reduktionsflöden som är integrerade i ASIC Intellectual Property (IP) designflöde. Detta leder till fokus på energieffektiv design förutom att det är funktionellt effektivt. Krafteffektivitetsrelaterade hotspots är de ledande orsakerna till respins av chip, och en riktlinjemetodik för att konstruera block på ett energieffektivt sätt leder till energieffektiv design av Integrated Circuits (ICs). Detta lindrar intensiteten hos kylbehovet och kostnaden. Common Memory-kontrollen är en av de ledande energikonsumenterna i ASIC-designen hos Ericsson. Denna avhandling fokuserar på att utveckla en effektanalys och reduktionsflöde för den gemensamma minneskontrollern genom att ansluta verifieringsmiljön för blocket till lågnivåeffektanalysverktyg, med hjälp av motiverade test caser för att samla effektmätvärden, vilket leder till två huvudmål för avhandlingen, karakterisering och optimering av blocket för kraft. Detta arbete inkluderar också energieffektivitetsperspektiv genom Differential Energy Analys-teknik, initierad av Qualcomm och Ansys, för att förbättra flödet genom att förbättra test cases som hjälper till att upptäcka effekteffektivitet / buggar och därför optimera blocket. Flödet som utvecklats i avhandlingen uppfyller målen att karakterisera och optimera blocket. Karaktäriseringsdata presenteras för att ge en uppfattning om vilken typ av data som kan samlas in och vara användbara för SoC-arkitekter och designers i planering för framtida mönster. Karaktäriserings/ profileringsdata som samlats in från blocken bidrar tillsammans till effektanalysen för elektronisk systemnivå som hjälper till att korrelera ASIC-effektberäkningen till kisel. Arbetet validerar också flödet genom att arbeta på ett specifikt underblock, identifiera möjliga effektbuggar, modifiera utforma och validera förbättrad prestanda och därmed validera flödet.
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Stöttinger, Marc Sebastian Patric Verfasser], Sorin A. [Akademischer Betreuer] [Huss e Georg [Akademischer Betreuer] Sigl. "Mutating Runtime Architectures as a Countermeasure Against Power Analysis Attacks / Marc Sebastian Patric Stöttinger. Betreuer: Sorin Alexander Huss ; Georg Sigl". Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2013. http://d-nb.info/1106454448/34.
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Yu, Pengyuan. "Implementation of DPA-Resistant Circuit for FPGA". Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/32053.
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In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied submodule. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consumption-dependent information leaks. We will show all the necessary steps needed to implement secure circuits on a FPGA, from initial design stage all the way to verification of the level of security through laboratory measurements. We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. We demonstrate our approach on an FPGA prototype of a cryptographic design, and show through power-measurements followed by side-channel power analysis that secure logic implemented with our approach is resistant whereas non-routing-aware directly mapped circuit can be successfully attacked.Master of Science
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Lerman, Liran. "A machine learning approach for automatic and generic side-channel attacks". Doctoral thesis, Universite Libre de Bruxelles, 2015. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/209070.
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L'omniprésence de dispositifs interconnectés amène à un intérêt massif pour la sécurité informatique fournie entre autres par le domaine de la cryptographie. Pendant des décennies, les spécialistes en cryptographie estimaient le niveau de sécurité d'un algorithme cryptographique indépendamment de son implantation dans un dispositif. Cependant, depuis la publication des attaques d'implantation en 1996, les attaques physiques sont devenues un domaine de recherche actif en considérant les propriétés physiques de dispositifs cryptographiques. Dans notre dissertation, nous nous concentrons sur les attaques profilées. Traditionnellement, les attaques profilées appliquent des méthodes paramétriques dans lesquelles une information a priori sur les propriétés physiques est supposée. Le domaine de l'apprentissage automatique produit des modèles automatiques et génériques ne nécessitant pas une information a priori sur le phénomène étudié.Cette dissertation apporte un éclairage nouveau sur les capacités des méthodes d'apprentissage automatique. Nous démontrons d'abord que les attaques profilées paramétriques surpassent les méthodes d'apprentissage automatique lorsqu'il n'y a pas d'erreur d'estimation ni d'hypothèse. En revanche, les attaques fondées sur l'apprentissage automatique sont avantageuses dans des scénarios réalistes où le nombre de données lors de l'étape d'apprentissage est faible. Par la suite, nous proposons une nouvelle métrique formelle d'évaluation qui permet (1) de comparer des attaques paramétriques et non-paramétriques et (2) d'interpréter les résultats de chaque méthode. La nouvelle mesure fournit les causes d'un taux de réussite élevé ou faible d'une attaque et, par conséquent, donne des pistes pour améliorer l'évaluation d'une implantation. Enfin, nous présentons des résultats expérimentaux sur des appareils non protégés et protégés. La première étude montre que l'apprentissage automatique a un taux de réussite plus élevé qu'une méthode paramétrique lorsque seules quelques données sont disponibles. La deuxième expérience démontre qu'un dispositif protégé est attaquable avec une approche appartenant à l'apprentissage automatique. La stratégie basée sur l'apprentissage automatique nécessite le même nombre de données lors de la phase d'apprentissage que lorsque celle-ci attaque un produit non protégé. Nous montrons également que des méthodes paramétriques surestiment ou sous-estiment le niveau de sécurité fourni par l'appareil alors que l'approche basée sur l'apprentissage automatique améliore cette estimation.
En résumé, notre thèse est que les attaques basées sur l'apprentissage automatique sont avantageuses par rapport aux techniques classiques lorsque la quantité d'information a priori sur l'appareil cible et le nombre de données lors de la phase d'apprentissage sont faibles.
Doctorat en Sciences
info:eu-repo/semantics/nonPublished
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Ghanavati, Goodarz. "Statistical Analysis of High Sample Rate Time-series Data for Power System Stability Assessment". ScholarWorks @ UVM, 2015. http://scholarworks.uvm.edu/graddis/333.
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The motivation for this research is to leverage the increasing deployment of the phasor measurement unit (PMU) technology by electric utilities in order to improve situational awareness in power systems. PMUs provide unprecedentedly fast and synchronized voltage and current measurements across the system. Analyzing the big data provided by PMUs may prove helpful in reducing the risk of blackouts, such as the Northeast blackout in August 2003, which have resulted in huge costs in past decades.
In order to provide deeper insight into early warning signs (EWS) of catastrophic events in power systems, this dissertation studies changes in statistical properties of high-resolution measurements as a power system approaches a critical transition. The EWS under study are increases in variance and autocorrelation of state variables, which are generic signs of a phenomenon known as critical slowing down (CSD).
Critical slowing down is the result of slower recovery of a dynamical system from perturbations when the system approaches a critical transition. CSD has been observed in many stochastic nonlinear dynamical systems such as ecosystem, human body and power system. Although CSD signs can be useful as indicators of proximity to critical transitions, their characteristics vary for different systems and different variables within a system.
The dissertation provides evidence for the occurrence of CSD in power systems using a comprehensive analytical and numerical study of this phenomenon in several power system test cases. Together, the results show that it is possible extract information regarding not only the proximity of a power system to critical transitions but also the location of the stress in the system from autocorrelation and variance of measurements. Also, a semi-analytical method for fast computation of expected variance and autocorrelation of state variables in large power systems is presented, which allows one to quickly identify locations and variables that are reliable indicators of proximity to instability.
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Al-Hajri, Muhammad T. "Electrical power energy optimization at hydrocarbon industrial plant using intelligent algorithms". Thesis, Brunel University, 2016. http://bura.brunel.ac.uk/handle/2438/12681.
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In this work, the potential of intelligent algorithms for optimizing the real power loss and enhancing the grid connection power factor in a real hydrocarbon facility electrical system is assessed. Namely, genetic algorithm (GA), improve strength Pareto evolutionary algorithm (SPEA2) and differential evolutionary algorithm (DEA) are developed and implemented. The economic impact associated with these objectives optimization is highlighted. The optimization of the subject objectives is addressed as single and multi-objective constrained nonlinear problems. Different generation modes and system injected reactive power cases are evaluated. The studied electrical system constraints and parameters are all real values. The uniqueness of this thesis is that none of the previous literature studies addressed the technical and economic impacts of optimizing the aforementioned objectives for real hydrocarbon facility electrical system. All the economic analyses in this thesis are performed based on real subsidized cost of energy for the kingdom of Saudi Arabia. The obtained results demonstrate the high potential of optimizing the studied system objectives and enhancing the economics of the utilized generation fuel via the application of intelligent algorithms.
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Zapletal, Ondřej. "Klasifikátory proudových otisků". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-220592.
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Over the last several years side-channel analysis has emerged as a major threat to securing sensitive information in cryptographic devices. Several side-channels have been discovered and used to break implementations of all major cryptographic algorithms (AES, DES, RSA). This thesis is focused on power analysis attacks. A variety of power analysis methods has been developed to perform these attacks. These methods include simple power analysis (SPA), differential power analysis (DPA), template attacks, etc. This work provides comprehensive survey of mentioned methods and also investigates the application of a machine learning techniques in power analysis. The considered learning techniques are neural networks and support vector machines. The final part of this thesis is dedicated to implemenation of the attack against protected software AES implementation which is used in the DPA Contest.
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Mohammad, Azhar. "EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS". UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/125.
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The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.
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Chamas, Ibrahim. "The Analysis and Design of Phase-tunable Low-Power Low-Phase-Noise I/Q Signal Sources for Analog Phase Calibrated Transceivers". Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/102076.
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Due to the demand for low-cost, small-form factor and large-scale integration of system-on-chip wireless transceivers, the image-reject, zero-IF and low-IF receiver architectures have become the main topologies used in mainstream wireless communication systems. Consequently, signal sources with quadrature phase outputs [quadrature oscillators (QOs)] are therefore essential, and their phase noise, driving capability, tuning range, oscillation frequency, and power consumption have a major impact on the overall receiver performance. Additionally, it is required that the QO synthesize precise I/Q waveforms across the signal bandwidth over process, voltage, and temperature variations for adequate image-rejection and signal modulation/demodulation. While the use of symmetrical layout and large inter-digitated devices minimize both systematic and random mismatches, this solution alone may not succeed in achieving the stringent performance requirements dictated by modern wireless standards particularly as the technology scales into the sub-100nm regime, necessitating both phase and gain calibration of the mismatched I/Q channels post-fabrication. Given the necessity for precise RF quadrature signal synthesis, the goal of this work is to investigate low-power low-phase-noise quadrature oscillator (QVCO) topologies with an integrated phase calibration feature.
The first part of this work focuses on the analysis and modeling of cross-coupled LC QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, design trade-offs, phase-noise performance, effect of including phase shift in the coupling paths, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. Particularly, we introduce the concept of an effective core and coupling transconductances to explain various oscillator properties. Additionally, a new incremental circuit element — the quadrature resistance — is introduced to evaluate the effect of coupling on the open-loop quality factor and hence on the oscillator phase noise performance. Mechanisms affecting the mode selectivity are identified and modeled. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation.
Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based on the disconnected-source parallel-coupled LC QVCO topology. The phase-tunable LC QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the relative amplitude error or consuming additional power or chip area. Additionally, in restoring the phase balance, it is observed that the proposed method restores the phase noise performance to its optimal value which presents a potential advantage over classical calibration techniques. Time domain measurements performed on a 5 GHz prototype show that I/Q signals with phase error up to ~±30°, beyond which the VCO cores are unlocked, can be driven to perfect quadrature phase. The PT-QVCO can be tuned from 3.87-4.45 GHz at the negative mode and 4.4-5.4 GHz at the positive mode, a total of ~1.5 GHz. The fabricated circuit including pad structures occupies an area of 1.1x0.7 mm² and drains 18mW (excluding buffer circuits) from a 1.8 V supply voltage.
The third part of this work introduces a new low-power, low-phase-noise super harmonic injection-coupled LC QVCO (IC-QVCO) topology. Analysis of the waveform accuracy reveals an inverse dependence of the quadrature error on the tank quality factor thus allowing circuit optimization for both low phase noise and precise quadrature synthesis. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-σ variation in the device parameters. An X-band IC-QVCO prototype with a TTF implemented in a 0.18μm RF CMOS process, achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz along the 9.0 to 9.6 GHz frequency tuning range while dissipating only 9mW from the 1.8V supply. The TTF reduces both the 1/f² and 1/f³ phase noise and calibrates the residual phase error within ±11° post-fabrication without affecting the relative amplitude error or the phase noise performance. The circuit performance compares favorably with recently published work.
In the fourth part of this work, we explore the implementation of LC QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an MOS varactor and a digitally controlled switch capacitor array for frequency tuning, we propose an alternative frequency tuning technique based on the fundamental operation of LC QVCOs. The off-resonance operation, which is defined by the coupling network, suggests varying the coupling current to achieve frequency tuning. In essence, by modifying the bias current of the coupling transistors (GMc-tuning), a wide and linear frequency tuning range can be achieved. Extensive simulation results of a 60 GHz prototype, implemented in a 90 nm commercial RF CMOS process, demonstrates a 5 GHz of frequency tuning range (57.5 GHz → 62.5 GHz), a tuning sensitivity of 1GHz/mA, and a 4dB improvement in the phase noise compared to a varactor solution.
Finally, the Appendix includes recent research work on the analysis and design of gPh.D.
While resting in bed due to illness, the Dutch scientist Christiaan Huygens keenly observed that the pendulums of two clocks hanging on the wall moved synchronously when the clocks were hung close to each other. He concluded that these two oscillatory systems were forced to move in unison by virtue of mechanical coupling through the wall. In essence, each pendulum injected mechanical vibrations into the wall that was strong enough to lock the adjacent pendulum into synchronous motion. Injection locking of oscillatory systems plays a critical role in communication systems ranging from frequency division, to generating clocks (oscillators) with finer phase separation, to the synthesis of orthogonal (quadrature) clocks. All communication systems have the same basic form. Firstly, there will some type of an information or data source which can be a keyboard or a microphone in a smartphone. The source is connected to a receiver by some sort of a channel. In wireless systems, the channel is the air medium. Moreover, to comply with the FCC and 3GPP requirements, data can only be transmitted wirelessly within a predefined set of frequencies and with stringent emission requirements to avoid interference with other wireless systems. These frequencies are generated by high fidelity clock sources, also known as oscillators. Consider a group of people sharing the same room and hence the same channel want to share information. Without regulating the “loudness” of each communicating ensemble, the quality of communication can be severely impaired. Moreover, it is to be expected that information can be shared more efficiently if each pair is allocated non-overlapping timeslots – speak when others are quiet. Called time orthogonality, all wireless systems require precise orthogonal (quadrature) clock sources to improve the communication efficiency. The precision of quadrature clocks is determined by the amplitude and phase accuracy. This dissertation takes a deep dive into the analysis and implementation of high accuracy quadrature (I/Q) clock sources using the concept of injection locking. These I/Q clocks or oscillators, also known as quadrature voltage controlled oscillators (QVCOs), have gained enormous popularity in the last decade. The first part of this work focuses on the analysis and modeling of QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based The phase-tunable QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the oscillator other performance metrics. The proposed topology was successfully verified in silicon using a 5GHz prototype. The third part of this work introduces a new low-power, low-phase-noise injection coupled QVCO (IC-QVCO) topology. An X-band IC-QVCO prototype was successfully verified in a 0.18m RF CMOS process. In the fourth part of this work, we explore the implementation of QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an conventional frequency tuning techniques, we propose an alternative approach based on the fundamental operation of QVCOs that outperforms existing solutions.
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González, Zumba Jorge Andrés. "Dynamic Modeling and Stability Analysis of Stochastic Multi-Physical Systems Applied to Electric Power Systems". Doctoral thesis, Universitat Politècnica de València, 2021. http://hdl.handle.net/10251/158558.
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[ES] La naturaleza aleatoria que caracteriza algunos fenómenos en sistemas físicos reales (e.g., ingeniería, biología, economía, finanzas, epidemiología y otros) nos ha planteado el desafío de un cambio de paradigma del modelado matemático y el análisis de sistemas dinámicos, y a tratar los fenómenos aleatorios como variables aleatorias o procesos estocásticos. Este enfoque novedoso ha traído como consecuencia nuevas especificidades que la teoría clásica del modelado y análisis de sistemas dinámicos deterministas no ha podido cubrir. Afortunadamente, maravillosas contribuciones, realizadas sobre todo en el último siglo, desde el campo de las matemáticas por científicos como Kolmogorov, Langevin, Lévy, Itô, Stratonovich, sólo por nombrar algunos; han abierto las puertas para un estudio bien fundamentado de la dinámica de sistemas físicos perturbados por ruido.
En la presente tesis se discute el uso de ecuaciones diferenciales algebraicas estocásticas (EDAEs) para el modelado de sistemas multifísicos en red afectados por perturbaciones estocásticas, así como la evaluación de su estabilidad asintótica a través de exponentes de Lyapunov (ELs). El estudio está enfocado en EDAEs d-index-1 y su reformulación como ecuaciones diferenciales estocásticas ordinarias (EDEs). Fundamentados en la teoría ergódica, es factible analizar los ELs a través de sistemas dinámicos aleatorios (SDAs) generados por EDEs subyacentes. Una vez garantizada la existencia de ELs bien definidas, hemos procedido al uso de técnicas de simulación numérica para determinar los ELs numéricamente. Hemos implementado métodos numéricos basados en descomposición QR discreta y continua para el cómputo de la matriz de solución fundamental y su uso en el cálculo de los ELs. Las características numéricas y computacionales más relevantes de ambos métodos se ilustran mediante pruebas numéricas. Toda esta investigación sobre el modelado de sistemas con EDAEs y evaluación de su estabilidad a través de ELs calculados numéricamente, tiene una interesante aplicación en ingeniería. Esta es la evaluación de la estabilidad dinámica de sistemas eléctricos de potencia. En el presente trabajo de investigación, implementamos nuestros métodos numéricos basados en descomposición QR para el test de estabilidad dinámica en dos modelos de sistemas eléctricos de potencia de una-máquina bus-infinito (OMBI) afectados por diferentes perturbaciones ruidosas. El análisis en pequeña-señal evidencia el potencial de las técnicas propuestas en aplicaciones de ingeniería.[CA] La naturalesa aleatòria que caracteritza alguns fenòmens en sistemes físics reals (e.g., enginyeria, biologia, economia, finances, epidemiologia i uns altres) ens ha plantejat el desafiament d'un canvi de paradigma del modelatge matemàtic i l'anàlisi de sistemes dinàmics, i a tractar els fenòmens aleatoris com a variables aleatòries o processos estocàstics. Aquest enfocament nou ha portat com a conseqüència noves especificitats que la teoria clàssica del modelatge i anàlisi de sistemes dinàmics deterministes no ha pogut cobrir. Afortunadament, meravelloses contribucions, realitzades sobretot en l'últim segle, des del camp de les matemàtiques per científics com Kolmogorov, Langevin, Lévy, Itô, Stratonovich, només per nomenar alguns; han obert les portes per a un estudi ben fonamentat de la dinàmica de sistemes físics pertorbats per soroll. En la present tesi es discuteix l'ús d'equacions diferencials algebraiques estocàstiques (EDAEs) per al modelatge de sistemes multifísicos en xarxa afectats per pertorbacions estocàstiques, així com l'avaluació de la seua estabilitat asimptòtica a través d'exponents de Lyapunov (ELs). L'estudi està enfocat en EDAEs d-index-1 i la seua reformulació com a equacions diferencials estocàstiques ordinàries (EDEs). Fonamentats en la teoria ergòdica, és factible analitzar els ELs a través de sistemes dinàmics aleatoris (SDAs) generats per EDEs subjacents. Una vegada garantida l'existència d'ELs ben definides, hem procedit a l'ús de tècniques de simulació numèrica per a determinar els ELs numèricament. Hem implementat mètodes numèrics basats en descomposició QR discreta i contínua per al còmput de la matriu de solució fonamental i el seu ús en el càlcul dels ELs. Les característiques numèriques i computacionals més rellevants de tots dos mètodes s'illustren mitjançant proves numèriques. Tota aquesta investigació sobre el modelatge de sistemes amb EDAEs i avaluació de la seua estabilitat a través d'ELs calculats numèricament, té una interessant aplicació en enginyeria. Aquesta és l'avaluació de l'estabilitat dinàmica de sistemes elèctrics de potència. En el present treball de recerca, implementem els nostres mètodes numèrics basats en descomposició QR per al test d'estabilitat dinàmica en dos models de sistemes elèctrics de potència d'una-màquina bus-infinit (OMBI) afectats per diferents pertorbacions sorolloses. L'anàlisi en xicotet-senyal evidencia el potencial de les tècniques proposades en aplicacions d'enginyeria.
[EN] The random nature that characterizes some phenomena in the real-world physical systems (e.g., engineering, biology, economics, finance, epidemiology, and others) has posed the challenge of changing the modeling and analysis paradigm and treat these phenomena as random variables or stochastic processes. Consequently, this novel approach has brought new specificities that the classical theory of modeling and analysis for deterministic dynamical systems cannot cover. Fortunately, stunning contributions made overall in the last century from the mathematics field by scientists such as Kolmogorov, Langevin, Lévy, Itô, Stratonovich, to name a few; have opened avenues for a well-founded study of the dynamics in physical systems perturbed by noise. In the present thesis, we discuss stochastic differential-algebraic equations (SDAEs) for modeling multi-physical network systems under stochastic disturbances, and their asymptotic stability assessment via Lyapunov exponents (LEs). We focus on d-index-1 SDAEs and their reformulation as ordinary stochastic differential equations (SDEs). Supported by the ergodic theory, it is feasible to analyze the LEs via the random dynamical system (RDSs) generated by the underlying SDEs. Once the existence of well-defined LEs is guaranteed, we proceed to the use of numerical simulation techniques to determine the LEs numerically. Discrete and continuous QR decomposition-based numerical methods are implemented to compute the fundamental solution matrix and use it in the computation of the LEs. Important numerical and computational features of both methods are illustrated through numerical tests. All this investigation concerning systems modeling through SDAEs and their stability assessment via computed LEs finds an appealing engineering application in the dynamic stability assessment of power systems. In this research work, we implement our QR-based numerical methods for testing the dynamic stability in two types of single-machine infinite-bus (SMIB) power system models perturbed by different noisy disturbances. The analysis in small-signal evidences the potential of the proposed techniques in engineering applications.
Mi agradecimiento al estado ecuatoriano que, a través del Programa de Becas para el Fortalecimiento y Desarrollo del Talento Humano en Ciencia y Tecnología 2012 de la Secretaría Nacional de Educación Superior, Ciencia y Tecnología (SENESCYT), han financiado mis estudios de doctorado.
González Zumba, JA. (2020). Dynamic Modeling and Stability Analysis of Stochastic Multi-Physical Systems Applied to Electric Power Systems [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/158558
TESIS
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Daněček, Petr. "Útoky na kryptografické moduly". Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-233418.
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The conventional way of cryptanalysis is based on the cryptographic algorithms weak points examine. The attack model of conventional cryptanalysis covers mathematical description of the cryptographic algorithm used. This model is not with the relation to the physical model implementation and the real environment. Cryptographic algorithms currently used in the combination with strong cipher keys are almost unbreakable and the conventional cryptanalysis is ineffective. The new way of cryptanalysis employs the side channels. The model of cryptanalysis using side channels is enhanced with physical revelation of module performing the cryptographic operations. This dissertation thesis deals with cryptographic module description and studies influence of side channels to the security of this module.
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Martinásek, Zdeněk. "Kryptoanalýza postranními kanály". Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-233604.
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Side channels fundamentally changes the view of the cryptographic system security in cryptography. It is not enough to analyze the security algorithm only from a mathematical point of view using abstract models but it is necessary to focus on the implementation of the algorithms. The introduction of the thesis deals with the basic terms, principles of side channel attacks and basic clasification of side channels. The following chapter describes the objectives of the thesis. The main goal of the thesis is to propose and experimentally verify a new power analysis method whish will use the neural network. This main goal was based on the realized analyzes presented in the following chapters. These chapters contain a detailed analysis of currently used power analysis and analysis of AES encryption algorithm. AES was selected becouse the algorithm is resistant to the conventional cryptoanalysis. The following section describes the experimental results of the optimization of existing methods, the influence of the parameters affecting power consumption and the results of the proposed analysis using neural networks. This section includes the discussion of the results. This type of side channel attack has not been published yet thus it is a completely new idea. The final goal of the thesis was to summarize the possible countermeasures protecting against the side channel attacks.
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Mena, Rodrigo. "Risk–based modeling, simulation and optimization for the integration of renewable distributed generation into electric power networks". Thesis, Châtenay-Malabry, Ecole centrale de Paris, 2015. http://www.theses.fr/2015ECAP0034/document.
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Il est prévu que la génération distribuée par l’entremise d’énergie de sources renouvelables (DG) continuera à jouer un rôle clé dans le développement et l’exploitation des systèmes de puissance électrique durables, efficaces et fiables, en vertu de cette fournit une alternative pratique de décentralisation et diversification de la demande globale d’énergie, bénéficiant de sources d’énergie plus propres et plus sûrs. L’intégration de DG renouvelable dans les réseaux électriques existants pose des défis socio–technico–économiques, qu’ont attirés de la recherche et de progrès substantiels.Dans ce contexte, la présente thèse a pour objet la conception et le développement d’un cadre de modélisation, simulation et optimisation pour l’intégration de DG renouvelable dans des réseaux de puissance électrique existants. Le problème spécifique à considérer est celui de la sélection de la technologie,la taille et l’emplacement de des unités de génération renouvelable d’énergie, sous des contraintes techniques, opérationnelles et économiques. Dans ce problème, les questions de recherche clés à aborder sont: (i) la représentation et le traitement des variables physiques incertains (comme la disponibilité de les diverses sources primaires d’énergie renouvelables, l’approvisionnement d’électricité en vrac, la demande de puissance et l’apparition de défaillances de composants) qui déterminent dynamiquement l’exploitation du réseau DG–intégré, (ii) la propagation de ces incertitudes sur la réponse opérationnelle du système et le suivi du risque associé et (iii) les efforts de calcul intensif résultant du problème complexe d’optimisation combinatoire associé à l’intégration de DG renouvelable.Pour l’évaluation du système avec un plan d’intégration de DG renouvelable donné, un modèle de calcul de simulation Monte Carlo non–séquentielle et des flux de puissance optimale (MCS–OPF) a été conçu et mis en oeuvre, et qui émule l’exploitation du réseau DG–intégré. Réalisations aléatoires de scénarios opérationnels sont générés par échantillonnage à partir des différentes distributions des variables incertaines, et pour chaque scénario, la performance du système est évaluée en termes économiques et de la fiabilité de l’approvisionnement en électricité, représenté par le coût global (CG) et l’énergie non fournie (ENS), respectivement. Pour mesurer et contrôler le risque par rapport à la performance du système, deux indicateurs sont introduits, la valeur–à–risque conditionnelle(CVaR) et l’écart du CVaR (DCVaR).Pour la sélection optimale de la technologie, la taille et l’emplacement des unités DG renouvelables,deux approches distinctes d’optimisation multi–objectif (MOO) ont été mis en oeuvre par moteurs de recherche d’heuristique d’optimisation (HO). La première approche est basée sur l’algorithme génétique élitiste de tri non-dominé (NSGA–II) et vise à la réduction concomitante de l’espérance mathématique de CG et de ENS, dénotés ECG et EENS, respectivement, combiné avec leur valeurs correspondent de CVaR(CG) et CVaR(ENS); la seconde approche effectue un recherche à évolution différentielle MOO (DE) pour minimiser simultanément ECG et s’écart associé DCVaR(CG). Les deux approches d’optimisation intègrent la modèle de calcul MCS–OPF pour évaluer la performance de chaque réseau DG–intégré proposé par le moteur de recherche HO.Le défi provenant de les grands efforts de calcul requises par les cadres de simulation et d’optimisation proposée a été abordée par l’introduction d’une technique originale, qui niche l’analyse de classification hiérarchique (HCA) dans un moteur de recherche de DE.Exemples d’application des cadres proposés ont été élaborés, concernant une adaptation duréseau test de distribution électrique IEEE 13–noeuds et un cadre réaliste du système test de sous–transmission et de distribution IEEE 30–noeuds. [...]Renewable distributed generation (DG) is expected to continue playing a fundamental role in the development and operation of sustainable, efficient and reliable electric power systems, by virtue of offering a practical alternative to diversify and decentralize the overall power generation, benefiting from cleaner and safer energy sources. The integration of renewable DG in the existing electric powernetworks poses socio–techno–economical challenges, which have attracted substantial research and advancement.In this context, the focus of the present thesis is the design and development of a modeling,simulation and optimization framework for the integration of renewable DG into electric powernetworks. The specific problem considered is that of selecting the technology, size and location of renewable generation units, under technical, operational and economic constraints. Within this problem, key research questions to be addressed are: (i) the representation and treatment of the uncertain physical variables (like the availability of diverse primary renewable energy sources, bulk–power supply, power demands and occurrence of components failures) that dynamically determine the DG–integrated network operation, (ii) the propagation of these uncertainties onto the system operational response and the control of the associated risk and (iii) the intensive computational efforts resulting from the complex combinatorial optimization problem of renewable DG integration.For the evaluation of the system with a given plan of renewable DG, a non–sequential MonteCarlo simulation and optimal power flow (MCS–OPF) computational model has been designed and implemented, that emulates the DG–integrated network operation. Random realizations of operational scenarios are generated by sampling from the different uncertain variables distributions,and for each scenario the system performance is evaluated in terms of economics and reliability of power supply, represented by the global cost (CG) and the energy not supplied (ENS), respectively.To measure and control the risk relative to system performance, two indicators are introduced, the conditional value–at–risk (CVaR) and the CVaR deviation (DCVaR).For the optimal technology selection, size and location of the renewable DG units, two distinct multi–objective optimization (MOO) approaches have been implemented by heuristic optimization(HO) search engines. The first approach is based on the fast non–dominated sorting genetic algorithm(NSGA–II) and aims at the concurrent minimization of the expected values of CG and ENS, thenECG and EENS, respectively, combined with their corresponding CVaR(CG) and CVaR(ENS) values; the second approach carries out a MOO differential evolution (DE) search to minimize simultaneously ECG and its associated deviation DCVaR(CG). Both optimization approaches embed the MCS–OPF computational model to evaluate the performance of each DG–integrated network proposed by the HO search engine. The challenge coming from the large computational efforts required by the proposed simulation and optimization frameworks has been addressed introducing an original technique, which nests hierarchical clustering analysis (HCA) within a DE search engine. Examples of application of the proposed frameworks have been worked out, regarding an adaptation of the IEEE 13 bus distribution test feeder and a realistic setting of the IEEE 30 bussub–transmission and distribution test system. The results show that these frameworks are effectivein finding optimal DG–integrated networks solutions, while controlling risk from two distinctperspectives: directly through the use of CVaR and indirectly by targeting uncertainty in the form ofDCVaR. Moreover, CVaR acts as an enabler of trade–offs between optimal expected performanceand risk, and DCVaR integrates also uncertainty into the analysis, providing a wider spectrum ofinformation for well–supported and confident decision making
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Dehbaoui, Amine. "Analyse Sécuritaire des Émanations Électromagnétiques des Circuits Intégrés". Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20020.
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Le développement de la société de l'information et de la monnaie virtuelle, a soulevé de nouveaux problèmes aux communautés de la sécurité et du circuit intégré, faisant devenir la cryptologie un outil incontournable permettant de répondre aux exigences sécuritaires telles que l'identification, l'authentification ou la confidentialité. L'intégration des primitives cryptographiques dans différents dispositifs électroniques est largement répandue aujourd'hui dans le domaine des communications, des services financiers, des services gouvernementaux ou de la PayTV. Au premier rang de ces dispositifs, figure la carte à puce. D'après un rapport publié en août 2010, IMS Research prévoit que le marché de la carte à puce atteindra les 5.8 milliards d'unités vendues en fin d'année. La grande majorité est utilisée dans les télécommunications (carte SIM) et les services bancaires. La carte à puce incorpore un circuit intégré qui peut être, soit un processeur dédié aux calculs cryptographiques, soit seulement de la mémoire non-volatile ou les deux. Ces circuits intégrés manipulent et contiennent donc des secrets comme les clefs secrètes ou privées utilisées par les algorithmes de cryptographie symétriques ou asymétriques. Ces clefs doivent donc, rester absolument confidentielles et intègres afin de garantir la chaîne de sécurité. Par conséquent la robustesse des cartes à puces aux attaques cryptographiques est cruciale. En effet, les attaques sur les circuits intégrés sont aujourd'hui très performantes. Elles peuvent être classées selon trois grandes familles : invasives, semi-invasives et non-invasives. 1- Les attaques invasives sont des attaques menées en général par des experts et requièrent du matériel spécifique. 2- Les attaques semi-invasives, famille d'attaques récemment introduite par l'équipe de Ross Anderson, dont le principe est de décapsuler le package contenant le circuit, afin de se positionner le plus proche possible de la surface, sans pour autant en détériorer les fonctionnalités. 3- Les attaques non-invasives ne nécessitent aucune préparation préalable du dispositif soumis aux attaques. Elles consistent à espionner les phénomènes physiques engendrés par la manipulation des données et notamment les clefs secrètes. Les attaques non-invasives peuvent être considérées comme les plus dangereuses, dans la mesure où ce type d'attaque peut être réalisé sans contact avec le circuit. En effet, pendant l'utilisation d'appareils électroniques, les circuits qui les composent sont soumis à des variations de courant et de tension. Ces variations génèrent des ondes électromagnétiques qui se propagent dans le voisinage du circuit. Ces émanations présentent une corrélation avec des informations censées être stockées dans la puce de façon sécurisée (exemple: la clef secrète d'une carte bancaire utilisée pour l'authentification). Plusieurs attaques dites par canaux auxiliaires, et basées sur ces fuites électromagnétiques ont été publiées par la communauté scientifique ces dernières années. Cette thèse a pour objectifs: (a) comprendre les différentes sources des émanations électromagnétiques des circuits intégrés, et de proposer un flot d'attaque électromagnétique localisée et en champ proche afin de tester la robustesse d'un circuit cryptographique contre les attaques et analyses utilisant le canal électromagnétique, et (b) proposer des contre-mesures afin de contrecarrer ces attaques par analyse de champ électromagnétique. Afin d'atteindre ces objectifs, nous présentons, dans un premier temps, une technique efficace nommée WGMSI (Weighted Global Magnitude Squared Incoherence) pour localiser les positions, au-dessus du circuit cryptographique, qui génèrent les émanations électromagnétiques les plus dépendantes des données secrètes. Dans un deuxième temps la WGMSI est utilisée aussi pour améliorer la stabilité et la convergence des différentes attaques électromagnétiques proposées dans la littérature. La suite de la thèse décrit les différentes contre-mesures aux attaques par canaux auxiliaires. En effet, face à ces techniques d'attaques évoluées, il est primordial, de rendre les fonctions cryptographiques implantées dans les circuits intégrés pour la sécurité (confidentialité, authentification, intégrité ... ), inattaquables en un temps raisonnable et ceci même en manipulant des sous-clefs dans des chiffrements par blocs. Pour cela, on se focalisera principalement aux contre-mesures basées sur des logiques différentielles et dynamiques. Ces contre-mesures sont dites par conception, puisqu'elles se situent au niveau des portes logiques qui sont considérées comme les éléments de base pour la conception d'un circuit intégré. Ceci permet une certaine indépendance des algorithmes cryptographiques vis à vis de l'architecture ou de la technologie considérées. Parmi les différentes logiques différentielles et dynamiques, on s'intéressera plus spécifiquement à la logique STTL (Secure Triple Track logic) qui peut être considérée comme une amélioration de la logique double rail, dans la mesure où un troisième rail est ajouté afin de contrecarrer la faiblesse principale de la logique double rail, à savoir l'évaluation anticipée. Enfin, nous présenterons un flot d'implémentation sur FPGA de la logique STTL prouvée robuste aux attaques par analyse de courant, et nous implémenterons un prototype de DES STTL afin de tester sa robustesse aux attaques électromagnétiques localisées en champ procheThe integration of cryptographic primitives in different electronic devices is widely used today incommunications, financial services, government services or PayTV.Foremost among these devices include the smart card. According to a report published in August 2010, IMS Research forecasts that the smart card market will reach 5.8 billion units sold in this year. The vast majority is used in telecommunications (SIM) and banking.The smart card incorporates an integrated circuit which can be a dedicated processor for cryptographic calculations. Therefore, these integrated circuits contain secrets such as secret or private keys used by the symmetric or asymmetric cryptographic algorithms. These keys must remain absolutely confidential to ensure the safety chain.Therefore the robustness of smart cards against attacks is crucial. These attacks can be classifiedinto three main categories: invasive, semi-invasive and non-invasive.Non-invasive attacks can be considered the most dangerous, since this kind of attack can be achieved without any contact with the circuit.Indeed, while using electronic circuits that compose them are subjected to variations in current and voltage. These variations generate an electromagnetic radiation propagating in the vicinity of the circuit.These radiations are correlated with secret information (eg a secret key used for authentication). Several attacks based on these leakages were published by the scientific community.This thesis aims to: (a) understand the different sources of electromagnetic emanations of integrated circuits, and propose a localized near field attack to test the robustness of a cryptographic circuit and (b) propose counter-measures to these attacks
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Gomina, Kamil. "Méthodologie et développement de solutions pour la sécurisation des circuits numériques face aux attaques en tensions". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0751.
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Les applications grand public comme la téléphonie mobile ou les cartes bancaires manipulent des données confidentielles. A ce titre, les circuits qui les composent font de plus en plus l'objet d'attaques qui présentent des menaces pour la sécurité des données. Les concepteurs de systèmes sur puce (SoC) doivent donc proposer des solutions sécurisées, tout en limitant le coût et la complexité globale des applications. L’analyse des attaques existantes sur les circuits numériques nous a orienté vers celles se basant sur la tension d'alimentation, dans des nœuds technologiques avancés.Dans un premier temps, nous avons déterminé la signature électrique d’un circuit en phase de conception. Pour cela, un modèle électrique a été proposé, prenant en compte la consommation en courant et la capacité de la grille d'alimentation. L'extraction de ces paramètres ainsi que l'évaluation du modèle sont présentées. L’utilisation de ce modèle a permis de mesurer la vulnérabilité d’un circuit mais aussi d’évaluer quantitativement des contremesures, notamment celle utilisant des capacités de découplage. Ensuite, l’étude se consacre à l’injection de fautes par impulsions de tension d’alimentation. Les mécanismes d’injection de fautes sur des circuits numériques ont été étudiés. Dès lors, des solutions de détection d’attaques ont été proposées et évaluées à la fois en simulation et par des tests électriques sur circuit. Les résultats ont permis de confirmer les analyses théoriques et la méthodologie utilisée.Ce travail a ainsi montré la faisabilité de solutions à bas coût contre les attaques actives et passives en tension, utilisables dans le cadre d’un développement industriel de produitsGeneral use products as mobile phones or smartcards manipulate confidential data. As such, the circuits composing them are more and more prone to physical attacks, which involve a threat for their security. As a result, SoC designers have to develop efficient countermeasures without increasing overall cost and complexity of the final application. The analysis of existing attacks on digital circuits leads to consider power attacks, in advanced technology nodes.First of all, the power signature of a circuit was determined at design time. To do so, an electrical model was suggested based on the current consumption and the overall power grid capacitance. The methodology to extract these parameters, as well as the evaluation of the model are presented. This model allows designers to anticipate information leakage at design time and to quantify the protection of countermeasures, as the use of integrated decoupling capacitors. Then, the study was dedicated to power glitch attacks. The different fault injection mechanisms were analyzed in details. From then on, a set of detection circuits were suggested and evaluated at design time and on silicon by electrical tests. Both the theoretical analysis and the given methodology were confirmed by the test campaigns.This work demonstrated that the design of low-cost solutions against passive and active power attacks can be achieved, and used in a large scale product development
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Oliveira, Mario Orlando. "Proteção diferencial de transformadores trifásicos utilizando a transformada wavelet". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/17292.
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A qualidade e a continuidade do fornecimento de energia elétrica aos consumidores são fatores muito importantes quando da avaliação da eficiência de um sistema elétrico de potência. Nesse contexto, os transformadores são equipamentos muito importantes e demandam especial atenção quando do projeto do esquema de proteção. Apesar do crescente desenvolvimento das metodologias de proteção de transformadores trifásicos, alguns aspectos ainda não foram totalmente solucionados. Um desses diz respeito à proteção diferencial de transformadores de potência, a qual apresenta vários problemas na discriminação de faltas internas ao transformador. A geração de correntes diferenciais provocada por fenômenos transitórios, como a energização do transformador, produz a incorreta operação do relé, ocasionando uma queda na eficiência do esquema de proteção diferencial. Assim sendo, o presente trabalho apresenta uma nova metodologia de proteção diferencial de transformadores trifásicos, a qual utiliza a transformada wavelet para extrair os sinais transitórios dominantes induzidos pelas faltas internas. A transformada wavelet é uma eficiente ferramenta utilizada no estudo de sinais não-estacionários e de rápida transição. De forma a atender os principais problemas do esquema convencional de proteção, a transformada wavelet discreta é utilizada para decompor os sinais de corrente diferencial em várias faixas de freqüências. Após essa decomposição, a variação de energia espectral dos coeficientes de detalhe wavelet é analisada pelo algoritmo proposto, e assim uma discriminação entre faltas internas e correntes de magnetização, ou correntes inrush, é feita. Usando um modelo elaborado de um sistema elétrico de transmissão são efetuadas rigorosas simulações computacionais para avaliar o desempenho do algoritmo proposto. Os resultados obtidos nessas simulações mostram que a metodologia de proteção diferencial de transformadores trifásicos baseada na variação de energia espectral dos coeficientes wavelets apresenta um ótimo desempenho quando comparada com a metodologia de proteção convencional.Power supply quality and continuity are very important aspect when assessing the efficiency of an electric power system. In this context, the transformers are key equipments that require special attention during the protection scheme design. Despite the increasing development of methodologies for three-phase transformers protection, some aspects have not yet been fully studied. One of these aspects concerns to the differential protection of power transformers, which presents several restrictions regarding the characterization of internal faults. The observation of differential currents caused by transient phenomena such as transformer energization, produces an incorrect operation of protective relaying, causing a drop in the protection scheme efficiency. Therefore, this work presents a new methodology for differential protection of three-phase transformers using the wavelet transform to extract the transient signals induced by the dominant internal faults. The wavelet transform is an efficient tool in the study of non-stationary signals with fast transients. In order to overcome the main problems of the traditional protection scheme, the discrete wavelet transform is used to decompose the differential current signals into several bands of frequencies. After this decomposition, the spectral energy variation of the wavelet detail coefficients is analyzed by the proposed algorithm and, thus, classification between internal faults, external faults and inrush currents is performed. Using a transmission system model, accurate simulations are performed to evaluate the computational performance of the proposed protection algorithm. The results obtained in these simulations show that the proposed methodology has a great performance when compared with traditional protection philosophies.
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Mazumder, Sudip K. "Nonlinear Analysis and Control of Standalone, Parallel DC-DC, and Parallel Multi-Phase PWM Converters". Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/28690.
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Applications of distributed-power systems are on the rise. They are already used in telecommunication power supplies, aircraft and shipboard power-distribution systems, motor drives, plasma applications, and they are being considered for numerous other applications. The successful operation of these multi-converter systems relies heavily on a stable design. Conventional analyses of power converters are based on averaged models, which ignore the fast-scale instability and analyze the stability on a reduced-order manifold. As such, validity of the averaged models varies with the switching frequency even for the same topological structure.
The prevalent procedure for analyzing the stability of switching converters is based on linearized smooth averaged (small-signal) models. Yet there are systems (in active use) that yield a non-smooth averaged model. Even for systems for which smooth averaged models are realizable, small-signal analyses of the nominal solution/orbit do not provide anything about three important characteristics: region of attraction of the nominal solution, dependence of the converter dynamics on the initial conditions of the states, and the post-instability dynamics. As such, converters designed based on small-signal analyses may be conservative. In addition, linear controllers based on such analysis may not be robust and optimal. Clearly, there is a need to analyze the stability of power converters from a different perspective and design nonlinear controllers for such hybrid systems.
In this Dissertation, using bifurcation analysis and Lyapunov's method, we analyze the stability and dynamics of some of the building blocks of distributed-power systems, namely standalone, integrated, and parallel converters. Using analytical and experimental results, we show some of the differences between the conventional and new approaches for stability analyses of switching converters and demonstrate the shortcomings of some of the existing results. Furthermore, using nonlinear analyses we attempt to answer three fundamental questions: when does an instability occur, what is the mechanism of the instability, and what happens after the instability?
Subsequently, we develop nonlinear controllers to stabilize parallel dc-dc and parallel multi-phase converters. The proposed controllers for parallel dc-dc converters combine the concepts of multiple-sliding-surface and integral-variable-structure control. They are easy to design, robust, and have good transient and steady-state performances. Furthermore, they achieve a constant switching frequency within the boundary layer and hence can be operated in interleaving or synchronicity modes. The controllers developed for parallel multi-phase converters retain many of the above features. In addition, they do not require any communication between the modules; as such, they have high redundancy. One of these control schemes combines space-vector modulation and variable-structure control. It achieves constant switching frequency within the boundary layer and a good compromise between the transient and steady-state performances.Ph. D.
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Sommer, Andrew Patrick. "VIBRATION-BASED HEALTH MONITORING OF MULTIPLE-STAGE GEAR TRAIN AND DIFFERENTIAL PLANETARY TRANSMISSION INVOLVING TEETH DAMAGE AND BACKLASH NONLINEARITY". DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/631.
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The objective of this thesis is to develop vibration-based fault detection strategies for on-line condition monitoring of gear transmission systems. The study divides the thesis into three sections. First of all, the local stresses created by a root fatigue crack on a pinion spur gear are analyzed using a quasi-static finite element model and non-linear contact mechanics simulation. Backlash between gear teeth which is essential to provide better lubrication on tooth surfaces and to eliminate interference is included as a defect and a necessary part of transmission design. The second section is dedicated to fixed axis power trains. Torsional vibration is shown to cause teeth separation and double-sided impacts in unloaded and lightly loaded gearing drives. The transient and steady-state dynamic loading on teeth within a two stage crank-slider mechanism arising from backlash and geometric manufacturing errors is investigated by utilizing a non-linear multi-body dynamics software model. The multi-body model drastically reduces the computation time required by finite element methods to simulate realistic operation. The gears are considered rigid with elastic contact surfaces defined by a penalty based non-linear contact formulation. The third section examines a practical differential planetary transmission which combines two inputs and one output. Planetary gears with only backlash errors are compared to those containing both backlash and tooth defects under different kinematic and loading conditions. Fast Fourier Transform (FFT) analysis shows the appearance of side band modulations and harmonics of the gear mesh frequency. A joint time-frequency analysis (JTFA) during start-up reveals the unique vibration patterns for fixed axis gear train and differential planetary gear, respectively, when the contact forces increase during acceleration.
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Nejadmalayeri, Amir Hossein. "CDMA Channel Selection Using Switched Capacitor Technique". Thesis, University of Waterloo, 2001. http://hdl.handle.net/10012/782.
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CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.
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Ghaweta, Ahmad. "OPTIMAL DISTRIBUTION FEEDER RECONFIGURATION WITH DISTRIBUTED GENERATION USING INTELLIGENT TECHNIQUES". UKnowledge, 2019. https://uknowledge.uky.edu/ece_etds/134.
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Feeder reconfiguration is performed by changing the open/close status of two types of switches: normally open tie switches and normally closed sectionalizing switches. A whole feeder or part of a feeder may be served from another feeder by closing a tie switch linking the two while an appropriate sectionalizing switch must be opened to maintain the radial structure of the system. Feeder reconfiguration is mainly aiming to reduce the system overall power losses and improve voltage profile. In this dissertation, several approaches have been proposed to reconfigure the radial distribution networks including the potential impact of integrating Distributed Energy Resources (DER) into the grid. These approaches provide a Fast-Genetic Algorithm “FGA” in which the size and convergence speed is improved compared to the conventional genetic algorithm. The size of the population matrix is also smaller because of the simple way of constructing the meshed network.
Additionally, FGA deals with integer variable instead of a binary one, which makes FGA a unique method. The number of the mesh/loop is based on the number of tie switches in a particular network. The validity of the proposed FGA is investigated by comparing the obtained results with the one obtained from the most recent approaches. The second the approach is the implementation of the Differential Evolution (DE) algorithm. DE is a population-based method using three operators including crossover, mutation, and selection. It differs from GA in that genetic algorithms rely on crossover while DE relies on mutation. Mutation is based on the differences between randomly sampled pairs of solutions in the population. DE has three advantages: the ability to find the global optimal result regardless of the initial values, fast convergence, and requirement of a few control parameters. DE is a well-known and straightforward population-based probabilistic approach for comprehensive optimization.
In distribution systems, if a utility company has the right to control the location and size of distributed generations, then the location and size of DGs may be determined based on some optimization methods. This research provides a promising approach to finding the optimal size and location of the planned DER units using the proposed DE algorithm. DGs location is obtained using the sensitivity of power losses with respect to real power injection at each bus. Then the most sensitive bus is selected for installing the DG unit. Because the integration of the DG adds positive real power injections, the optimal location is the one with the most negative sensitivity in order to get the largest power loss reduction. Finally, after the location is specified, the proposed Differential Evolution Algorithm (DEA) is used to obtain the optimal size of the DG unit. Only the feasible solutions that satisfy all the constraints are considered.
The objective of installing DG units to the distribution network is to reduce the system losses and enhance the network voltage profile. Nowadays, these renewable DGs are required to equip with reactive power devices (such as static VAR compensators, capacitor banks, etc.), to provide reactive power as well as to control the voltage at their terminal bus. DGs have various technical benefits such as voltage profile improvement, relief in feeder loading, power loss minimization, stability improvement, and voltage deviation mitigation. The distributed generation may not achieve its full potential of benefits if placed at any random location in the system. It is necessary to investigate and determine the optimum location and size of the DG. Most distribution networks are radial in nature with limited short-circuit capacity. Therefore, there is a limit to which power can be injected into the distribution network without compromising the power quality and the system stability. This research is aiming to investigate this by applying DG technologies to the grid and keeping the system voltage within a defined boundary [0.95 - 1.05 p.u]. The requirements specified in IEEE Standard 1547 are considered.
This research considers four objectives related to minimization of the system power loss, minimization of the deviations of the nodes voltage, minimization of branch current constraint violation, and minimization of feeder’s currents imbalance. The research formulates the problem as a multi-objective problem. The effectiveness of the proposed methods is demonstrated on different revised IEEE test systems including 16 and 33-bus radial distribution system.
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Le, Bouder Hélène. "UN FORMALISME UNIFIANT LES ATTAQUES PHYSIQUES SUR CIRCUITS CRYTOGRAPHIQUES ET SON EXPLOITATION AFIN DE COMPARER ET RECHERCHER DE NOUVELLES ATTAQUES". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0759/document.
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Cette thèse se situe dans la cryptanalyse physique des algorithmes de chiffrement par blocs. Un algorithme cryptographique est conçu pour être mathématiquement robuste. Cependant, une fois implémenté dans un circuit, il est possible d'attaquer les failles de ce dernier. Par opposition à la cryptanalyse classique, on parle alors d'attaques physiques. Celles-ci ne permettent pas d'attaquer l'algorithme en soi, mais son implémentation matérielle. Il existe deux grandes familles d'attaques physiques différentes : les attaques par observation du circuit durant le chiffrement, et les attaques par injections de fautes, qui analysent l'effet d'une perturbation intentionnelle sur le fonctionnement du circuit. Les attaques physiques ont deux types d'objectifs : rechercher la clé ou faire de la rétro-conception (retrouver une partie d'un algorithme de chiffrement privé, ex : s-boxes modifiées). Bien que leurs principes semblent distincts, cette thèse présente un formalisme qui permet d'unifier toutes ces attaques. L'idée est de décrire les attaques physiques de façon similaire, afin de pouvoir les comparer. De plus, ce formalisme a permis de mettre en évidence de nouvelles attaques. Des travaux novateurs ayant pour objet de retrouver la clé de chiffrement d'un AES, uniquement avec la consommation de courant ont été menés. Une nouvelle attaque de type FIRE (Fault Injection for Reverse Engineering) pour retrouver les s-boxes d'un pseudo DES est également présentée dans la thèse. Ce travail a abouti sur une réflexion plus générale, sur les attaques par injections de fautes dans les schémas de Feistel classiques et généralisésThe main subject of this work is the physical cryptanalysis of blocks ciphers. Even if cryptographic algorithms are properly designed mathematically, they may be vulnerable to physical attacks. Physical attacks are mainly divided in two families: the side channel attacks which are based on the observation of the circuit behaviour during the computation, and the fault injection attacks which consist in disturbing the computation in order to alter the correct progress of the algorithm. These attacks are used to target the cipher key or to reverse engineer the algorithm. A formalism is proposed in order to describe the two families in a unified way. Unifying the different attacks under a same formalism allows to deal with them with common mathematical tools. Additionally, it allows a comparison between different attacks. Using this framework, a generic method to assess the vulnerabilities of generalized Feistel networks to differential fault analysis is presented. This work is furthermore extended to improve a FIRE attack on DES-like cryptosystems with customized s-boxes
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Richmond, Tania. "Implantation sécurisée de protocoles cryptographiques basés sur les codes correcteurs d'erreurs". Thesis, Lyon, 2016. http://www.theses.fr/2016LYSES048/document.
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Le premier protocole cryptographique basé sur les codes correcteurs d'erreurs a été proposé en 1978 par Robert McEliece. La cryptographie basée sur les codes est dite post-quantique car il n'existe pas à l'heure actuelle d'algorithme capable d'attaquer ce type de protocoles en temps polynomial, même en utilisant un ordinateur quantique, contrairement aux protocoles basés sur des problèmes de théorie des nombres. Toutefois, la sécurité du cryptosystème de McEliece ne repose pas uniquement sur des problèmes mathématiques. L'implantation, logicielle ou matérielle, a également un rôle très important pour sa sécurité et l'étude de celle-ci face aux attaques par canaux auxiliaires/cachés n'a débuté qu'en 2008. Des améliorations sont encore possibles. Dans cette thèse, nous proposons de nouvelles attaques sur le déchiffrement du cryptosystème de McEliece, utilisé avec les codes de Goppa classiques, ainsi que des contre-mesures correspondantes. Les attaques proposées sont des analyses de temps d'exécution ou de consommation d'énergie. Les contre-mesures associées reposent sur des propriétés mathématiques et algorithmiques. Nous montrons qu'il est essentiel de sécuriser l'algorithme de déchiffrement en le considérant dans son ensemble et non pas seulement étape par étapeThe first cryptographic protocol based on error-correcting codes was proposed in 1978 by Robert McEliece. Cryptography based on codes is called post-quantum because until now, no algorithm able to attack this kind of protocols in polynomial time, even using a quantum computer, has been proposed. This is in contrast with protocols based on number theory problems like factorization of large numbers, for which efficient Shor's algorithm can be used on quantum computers. Nevertheless, the McEliece cryptosystem security is based not only on mathematical problems. Implementation (in software or hardware) is also very important for its security. Study of side-channel attacks against the McEliece cryptosystem have begun in 2008. Improvements can still be done. In this thesis, we propose new attacks against decryption in the McEliece cryptosystem, used with classical Goppa codes, including corresponding countermeasures. Proposed attacks are based on evaluation of execution time of the algorithm or its power consumption analysis. Associate countermeasures are based on mathematical and algorithmic properties of the underlying algorithm. We show that it is necessary to secure the decryption algorithm by considering it as a whole and not only step by step