Bibliografias temáticas / SoC (System-on-Chip)

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Literatura científica selecionada sobre o tema "SoC (System-on-Chip)"

Autor: Grafiati
Publicado: 4 de junho de 2021
Última modificação: 26 de julho de 2025

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Artigos de revistas sobre o assunto "SoC (System-on-Chip)"

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Mr., Abhijit Patil, and A. A. Shirolkar Mr. "A Review on System on Chip SoC Designs for Real Time Industrial Application." International Journal of Trend in Scientific Research and Development 2, no. 1 (2017): 1534–37. https://doi.org/10.31142/ijtsrd7077.

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Now a days System on a chip SoC technology is used in small, increasingly complex consumer electronic devices. A system on a chip SoC is a microchip with all the necessary electronic circuits and parts for a given system, such as a Smartphone or wearable computer, on a single integrated circuit IC . Day by day the scope and use of the electronics concepts in industrial field is increasing step by step. In this paper the review of newly developed concepts is done for the SoC design for real time industrial application. This paper also reviews a power and area efficient for industrial applicatio
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Sagar, G. Venkataramana, and Dr K. Srinivasa Rao. "Reconfigurable FFT System on Chip (SOC)." International Journal of Computer Applications 11, no. 5 (2010): 35–38. http://dx.doi.org/10.5120/1575-2107.

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Jia, Hao, Shanglin Yang, Ting Zhou, et al. "WDM-compatible multimode optical switching system-on-chip." Nanophotonics 8, no. 5 (2019): 889–98. http://dx.doi.org/10.1515/nanoph-2019-0005.

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AbstractThe development of optical interconnect techniques greatly expands the communication bandwidth and decreases the power consumption at the same time. It provides a prospective solution for both intra-chip and inter-chip links. Herein reported is an integrated wavelength-division multiplexing (WDM)-compatible multimode optical switching system-on-chip (SoC) for large-capacity optical switching among processors. The interfaces for the input and output of the processor signals are electrical, and the on-chip data transmission and switching process are optical. It includes silicon-based mic
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Geethanjali, N., and K.R Rekha. "Design and Implementation of a Efficient Router using X Y Algorithm." Indian Journal of Data Communication and Networking (IJDCN) 1, no. 3 (2021): 5–9. https://doi.org/10.54105/ijdcn.B5009.061321.

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The engineering for on chip network configuration utilizing dynamic reconfiguration is an answer for Communication Interfaces, Chip cost, Quality of Service, ensure adaptability of the organization. The proposed engineering powerfully arrange itself concerning Hardware Modules like switches, Switch based packet , information to a packet size with changing the correspondence situation and its prerequisites on run time. The NOC Architecture assumes urgent part while planning correspondence frameworks intended for SOC. The NOC engineering be better over traditional transport, mutual transport pla
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Ashutosh, Dhar Dwivedi. "A Comprehensive Study of Network on Chip and System on Chip in Perspective of Internet of Things." International Journal of Engineering Sciences & Emerging Technologies 11, no. 2 (2023): 337–49. https://doi.org/10.5281/zenodo.11382807.

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<em>Network on Chip (NoC) and System on Chip (SoC) are both important technologies used in various fields, including embedded systems, high-performance computing, and Internet of Things (IoT). NoC is used to provide a communication infrastructure for systems that integrate multiple components, such as processing units, memory, and peripherals, onto a single chip or across multiple chips. NoC can improve the scalability, performance, and energy efficiency of such systems by providing a high-bandwidth, low-latency communication channel between the components. SoC is used to integrate multiple co
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Liu, Xiang Wen, and Li Min Liu. "The IP Design for a Customized Mobile SoC." Advanced Materials Research 605-607 (December 2012): 2087–90. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2087.

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IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.
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DOERING, ROBERT R. "System-on-Chip Integration." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 325–32. http://dx.doi.org/10.1142/s0129156402001289.

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Numerous "signal-processing products" are now driving the semiconductor market for SOC solutions enabling real-time performance, low-cost, low-power, portability, etc. A primary limit on the types of electronic (or other) functions that will be integrated into future SOCs is cost of integration, which tends to grow non-linearly with process complexity and chip area. A near-continuum of System-on/in-X solutions is emerging between traditional System-on-Chip and System-on-Board. These approaches span the tradeoff between bandwidth and cost. For the foreseeable future, digital CMOS will continue
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Budiarto, Rahmat, Lelyzar Siregar, and Deris Stiawan. "Network-on-Chip Paradigm for System-on-Chip Communication." Computer Engineering and Applications Journal 6, no. 1 (2017): 1–4. http://dx.doi.org/10.18495/comengapp.v6i1.186.

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Developments of modern technologies in electronics, such as communication, Internet, pervasive and ubiquitous computing and ambient intelligence have figured largely our life. In our day micro-electronic products inspire the ways of learning, communication and entertainment. These products such as laptop computer, mobile phones, and personal handheld sets are becoming faster, lighter in weight, smaller in size, larger in capacity, lower in power consumptions, cheaper and functionally enhanced. This trend will persistently continue. Following this trend, we could integrate more and more complex
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R., Dorothy, and T. Sasilatha. "System on Chip Based RTC in Power Electronics." Bulletin of Electrical Engineering and Informatics 6, no. 4 (2017): 358–63. https://doi.org/10.11591/eei.v6i4.867.

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Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-theLoop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal c
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Chitti, Sridevi, P. Chandrasekhar, and M. Asharani. "A Unique Test Bench for Various System-on-a-Chip." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3318. http://dx.doi.org/10.11591/ijece.v7i6.pp3318-3322.

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This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a genera
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Teses / dissertações sobre o assunto "SoC (System-on-Chip)"

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Gonciari, Paul Theo. "Low cost test for core-based system-on-a-chip." Thesis, University of Southampton, 2003. https://eprints.soton.ac.uk/257354/.

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The availability of high level integration leads to building of millions of gates systemson- a-chip (SOC). Due to the high complexity of SOCs, testing them is becoming increasingly difficult. In addition, if the current test practises are maintained, the high cost of test will lead to a considerable production cost increase. To alleviate the test cost problem, this research investigates methods which lead to low-cost test of core-based systems-on-a-chip based on test resource partitioning and without changing the embedded cores. Analysing the factors which drive the continuous increase in test
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Zhao, Wei. "Digital Surveillance Based on Video CODEC System-on-a-Chip (SoC) Platforms." FIU Digital Commons, 2010. http://digitalcommons.fiu.edu/etd/334.

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Today, most conventional surveillance networks are based on analog system, which has a lot of constraints like manpower and high-bandwidth requirements. It becomes the barrier for today’s surveillance network development. This dissertation describes a digital surveillance network architecture based on the H.264 coding/decoding (CODEC) System-on-a-Chip (SoC) platform. The proposed digital surveillance network architecture includes three major layers: software layer, hardware layer, and the network layer. The following outlines the contributions to the proposed digital surveillance network archi
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Yabarrena, Jean Mimar Santa Cruz. "Tecnologias system on chip e CAN em sistemas de controle distribuído." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/18/18149/tde-31072006-203757/.

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Sistemas de controle precisam trabalhar com restrições temporais rigorosas para garantir seu correto funcionamento, sendo por isso considerados sistemas de tempo-real. Quando tais sistemas são distribuídos, as redes de sensores, atuadores e controladores estão interligados em geral, por redes de campo. Nesse contexto, as redes de campo desempenham um papel extremamente importante no comportamento global do sistema. O presente trabalho de pesquisa apresenta a descrição do processo de desenvolvimento de um system on-chip (SoC) para um sistema de controle. Diferentemente das abordagens clássicas,
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Lu, Jian. "Embedded Magnetics for Power System on Chip (PSoC)." Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2993.

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A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed, offering a cost effective approach to realize power systems on chip (PSoC) or System-in-Package (PSiP). The concept has been investigated both experimentally and with finite element modeling. Improvement in total inductance is demonstrated for multi-turn bondwire inductors over single bondwire inductors. The inductance and Q factor can be further boosted with coupled multi-turn inductor concept. Transformer parameters including self- and mutual inductance, and coupling factors are extrac
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Flórez, Martha Johanna Sepúlveda. "Estimativa de desempenho de uma NoC a partir de seu modelo em SYSTEMC-TLM." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-152854/.

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The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that e
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Aulagnier, Guillaume. "Optimisation de convertisseurs DC-DC SoC (System on Chip) pour l'automobile." Phd thesis, Toulouse, INPT, 2015. http://oatao.univ-toulouse.fr/19512/1/AULAGNIER_Guillaume.pdf.

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L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électr
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Dias, Marcelo Mallmann. "Plataforma para injeção de falhas em System-on-Chip (SOC)." Pontifícia Universidade Católica do Rio Grande do Sul, 2011. http://hdl.handle.net/10923/3178.

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Made available in DSpace on 2013-08-07T18:53:18Z (GMT). No. of bitstreams: 1 000434259-Texto+Completo-0.pdf: 861644 bytes, checksum: a1d7d01d86f05de127324b3bd5e5c832 (MD5) Previous issue date: 2011<br>The increasing number of embedded computer systems being used in several segments of our society, from simple consumer products to safety critical applications, has intensified the study and development of new test methodologies and fault tolerance techniques capable of assuring the high reliability expected from those systems. Fault injection represents an extremely efficient way of the test a
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Adhipathi, Pradeep. "Model based approach to Hardware/ Software Partitioning of SOC Designs." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9986.

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As the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other components and, in turn, the performance of the system. This has led to an integrated design approach known as hardware/software co-design and co-verification. The conventional techniques for co-design favor partitioning the system into hardware and software components at an early stage o
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Dias, Marcelo Mallmann. "Plataforma para inje??o de falhas em System-on-Chip (SOC)." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2009. http://tede2.pucrs.br/tede2/handle/tede/3036.

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Made available in DSpace on 2015-04-14T13:56:21Z (GMT). No. of bitstreams: 1 434259.pdf: 861644 bytes, checksum: a1d7d01d86f05de127324b3bd5e5c832 (MD5) Previous issue date: 2009-08-31<br>O aumento do n?mero de sistemas computacionais embarcados sendo utilizados em diversos segmentos de nossa sociedade, de simples bens de consumo at? aplica??es cr?ticas, intensificou o desenvolvimento de novas metodologias de teste e t?cnicas de toler?ncia a falhas capazes de garantir o grau de confiabilidade esperado os mesmos. A inje??o de falhas representa uma solu??o extremamente eficaz de avaliar metodol
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Avnit, Karin Computer Science &amp Engineering Faculty of Engineering UNSW. "Provably correct on-chip communication: a formal approach to automatic synthesis of SoC protocol converters." Awarded By:University of New South Wales. Computer Science & Engineering, 2010. http://handle.unsw.edu.au/1959.4/44701.

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The field of chip design is characterized by contradictory pressures to reduce time-to-market and maintain a high level of reliability. As a result, module reuse has become common practice in chip design. To save time on both design and verification, Systems-on-Chips (SoCs) are composed using pre-designed and pre-verified modules. The integrated modules are often designed by different groups and for different purposes, and are later integrated into a single chip. In the absence of a single interface standard for such modules, "plug-n-play" style integration is not likely, as the subject module
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Livros sobre o assunto "SoC (System-on-Chip)"

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. System on Chip (SOC) Architecture. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2.

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Chakravarthi, Veena S. A Practical Approach to VLSI System on Chip (SoC) Design. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-23049-4.

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Chakravarthi, Veena S. A Practical Approach to VLSI System on Chip (SoC) Design. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-18363-8.

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Madisetti, Vijay K. A platform-centric approach to system-on-chip (SOC) design. Springer, 2005.

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Madisetti, V. A platform-centric approach to system-on-chip (SOC) design. Springer, 2010.

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Chonlameth, Arpnikanondt, ed. A platform-centric approach to system-on-chip (SoC) design. Springer, 2005.

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Burg, Andreas, Ayṣe Coṣkun, Matthew Guthaus, Srinivas Katkoori, and Ricardo Reis, eds. VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0.

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Chakrabarty, Krishnendu, ed. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6527-4.

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Chakrabarty, Krishnendu. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. Springer US, 2002.

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Krishnendu, Chakrabarty, ed. SOC (System-on-a-Chip) testing for plug and play test automation. Kluwer Academic Publishers, 2002.

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Capítulos de livros sobre o assunto "SoC (System-on-Chip)"

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "SOC Software." In System on Chip (SOC) Architecture. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_8.

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Farahmandi, Farimah, Yuanwen Huang, and Prabhat Mishra. "SoC Security Verification Challenges." In System-on-Chip Security. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30596-3_2.

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Dongarra, Jack, Piotr Luszczek, Felix Wolf, et al. "System on Chip (SoC)." In Encyclopedia of Parallel Computing. Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_2101.

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Dongarra, Jack, Piotr Luszczek, Felix Wolf, et al. "SoC (System on Chip)." In Encyclopedia of Parallel Computing. Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_5.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "SOC Advanced Architectures." In System on Chip (SOC) Architecture. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_9.

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Farahmandi, Farimah, Yuanwen Huang, and Prabhat Mishra. "SoC Trust Metrics and Benchmarks." In System-on-Chip Security. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30596-3_3.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "System on Chips (SOC)." In System on Chip (SOC) Architecture. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_2.

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Farahmandi, Farimah, Yuanwen Huang, and Prabhat Mishra. "SoC Security Verification Using Property Checking." In System-on-Chip Security. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30596-3_7.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "IOT SOC Architecture Definition." In System on Chip (SOC) Architecture. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_7.

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Chakravarthi, Veena S., and Shivananda R. Koteshwar. "System on Chip (SOC) Architecture." In System on Chip (SOC) Architecture. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-36242-2_3.

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Trabalhos de conferências sobre o assunto "SoC (System-on-Chip)"

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Leong, Wai Yie, Yuan Zhi Leong, and Wai San Leong. "System-on-Chip (SoC) Medicine." In 2024 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition (iWEM). IEEE, 2024. http://dx.doi.org/10.1109/iwem59914.2024.10649387.

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Heinz, Carsten, and Andreas Koch. "COSSEA: Context-based SoC Security Enforcement Architecture." In 2024 IEEE 37th International System-on-Chip Conference (SOCC). IEEE, 2024. http://dx.doi.org/10.1109/socc62300.2024.10737786.

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Yayla, Mikail, Clifford Leon Dmello, Georg Ellguth, et al. "EdgeVision SoC: PPA-Impact of RTL-level Modifications." In 2024 IEEE 37th International System-on-Chip Conference (SOCC). IEEE, 2024. http://dx.doi.org/10.1109/socc62300.2024.10737776.

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Kaxiras, Stefanos, and Alberto Ros. "Efficient, snoopless, System-on-Chip coherence." In 2012 IEEE 25th International SOC Conference (SOCC). IEEE, 2012. http://dx.doi.org/10.1109/socc.2012.6398353.

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Furber, S., and J. Bainbridge. "Future Trends in SoC Interconnect." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595673.

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Isomaki, P., and N. Avessta. "Rapid Refinable SoC SDR Design." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595659.

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Nigussie, E., J. Plosila, and J. Isoaho. "Reliable Asynchronous Links for SoC." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595660.

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Rogin, Frank, Rolf Drechsler, and Steffen Rulke. "Automatic debugging of System-on-a-Chip designs." In 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398027.

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Ho, Chun Hok, Wayne Luk, Jakub M. Szefer, and Ruby B. Lee. "Tuning instruction customisation for reconfigurable system-on-chip." In 2009 IEEE International SOC Conference (SOCC). IEEE, 2009. http://dx.doi.org/10.1109/soccon.2009.5398096.

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"SOC 2011: Advanced program." In 2011 International Symposium on System-on-Chip - SOC. IEEE, 2011. http://dx.doi.org/10.1109/issoc.2011.6089215.

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