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Zeitschriftenartikel zum Thema „Memory transistor“

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Veröffentlicht am 25. Mai 2024

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1

Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, et al. "Copper atomic-scale transistors." Beilstein Journal of Nanotechnology 8 (March 1, 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.

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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of th

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Choi, Young Jin, Jihyun Kim, Min Je Kim, et al. "Hysteresis Behavior of the Donor–Acceptor-Type Ambipolar Semiconductor for Non-Volatile Memory Applications." Micromachines 12, no. 3 (2021): 301. http://dx.doi.org/10.3390/mi12030301.

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Donor–acceptor-type organic semiconductor molecules are of great interest for potential organic field-effect transistor applications with ambipolar characteristics and non-volatile memory applications. Here, we synthesized an organic semiconductor, PDPPT-TT, and directly utilized it in both field-effect transistor and non-volatile memory applications. As-synthesized PDPPT-TT was simply spin-coated on a substrate for the device fabrications. The PDPPT-TT based field-effect transistor showed ambipolar electrical transfer characteristics. Furthermore, a gold nanoparticle-embedded dielectric layer

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3

Kim, Woojo, Jimin Kwon, and Sungjune Jung. "3D Integration of Flexible and Printed Electronics: Integrated Circuits, Memories, and Sensors." Journal of Flexible and Printed Electronics 2, no. 2 (2023): 199–210. http://dx.doi.org/10.56767/jfpe.2023.2.2.199.

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Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix

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Kim, Ji-Hun, Hyeon-Jun Kim, Ki-Jun Kim, Tae-Hun Shim, Jin-Pyo Hong, and Jea-gun Park. "3-Terminal Igzo FET Based 2T0C DRAM Combined Bit-Line Structure." ECS Meeting Abstracts MA2023-02, no. 30 (2023): 1561. http://dx.doi.org/10.1149/ma2023-02301561mtgabs.

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The IGZO (InGaZnO)-based two-transistor zero-capacitor(2T0C) DRAM has attracted much attention as an alternative memory to overcome the scale-down limit of current 1T1C DRAM due to its low power consumption and monolithic 3D stacking capability. In particular, its low power consumption and the feasibility of low temperature process make it highly implementable for 3D DRAM. For operating the 2T0C DRAM, four metal lines are necessary, i.e., write word line and write bit line (WBL) for operating write transistor (WTR), and read word line and read bit line (RBL) for operating read transistor (RTR)

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Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (2019): 643. http://dx.doi.org/10.3390/mi10100643.

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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts i

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Brtník, Bohumil. "Assembling a Formula for Current Transferring by Using a Summary Graph and Transformation Graphs." Journal of Electrical Engineering 64, no. 5 (2013): 334–36. http://dx.doi.org/10.2478/jee-2013-0050.

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Abstract This paper deals with the symbolic solution of the switched current circuits. As is described, the full graph method of the solution can be used for finding relationships expressing current transfer, too. The summa MC-graph is constructed using two-graphs method in two-phase switching. By comparing the matrix form with results of the Mason’s formula are derived relations for current transfers in all phases. There are discussed various options described transistor memory cells - with loss and lossless transistors and normal transistor current mirror. Evaluation of the graph is simplifi

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Grudanov, Oleksandr. "Stability Parameters of Register File Bit Cell with Low Power Consumption Priority." Electronics and Control Systems 3, no. 77 (2023): 40–46. http://dx.doi.org/10.18372/1990-5548.77.17963.

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This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the exi

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Fuller, Elliot J., Scott T. Keene, Armantas Melianas, et al. "Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing." Science 364, no. 6440 (2019): 570–74. http://dx.doi.org/10.1126/science.aaw5581.

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Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridgi

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Srinivasarao, B. N., and K. Chandrabhushana Rao. "Design and Analysis of Area Efficient 128 Bytes SRAM Architecture." Journal of VLSI Design and Signal Processing 8, no. 1 (2022): 19–26. http://dx.doi.org/10.46610/jovdsp.2022.v08i01.004.

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SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM

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Seo, Yeongkyo, and Kon-Woo Kwon. "Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application." Electronics 12, no. 20 (2023): 4223. http://dx.doi.org/10.3390/electronics12204223.

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This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches du

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Gul, Waqas, Maitham Shams, and Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview." Micromachines 13, no. 8 (2022): 1332. http://dx.doi.org/10.3390/mi13081332.

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Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a maj

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Li, Tingkai, Sheng Teng Hsu, Bruce D. Ulrich, and David R. Evans. "Semiconductive metal oxide ferroelectric memory transistor: A long-retention nonvolatile memory transistor." Applied Physics Letters 86, no. 12 (2005): 123513. http://dx.doi.org/10.1063/1.1886252.

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13

Cheremisinov, D. I., and L. D. Cheremisinova. "Logical gates recognition in a flat transistor circuit." Informatics 18, no. 4 (2021): 96–107. http://dx.doi.org/10.37661/1816-0301-2021-18-4-96-107.

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O b j e c t i v e s. With the increasing complexity of verification and simulation of modern VLSI, containing hundreds of millions of transistors, the means of extracting the hierarchical description at the level of logical elements froma flat description of circuits at the transistor level are becoming the main tools for computer-aided design and verification. Decompilation tools for transistor circuits can not only significantly reduce the time to perform VLSI topology check, but also provide the basis for generating test cases, logical reengineering of integrated circuits and reverse engine

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Qi, Hongxia, and Ying Wu. "Synaptic plasticity of TiO2 nanowire transistor." Microelectronics International 37, no. 3 (2020): 125–30. http://dx.doi.org/10.1108/mi-08-2019-0053.

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Purpose The emulation of synapses is essential to neuromorphic computing systems. Despite remarkable progress has been made in the two-terminal device (memristor), three-terminal transistors evoke greater attention because of the controlled conductance between the source and drain. The purpose of this paper is to investigate the synaptic plasticity of the TiO2 nanowire transistor. Design/methodology/approach TiO2 nanowire transistor was assembled by dielectrophoresis, and the synaptic plasticity such as paired-pulse facilitation, learning behaviors and high-pass filter were studied. Findings F

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Xie, Dongyu, Xiaoci Liang, Di Geng, Qian Wu, and Chuan Liu. "An Enhanced Synaptic Plasticity of Electrolyte-Gated Transistors through the Tungsten Doping of an Oxide Semiconductor." Electronics 13, no. 8 (2024): 1485. http://dx.doi.org/10.3390/electronics13081485.

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Oxide electrolyte-gated transistors have shown the ability to emulate various synaptic functions, but they still require a high gate voltage to form long-term plasticity. Here, we studied electrolyte-gated transistors based on InOx with tungsten doping (W-InOx). When the tungsten-to-indium ratio increased from 0% to 7.6%, the memory window of the transfer curve increased from 0.2 V to 2 V over a small sweep range of −2 V to 2.5 V. Under 50 pulses with a duty cycle of 2%, the conductance of the transistor increased from 40-fold to 30,000-fold. Furthermore, the W-InOx transistor exhibited improv

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Fazio, Al. "Flash Memory Scaling." MRS Bulletin 29, no. 11 (2004): 814–17. http://dx.doi.org/10.1557/mrs2004.233.

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AbstractIn order to meet technology scaling in the field of solid-state memory and data storage, the mainstream transistor-based flash technologies will start evolving to incorporate material and structural innovations. Dielectric scaling in nonvolatile memories is approaching the point where new approaches will be required to meet the scaling requirements while simultaneously meeting the reliability and performance requirements of future products. High-dielectric-constant materials are being explored as possible candidates to replace the traditional SiO2 and ONO (oxide/nitride/oxide) films us

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Hellkamp, Daniel, and Kundan Nepal. "True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors." Journal of Circuits, Systems and Computers 28, no. 05 (2019): 1950085. http://dx.doi.org/10.1142/s0218126619500853.

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Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [Formula: see text]- and [Formula: see text]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar

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Lee, Dain, Yongsuk Choi, Euyheon Hwang, Moon Sung Kang, Seungwoo Lee, and Jeong Ho Cho. "Black phosphorus nonvolatile transistor memory." Nanoscale 8, no. 17 (2016): 9107–12. http://dx.doi.org/10.1039/c6nr02078j.

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19

Fuhrer, M. S., B. M. Kim, T. Dürkop, and T. Brintlinger. "High-Mobility Nanotube Transistor Memory." Nano Letters 2, no. 7 (2002): 755–59. http://dx.doi.org/10.1021/nl025577o.

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20

Kim, Soo-Jin, and Jang-Sik Lee. "Flexible Organic Transistor Memory Devices." Nano Letters 10, no. 8 (2010): 2884–90. http://dx.doi.org/10.1021/nl1009662.

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21

Ni, Yao, Yongfei Wang, and Wentao Xu. "Flexible Transistor‐Structured Memory: Recent Process of Flexible Transistor‐Structured Memory (Small 9/2021)." Small 17, no. 9 (2021): 2170037. http://dx.doi.org/10.1002/smll.202170037.

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22

Boampong, Amos Amoako, Jae-Hyeok Cho, Yoonseuk Choi, and Min-Hoi Kim. "Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure." Journal of Nanoscience and Nanotechnology 21, no. 3 (2021): 1766–71. http://dx.doi.org/10.1166/jnn.2021.18923.

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We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to t

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Jin, Risheng, Keli Shi, Beibei Qiu, and Shihua Huang. "Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate." Nanotechnology 33, no. 2 (2021): 025201. http://dx.doi.org/10.1088/1361-6528/ac2dc5.

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Abstract Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory

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Sedaghat, Mahsa, and Mahdi Salimi. "Evaluation and Comparison of CMOS logic circuits with CNTFET." Journal of Research in Science, Engineering and Technology 3, no. 04 (2019): 1–9. http://dx.doi.org/10.24200/jrset.vol3iss04pp1-9.

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In this paper, a comparison between CMOS and MOSFET base circuits HSPICE is done with software. 0.13 CMOS transistor model for simulation and CNTFET Model of Stanford University used. In simulations amounts of power, circuit delay and PDP is calculated and these values were compared at the end. And tried to CNTFET applications of transistors in circuit design, including memory and logic circuits Ternary be expressed.

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Shim, Hyunseok, Kyoseung Sim, Faheem Ershad, et al. "Stretchable elastic synaptic transistors for neurologically integrated soft engineering systems." Science Advances 5, no. 10 (2019): eaax4961. http://dx.doi.org/10.1126/sciadv.aax4961.

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Artificial synaptic devices that can be stretched similar to those appearing in soft-bodied animals, such as earthworms, could be seamlessly integrated onto soft machines toward enabled neurological functions. Here, we report a stretchable synaptic transistor fully based on elastomeric electronic materials, which exhibits a full set of synaptic characteristics. These characteristics retained even the rubbery synapse that is stretched by 50%. By implementing stretchable synaptic transistor with mechanoreceptor in an array format, we developed a deformable sensory skin, where the mechanoreceptor

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Shrivastava, Anurag, and Mohan Gupta. "Evaluation of the Core Processor Cache Memory Architecture's Performance." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 11–18. http://dx.doi.org/10.51976/jfsa.211903.

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In this study, memory architectures for single-bit caches are studied. Voltage differential sense amplifiers and charge transfer differential sense amplifiers are used to study a six-transistor static random-access memory. In a single-bit, six-transistor static random-access memory, it has been demonstrated that the voltage differential sensing amplifier uses the least power.

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Gudlavalleti, R. H., B. Saman, R. Mays, et al. "A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040009. http://dx.doi.org/10.1142/s0129156420400091.

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Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWS-FET (1T) device and two

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Arimoto, Yoshihiro, and Hiroshi Ishiwara. "Current Status of Ferroelectric Random-Access Memory." MRS Bulletin 29, no. 11 (2004): 823–28. http://dx.doi.org/10.1557/mrs2004.235.

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AbstractThe current status of ferroelectric random-access memory (FeRAM) technology is reviewed in this article. Presented first is the status of conventional FeRAM, in which the memory cells are composed of ferroelectric capacitors to store the data and cell-selection transistors to access the selected capacitors. Discussed next are recent developments in the field. Pb(Zrx, Ti1–x)O3 (PZT) and SrBi2Ta2O9 (SBT) films are being used to produce 0.13 mμ and 0.18 μm FeRAM cells, respectively, with a stacked capacitor configuration; these cells are easily embedded into logic circuits. A new class of

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MATSUMOTO, KAZUHIKO. "ROOM-TEMPERATURE SINGLE ELECTRON DEVICES BY SCANNING PROBE PROCESS." International Journal of High Speed Electronics and Systems 10, no. 01 (2000): 83–91. http://dx.doi.org/10.1142/s0129156400000118.

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A single electron transistor (SET) and a single electron memory were fabricated using the improved pulse-mode AFM nano-oxidation process. A single electron transistor which works as an electrometer for detecting the potential of the memory node of the single electron memory showed clear Coulomb oscillation characteristics with the period of 2.1 V at room temperature. A single electron memory exhibited a hysteresis loop as the memory bias was scanned from 0 to 10 V and then back down to 0 V.

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Seon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (2019): 988. http://dx.doi.org/10.3390/electronics8090988.

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physic

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Kumari, Nibha, and Prof Vandana Niranjan. "Low-Power 6T SRAM Cell using 22nm CMOS Technology." Indian Journal of VLSI Design 2, no. 2 (2022): 5–10. http://dx.doi.org/10.54105/ijvlsid.b1210.092222.

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Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of convention

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Huang, Jing, Pengfei Tan, Fang Wang, and Bo Li. "Ferroelectric Memory Based on Topological Domain Structures: A Phase Field Simulation." Crystals 12, no. 6 (2022): 786. http://dx.doi.org/10.3390/cryst12060786.

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The low storage density of ferroelectric thin film memory currently limits the further application of ferroelectric memory. Topologies based on controllable ferroelectric domain structures offer opportunities to develop microelectronic devices such as high-density memories. This study uses ferroelectric topology domains in a ferroelectric field-effect transistor (FeFET) structure for memory. The electrical behavior of FeFET and its flip properties under strain and electric fields are investigated using a phase-field model combined with the device equations of field-effect transistors. When the

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Yin, Wan-Jun, Tao Wen, and Wei Zhang. "Design of Dynamic Random Access Memory Based on One Transistor One Diode Memory Cell." Journal of Nanoelectronics and Optoelectronics 16, no. 1 (2021): 114–18. http://dx.doi.org/10.1166/jno.2021.2924.

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This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains one capacitor and one

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Saman, Bander, P. Gogna, El-Sayed Hasaneen, J. Chandy, E. Heller, and F. C. Jain. "Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation." International Journal of High Speed Electronics and Systems 26, no. 03 (2017): 1740009. http://dx.doi.org/10.1142/s0129156417400092.

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This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has

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Natarajamoorthy, Mathan, Jayashri Subbiah, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design." Journal of Nanotechnology 2020 (April 30, 2020): 1–7. http://dx.doi.org/10.1155/2020/7608279.

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The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM c

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Jang, Won Douk, Young Jun Yoon, Min Su Cho, et al. "Design and Analysis of Metal-Oxide-Semiconductor Field-Effect Transistor-Based Capacitorless One-Transistor Embedded Dynamic Random-Access Memory with Double-Polysilicon Layer Using Grain Boundary for Hole Storage." Journal of Nanoscience and Nanotechnology 20, no. 11 (2020): 6596–602. http://dx.doi.org/10.1166/jnn.2020.18767.

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In this work, a capacitorless one-transistor embedded dynamic random-access memory based on a metal-oxide-semiconductor field-effect transistor with a double-polysilicon layer structure has been proposed and investigated using technology computer-aided design simulation. By using the grain boundary for hole storage, a higher sensing margin of 4.35 /μA//μm is achieved compared to that without using the grain boundary. Furthermore, the proposed device achieves a superior retention time of 555.77 /μs, which is reasonable from the viewpoint of its application in embedded systems (>100 /μs), eve

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Rumberg, Brandon, Spencer Clites, Haifa Abulaiha, Alexander DiLello, and David Graham. "Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays." Journal of Low Power Electronics and Applications 11, no. 1 (2021): 4. http://dx.doi.org/10.3390/jlpea11010004.

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Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present

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Wang, Peng-Fei, Xi Lin, Lei Liu, et al. "A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation." Science 341, no. 6146 (2013): 640–43. http://dx.doi.org/10.1126/science.1240961.

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As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensit

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Qiu, Haiyang, Dandan Hao, Hui Li, et al. "Transparent and biocompatible In₂O₃ artificial synapses with lactose–citric acid electrolyte for neuromorphic computing." Applied Physics Letters 121, no. 18 (2022): 183301. http://dx.doi.org/10.1063/5.0124219.

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Electrolyte-gated synaptic transistors are promising for artificial neural morphological devices. However, few literatures have been reported regarding the manufacturing of electrolyte-gated synaptic transistors with low cost and biocompatible components. Here, the fully transparent synaptic transistors based on water-induced In2O3 thin films have been integrated by sol–gel method at low temperature, and lactose dissolved in citric acid solution is used as the gate electrolyte. The migration of the ions at the interface plays a crucial role in the potentiation and depression of the synaptic we

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Chiquet, Philippe, Jérémy Postel-Pellerin, Célia Tuninetti, Sarra Souiki-Figuigui, and Pascal Masson. "Enhancement of flash memory endurance using short pulsed program/erase signals." ACTA IMEKO 5, no. 4 (2016): 29. http://dx.doi.org/10.21014/acta_imeko.v5i4.422.

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The present paper proposes to investigate the effect of short pulsed Program/Erase signals on the functioning of Flash memory transistors. Usually, electrical operations related to said devices involve the application of single long pulses to various terminals of the transistor to induce various tunneling effects allowing the variation of the floating gate charge. According to the literature, the oxide degradation occurring after a number of electrical operations, leading to loss of performance and reliability, can be reduced by replacing DC stress by AC stress or by reducing the time spent un

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Duraivel, A. N., B. Paulchamy, and K. Mahendrakan. "Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 602–11. http://dx.doi.org/10.1166/jno.2021.2984.

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Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but

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Pérez-Tomás, Amador, Anderson Lima, Quentin Billon, Ian Shirley, Gustau Catalan, and Mónica Lira-Cantú. "A Solar Transistor and Photoferroelectric Memory." Advanced Functional Materials 28, no. 17 (2018): 1707099. http://dx.doi.org/10.1002/adfm.201707099.

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Liang, Lijuan, Wenjuan He, Rong Cao, et al. "Non-Volatile Transistor Memory with a Polypeptide Dielectric." Molecules 25, no. 3 (2020): 499. http://dx.doi.org/10.3390/molecules25030499.

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Organic nonvolatile transistor memory with synthetic polypeptide derivatives as dielectric was fabricated by a solution process. When only poly (γ-benzyl-l-glutamate) (PBLG) was used as dielectric, the device did not show obvious hysteresis in transfer curves. However, PBLG blended with PMMA led to a remarkable increase in memory window up to 20 V. The device performance was observed to remarkably depend on the blend ratio. This study suggests the crystal structure and the molecular alignment significantly affect the electrical performance in transistor-type memory devices, thereby provides an

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Song, Chong-Myeong, and Hyuk-Jun Kwon. "Ferroelectrics Based on HfO2 Film." Electronics 10, no. 22 (2021): 2759. http://dx.doi.org/10.3390/electronics10222759.

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The discovery of ferroelectricity in HfO2 thin film, which is compatible with the CMOS process, has revived interest in ferroelectric memory devices. HfO2 has been found to exhibit high ferroelectricity at a few nanometers thickness, and studies have rapidly progressed in the past decade. Ferroelectricity can be induced in HfO2 by various deposition methods and heat treatment processes. By combining ferroelectric materials with field-effect transistors, devices that combine logic and memory functions can be implemented. Ferroelectric HfO2-based devices show high potential, but there are some c

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Xie, Hui, Hao Wu, and Chang Liu. "Non-Volatile Memory Based on ZnO Thin-Film Transistor with Self-Assembled Au Nanocrystals." Nanomaterials 14, no. 8 (2024): 678. http://dx.doi.org/10.3390/nano14080678.

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Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold sw

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Gherendi, Florin, Daniela Dobrin, and Magdalena Nistor. "Transparent Structures for ZnO Thin Film Paper Transistors Fabricated by Pulsed Electron Beam Deposition." Micromachines 15, no. 2 (2024): 265. http://dx.doi.org/10.3390/mi15020265.

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Thin film transistors on paper are increasingly in demand for emerging applications, such as flexible displays and sensors for wearable and disposable devices, making paper a promising substrate for green electronics and the circular economy. ZnO self-assembled thin film transistors on a paper substrate, also using paper as a gate dielectric, were fabricated by pulsed electron beam deposition (PED) at room temperature. These self-assembled ZnO thin film transistor source–channel–drain structures were obtained in a single deposition process using 200 and 300 µm metal wires as obstacles in the p

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ABDEL-HAFEEZ, SALEH M., and ANAS S. MATALKAH. "CMOS EIGHT-TRANSISTOR MEMORY CELL FOR LOW-DYNAMIC-POWER HIGH-SPEED EMBEDDED SRAM." Journal of Circuits, Systems and Computers 17, no. 05 (2008): 845–63. http://dx.doi.org/10.1142/s0218126608004599.

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Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the

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Yil Suk, Yang, You In-kyu, Lee Won Jae, Yu Byoung Gon, and Cho Kyong-Ik. "Design of a Single-Transistor-Type Ferroelectric Field Effect Transistor Memory." Journal of the Korean Physical Society 40, no. 4 (2002): 701. http://dx.doi.org/10.3938/jkps.40.701.

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Sun, Shuo, Hyochul Kim, Zhouchen Luo, Glenn S. Solomon, and Edo Waks. "A single-photon switch and transistor enabled by a solid-state quantum memory." Science 361, no. 6397 (2018): 57–60. http://dx.doi.org/10.1126/science.aat3581.

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Single-photon switches and transistors generate strong photon-photon interactions that are essential for quantum circuits and networks. However, the deterministic control of an optical signal with a single photon requires strong interactions with a quantum memory, which has been challenging to achieve in a solid-state platform. We demonstrate a single-photon switch and transistor enabled by a solid-state quantum memory. Our device consists of a semiconductor spin qubit strongly coupled to a nanophotonic cavity. The spin qubit enables a single 63-picosecond gate photon to switch a signal field

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Zhao, Yuhang, and Jie Jiang. "Recent Progress on Neuromorphic Synapse Electronics: From Emerging Materials, Devices, to Neural Networks." Journal of Nanoscience and Nanotechnology 18, no. 12 (2018): 8003–15. http://dx.doi.org/10.1166/jnn.2018.16428.

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To realize intelligent functions in electronic devices like a human brain, it is important to develop the electronic devices that can imitate biological neurons and synapses (synaptic electronics). In this paper, we review the critical learning mechanisms for synaptic plasticity. Different electronic devices were developed to mimic biological synapses, such as atomic switch, phase change memory, ferroelectric memory, and electric-double-layer transistors. More importantly, several groups have realized the artificial neuromorphic network using multi-gate transistor architecture. The leap from s

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