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Literatura académica sobre el tema "Semiconductor wafers Electronic packaging"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 4 de febrero de 2022

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Artículos de revistas sobre el tema "Semiconductor wafers Electronic packaging"

1

Strandjord, Andrew, Thorsten Teutsch, Axel Scheffler, et al. "Wafer Level Packaging of Compound Semiconductors." Journal of Microelectronics and Electronic Packaging 7, no. 3 (2010): 152–59. http://dx.doi.org/10.4071/imaps.263.

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The microelectronics industry has implemented a number of different wafer level packaging (WLP) technologies for high volume manufacturing, including: UBM deposition, solder bumping, wafer thinning, and dicing. These technologies were successfully developed and implemented at a number of contract manufacturing companies, and then licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon-based semiconductors. Continuous improvements and modifications to these WLP processes have made them compatible with the changes o

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2

Fjelstad, Joseph, Thomas DiStefano, and Anthony Faraci. "Wafer level packaging of compliant, chip size ICs." Microelectronics International 17, no. 2 (2000): 23–27. http://dx.doi.org/10.1108/13565360010332426.

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The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVETM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint

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3

Liu, Xiao, Qi Wu, Dongshun Bai, et al. "Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing." Journal of Microelectronics and Electronic Packaging 14, no. 1 (2017): 39–43. http://dx.doi.org/10.4071/imaps.349121.

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Advanced wafer-level packaging (WLP) techniques, mainly driven by high-performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology have been widely studied and developed over the last decade for use in various WLP technologies, such as package on package, fan-out integration, and 2.5-D and 3-D integration using through-silicon-via. Temporary bonding technology enables handling of thinned substrates (&lt;100 μm), which can no longer self-support during backside processing and packagin

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4

Hackler, Doug. "Semiconductor-on-Polymer Wafer Level Chip Scale Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 001232–56. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tha2_007.

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Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semi

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5

Tsang, Cornelia, Janet Okada, and Eric Huenger. "Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 001555–95. http://dx.doi.org/10.4071/2011dpc-wp13.

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As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used

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6

Liu, Yong. "Trends of power semiconductor wafer level packaging." Microelectronics Reliability 50, no. 4 (2010): 514–21. http://dx.doi.org/10.1016/j.microrel.2009.09.002.

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7

Olson, Tim. "Transforming Electronic Interconnect." International Symposium on Microelectronics 2017, S1 (2017): 000080–108. http://dx.doi.org/10.4071/isom-2017-slide-4.

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From nanometers at the transistor level to 100's of microns at the ball grid array (BGA) connections, electronic interconnect of semiconductors spans orders of magnitude as it forms the central nervous system of today's advanced electronic products. Tectonic shifts are currently underway within the industries providing electronic interconnect. Traditional supply chain boundaries produce back end of line (BEOL) structures within wafer foundries ranging from 10's of nanometers to 10's of microns. First-level interconnect, or packaging, the classical purvey of semiconductor assembly and test serv

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8

Kim, Geumtaek, and Daeil Kwon. "Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties." Journal of Nanoscience and Nanotechnology 21, no. 5 (2021): 2987–91. http://dx.doi.org/10.1166/jnn.2021.19136.

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Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on

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Papatryfonos, Konstantinos, David R. Selviah, Avi Maman, et al. "Co-Package Technology Platform for Low-Power and Low-Cost Data Centers." Applied Sciences 11, no. 13 (2021): 6098. http://dx.doi.org/10.3390/app11136098.

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We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum do

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10

Datta, Madhav. "Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview." Journal of Micromanufacturing 3, no. 1 (2019): 69–83. http://dx.doi.org/10.1177/2516598419880124.

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Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so t

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Tesis sobre el tema "Semiconductor wafers Electronic packaging"

1

Zhang, Zhuqing. "Study on the curing process of no-flow and wafer level underfill for flip-chip applications." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180247/unrestricted/zhang%5Fzhuqing%5F200312%5Fphd.pdf.

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Patel, Chirag Suryakant. "Compliant Wafer Level Package (CWLP)." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13518.

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Bode, Christopher Allen. "Run-to-run control of overlay and linewidth in semiconductor manufacturing." Digital version:, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008281.

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4

Dukic, Megan Marie. "Vibrating Kelvin Probe Measurements of a Silicon Surface with the Underside Exposed to Light." Thesis, Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19862.

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This thesis addresses the use of a vibrating Kelvin probe to monitor the change in the front surface potential of a silicon wafer while the rear surface is illuminated with monochromatic, visible light. Two tests were run to verify the change in surface potential. One test increased the intensity of the light and the other increased the wavelength while recording the front surface potential. The change in the surface potential for a range of intensities of incident light was recorded and analyzed. The results show that the change in surface potential increased with increasing intensity. Fo

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5

Wang, Cai Johnson R. Wayne. "High temperature high power SiC devices packaging processes and materials development." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/doctoral/WANG_CAI_24.pdf.

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6

Bowman, Amy Catherine. "A selective encapsulation solution for packaging an optical micro electro mechanical system." Link to electronic thesis, 2002. http://www.wpi.edu/Pubs/ETD/Available/etd-0108102-140953.

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Thesis (M.S.)--Worcester Polytechnic Institute.<br>Keywords: packaging; micro electro mechanical systems; MEMS; electronics; die warpage; die bow; encapsulant; encapsulate; electrochemical migration; corrosion; wirebonds. Includes bibliographical references (p. 94-99).

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7

Bai, Guofeng. "Low-Temperature Sintering of Nanoscale Silver Paste for Semiconductor Device Interconnection." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29409.

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This research has developed a lead-free semiconductor device interconnect technology by studying the processing-microstructure-property relationships of low-temperature sintering of nanoscale silver pastes. The nanoscale silver pastes have been formulated by adding organic components (dispersant, binder and thinner) into nano-silver particles. The selected organic components have the nano-particle polymeric stabilization, paste processing quality adjustment, and non-densifying diffusion retarding functions and thus help the pastes sinter to ~80% bulk density at temperatures no more than 300Â°C

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8

Yoon, Sangwoong. "LC-tank CMOS Voltage-Controlled Oscillators using High Quality Inductor Embedded in Advanced Packaging Technologies." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/4887.

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This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si

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9

Lu, Sin-Ruei, and 盧信睿. "Research of miniaturization packaging technology for semiconductor electronic component Schottky diode." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/48rq3w.

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碩士<br>中華科技大學<br>經營管理研究所<br>103<br>Taiwan's semiconductor industry is divided into three blocks, e.g. wafer design, wafer foundry and the own brand design, long-term growth rate in multiples of rapid growth, attracting many manufacturers to enter the lower technical and financial threshold semiconductor packaging industry; but the bullwhip effect phenomenon this cyclical industry and supply chain, semiconductor packaging plant mostly facing severe price competition. Since the entire electronics industry towards the trend in light, thin, short and small size. In order to sustainable development

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10

Ayhan, Ali Osman. "Finite element analysis of nonlinear deformation mechanisms in semiconductor packages /." Diss., 1999. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:9955139.

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Libros sobre el tema "Semiconductor wafers Electronic packaging"

1

Reliability of electronic packages and semiconductor devices. McGraw-Hill, 1997.

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2

IEEE/UCS/SEMI, International Symposium on Semiconductor Manufacturing (4th 1995 Austin Tex ). Fourth IEEE/UCS/SEMI International Symposium on Semiconductor Manufacturing: [proceedings]. Institute of Electrical and Electronics Engineers, 1995.

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3

Randa, J. Noise temperature measurements on wafer. U.S. Dept. of Commerce, Technology Administration, National Institute of Standards and Technology, 1997.

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4

N, Buckley D., Ringel S. A, Ren F, Electrochemical Society Electronics Division, and State-of-the-Art Program on Compound Semiconductors (20th : 1994 : San Francisco, Calif.), eds. Proceedings of the Symposium on Large Area Wafer Growth and Processing for Electronic and Photonic Devices and the Twentieth State-of-the Art Program on Compound Semiconductors (SOTAPOCS XX). The Electrochemical Society, 1995.

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5

Yong, Liu, and Shichun Qu. Wafer-Level Chip-Scale Packaging: Analog and Power Semiconductor Applications. Springer, 2014.

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6

Yong, Liu, and Shichun Qu. Wafer-Level Chip-Scale Packaging: Analog and Power Semiconductor Applications. Springer, 2016.

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7

J, Kowalski G., American Society of Mechanical Engineers. Electrical and Electronic Packaging Division., International Mechanical Engineering Congress and Exposition (2000 : Orlando, Fla.), and Symposium on Mechanics of SMT and Photonic Structures (12th : 2000 : Orlando, Fla.), eds. Packaging of electronic and photonic devices: Presented at the 2000 ASME International Mechanical Engineering Congress and Exposition, November 5-10, 2000, Orlando, Florida. American Society of Mechanical Engineers, 2000.

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8

Microelectronics Packaging Handbook, Part II: Semiconductor Packaging (Microelectronics Packaging Handbook). Springer, 1997.

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9

Zhao, Wei, Hui Liu, Xingsheng Liu, and Lingling Xiong. Packaging of High Power Semiconductor Lasers. Springer, 2014.

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10

Zhao, Wei, Hui Liu, Xingsheng Liu, and Lingling Xiong. Packaging of High Power Semiconductor Lasers. Springer, 2016.

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Capítulos de libros sobre el tema "Semiconductor wafers Electronic packaging"

1

Bridges, Denzel, Ruozhou Li, Zhiming Gao, et al. "Metallic Nanopastes for Power Electronic Packaging." In Semiconductor Nanocrystals and Metal Nanoparticles. CRC Press, 2016. http://dx.doi.org/10.1201/9781315374628-11.

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2

Elshabini, A. A., F. Barlow, and P. J. Wang. "Electronic Packaging: Semiconductor Packages ☆." In Reference Module in Materials Science and Materials Engineering. Elsevier, 2017. http://dx.doi.org/10.1016/b978-0-12-803581-8.02048-8.

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Actas de conferencias sobre el tema "Semiconductor wafers Electronic packaging"

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Jaeger, Richard C., Jeffrey C. Suhling, Yonggang Chen, Shahan Rahaman, and M. Nokibul Islam. "A Chip-on-Beam Calibration Technique for Piezoresistive Stress Sensor Die." In ASME 2003 International Electronic Packaging Technical Conference and Exhibition. ASMEDC, 2003. http://dx.doi.org/10.1115/ipack2003-35276.

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Wafer-level and four-point-bending (4PB) techniques are normally utilized for calibration of stress sensor test die. While excellent accuracy and repeatability have been demonstrated, the wafer-level technique requires access to a complete silicon wafer, whereas the 4PB method requires 5–10 cm strips of die. However, access to full wafers, or even strips of die, is typically limited to companies and universities with captive semiconductor fabrication facilities. In this paper, a chip-on-beam technique is demonstrated in which individual die are attached to silicon beams, and stress for calibra

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2

Chen, Jun, R. C. Jaeger, and J. C. Suhling. "Piezoresistive Theory for 4H Silicon Carbide Stress Sensors on Four-Degree Off-Axis Wafers." In ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/ipack2019-6461.

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Abstract Piezoresistive stress sensors have been shown to be a powerful tool for experimental evaluation of die stress distributions. Silicon Carbide (SiC) wide bandgap semiconductors are promising materials for development of high temperature power electronics. In the past, the analysis and design of stress sensors on silicon carbide have assumed that the wafer surface is aligned with the crystallographic axes. However, 4H silicon carbide wafers are produced with a four-degree off-axis cut to ensure high-quality homoepitaxial growth, so that the tilted wafer surface does not perfectly coincid

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3

Hung, Chu-Pao (Otis), Yu-Po Wang, Steven Chen, and Katch Wan. "Fan-Out MCM Solutions Study for Heterogeneous Integration on Intelligent Computing Application." In ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/ipack2020-2528.

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Abstract In recent years, semiconductor products have developed rapidly, from desktop computers with basic computing to Internet-connected smartphones, to emerging intelligent and perceived smart system products, such as mass-produced of smart home appliances, smart watches, and under development of smart glasses. The product trend is toward high performance, multi-functional integration, thinner profile and lower cost features. These requirements are interrelated with wafer technology and assembly process development. The advanced wafer technology, such as 5nm / 3nm, will provide higher perfo

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4

Ma, Lunyu, Qi Zhu, and Suresh K. Sitaraman. "Contact Reliability of Innovative Compliant Interconnects for Next Generation Electronic Packaging." In ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-41753.

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The ongoing research work at Georgia Institute of Technology, PARC, Inc., and Nanonexus, Inc. funded by NIST/ATP, aims to develop a novel compliant interconnect technology based on stress-engineering of thin-film metal deposition. The minimum pitch size can reach as small as 6 μm. The fabrication of the stress-engineered compliant interconnect is compatible with the standard IC fabrication processes. Therefore, the compliant interconnect fabrication can be fully integrated into front-end semiconductor process. Also, thousands of interconnects can be fabricated on the wafer in one batch, which

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5

Qu, Yan, Ekachai Puttitwong, John R. Howell, Ofodike A. Ezekoye, and Kenneth S. Ball. "Drawdown-Effect of Lightpipes in Silicon Wafer Surface Temperature Measurements." In ASME 2005 Summer Heat Transfer Conference collocated with the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems. ASMEDC, 2005. http://dx.doi.org/10.1115/ht2005-72203.

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Lightpipe radiation thermometers (LPRTs) have been widely used for temperature measurement in the semiconductor industries. According to the International Technology Roadmap for Semiconductors 2004 (ITRS), temperatures for semiconductor wafer processing should be measurable to within an uncertainty of ± 1.5°C at 1,000 °C with temperature calibration traceable to ITS (international temperature standard)-90. To achieve this uncertainty, there are several issues associated with LPRTs to be resolved. The “draw-down effect” is the one that will be examined in this paper. We discuss this effect both

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6

Meyer, Andreas, Gabriele Grimm, Michael Hecker, Martin Weisheit, and Eckhard Langer. "Challenges for Physical Failure Analysis of 3D-Integrated Devices—Sample Preparation and Analysis to Support Process Development of TSVs." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0012.

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Abstract The trend to higher integration of electronic devices to include more functions into ever-smaller devices, such as mobile phones or tablet computers, drives the development of novel packaging technologies for semiconductor chips. One of the approaches to reduce packaging size and power consumption is to stack multiple silicon chips on top of each other. An alternative approach is the utilization of through-silicon vias (TSV) to connect multiple chips to each other. This paper provides a set of sample preparation and analysis techniques for the comprehensive analysis of TSVs in support

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7

Czurratis, Peter, Peter Hoffrogge, Sebastian Brand, Frank Altmann, and Matthias Petzold. "Failure Analysis Using Scanning Acoustic Microscopy for Diagnostics of Electronic Devices and 3D System Integration Technologies." In ISTFA 2012. ASM International, 2012. http://dx.doi.org/10.31399/asm.cp.istfa2012p0100.

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Abstract New semiconductor chip technologies and technologies for 3D integration require information’s of packaging and interface defects in 3 dimensions, that means the lateral dimension of the defect and the location inside the device or package must be defined. In this paper, new methodical approaches for non destructive failure analysis on 3D integrated TSV samples are introduced. The concepts combine improved scanning acoustic microscopy (SAM) imaging hardware with unique software solutions for defect identification and quantitative analysis of mechanical properties using scanning acousti

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8

Mungekar, Hemant, Young S. Lee, and Shankar Venkataraman. "Feature Evolution During Sub 100NM Gap-Fill and Etch." In ASME 2005 Summer Heat Transfer Conference collocated with the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems. ASMEDC, 2005. http://dx.doi.org/10.1115/ht2005-72326.

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Inductively coupled plasma (ICP) reactors are being used at low gas pressure (&lt;100mTorr) and high plasma density ([e] &gt; 1013/cm2) processes in semiconductor fabrication. In these reactors plasma is generated by inductively coupled electric field while positive ions are accelerated anisotropically by applying a negative bias RF to the substrate. Semiconductor manufacturers face many challenges as wafer size increases while device geometries decrease. Two key challenges for both process design and electronics processing equipment design are (a) scale up of process from 200mm to 300

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9

Hu, Yuh-Chung, Wei-Hsin Gau, and Wei-Hsiang Tu. "High Precision Young’s Modulus Extraction of Thin Films Through Measuring the Electric-Circuit Behavior of Microstructures." In ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/ipack2005-73337.

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This paper is aimed at developing a high precision algorithm for extracting the Young’s modulus of thin films through the capacitance-voltage measurement of microstructures at wafer level. Two flat micro cantilever beams made of single crystalline silicon are demonstrated. The average value of extracted Young’s modulus in (110) crystalline plane by the present methodology is about 169 GPa, compared to the well-defined value of 168 GPa, the error percentage is within 1% and the high precision and repeatability of the present methodology are verified. Since the driving and measuring signals of t

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Wei, J., C. K. Wong, and L. C. Lee. "Low temperature bonding process for wafer-level MEMS packaging." In 2004 IEEE International Conference on Semiconductor Electronics. IEEE, 2004. http://dx.doi.org/10.1109/smelec.2004.1620824.

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