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Artículos de revistas sobre el tema "Semiconductor wafers Electronic packaging"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 4 de febrero de 2022

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1

Strandjord, Andrew, Thorsten Teutsch, Axel Scheffler, et al. "Wafer Level Packaging of Compound Semiconductors." Journal of Microelectronics and Electronic Packaging 7, no. 3 (2010): 152–59. http://dx.doi.org/10.4071/imaps.263.

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The microelectronics industry has implemented a number of different wafer level packaging (WLP) technologies for high volume manufacturing, including: UBM deposition, solder bumping, wafer thinning, and dicing. These technologies were successfully developed and implemented at a number of contract manufacturing companies, and then licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon-based semiconductors. Continuous improvements and modifications to these WLP processes have made them compatible with the changes o

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2

Fjelstad, Joseph, Thomas DiStefano, and Anthony Faraci. "Wafer level packaging of compliant, chip size ICs." Microelectronics International 17, no. 2 (2000): 23–27. http://dx.doi.org/10.1108/13565360010332426.

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The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVETM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint

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3

Liu, Xiao, Qi Wu, Dongshun Bai, et al. "Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing." Journal of Microelectronics and Electronic Packaging 14, no. 1 (2017): 39–43. http://dx.doi.org/10.4071/imaps.349121.

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Advanced wafer-level packaging (WLP) techniques, mainly driven by high-performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology have been widely studied and developed over the last decade for use in various WLP technologies, such as package on package, fan-out integration, and 2.5-D and 3-D integration using through-silicon-via. Temporary bonding technology enables handling of thinned substrates (&lt;100 μm), which can no longer self-support during backside processing and packagin

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4

Hackler, Doug. "Semiconductor-on-Polymer Wafer Level Chip Scale Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 001232–56. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tha2_007.

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Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semi

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5

Tsang, Cornelia, Janet Okada, and Eric Huenger. "Evalulation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (2011): 001555–95. http://dx.doi.org/10.4071/2011dpc-wp13.

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As 3D packaging technology and designs evolve, increasing complexity has been introduced in the fabrication of these devices. The integration of optical devices along with electronic wired elements such as the package platform identified in image sensors is one prime example where the design elements of the structures significantly increase the topography on the surface of the system. This multiplies the degree of difficulty in the lithography solution chosen to facilitate fabrication of these structures. The use of electrodeposited (ED) photoresists is a technology platform that has been used

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6

Liu, Yong. "Trends of power semiconductor wafer level packaging." Microelectronics Reliability 50, no. 4 (2010): 514–21. http://dx.doi.org/10.1016/j.microrel.2009.09.002.

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7

Olson, Tim. "Transforming Electronic Interconnect." International Symposium on Microelectronics 2017, S1 (2017): 000080–108. http://dx.doi.org/10.4071/isom-2017-slide-4.

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From nanometers at the transistor level to 100's of microns at the ball grid array (BGA) connections, electronic interconnect of semiconductors spans orders of magnitude as it forms the central nervous system of today's advanced electronic products. Tectonic shifts are currently underway within the industries providing electronic interconnect. Traditional supply chain boundaries produce back end of line (BEOL) structures within wafer foundries ranging from 10's of nanometers to 10's of microns. First-level interconnect, or packaging, the classical purvey of semiconductor assembly and test serv

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8

Kim, Geumtaek, and Daeil Kwon. "Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties." Journal of Nanoscience and Nanotechnology 21, no. 5 (2021): 2987–91. http://dx.doi.org/10.1166/jnn.2021.19136.

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Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on

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9

Papatryfonos, Konstantinos, David R. Selviah, Avi Maman, et al. "Co-Package Technology Platform for Low-Power and Low-Cost Data Centers." Applied Sciences 11, no. 13 (2021): 6098. http://dx.doi.org/10.3390/app11136098.

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We report recent advances in photonic–electronic integration developed in the European research project L3MATRIX. The aim of the project was to demonstrate the basic building blocks of a co-packaged optical system. Two-dimensional silicon photonics arrays with 64 modulators were fabricated. Novel modulation schemes based on slow light modulation were developed to assist in achieving an efficient performance of the module. Integration of DFB laser sources within each cell in the matrix was demonstrated as well using wafer bonding between the InP and SOI wafers. Improved semiconductor quantum do

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10

Datta, Madhav. "Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview." Journal of Micromanufacturing 3, no. 1 (2019): 69–83. http://dx.doi.org/10.1177/2516598419880124.

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Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so t

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11

Muro, Hideo. "History and Recent Progress of MEMS Physical Sensors." Advances in Science and Technology 81 (September 2012): 1–8. http://dx.doi.org/10.4028/www.scientific.net/ast.81.1.

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Recently various electronic control systems for automotive, industrial and consumer-electronic applications have been developed using advanced semiconductor technologies including MEMS sensors. This paper reviews the history of the development of the MEMS physical sensors and highlights their recent progress where their research trends are categorized into the following 4 items:ⅰ) Incorporation of heterogeneous sensors,ⅱ) Integration with advanced CMOS circuitry,ⅲ) Improvement on wafer-level packaging technology, ⅳ) Adoption of new materials. Several examples of each item are introduced in thi

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12

Malachowski, Karl, Karen Qian, Maaike Op de Beeck, et al. "Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging." International Symposium on Microelectronics 2012, no. 1 (2012): 000148–53. http://dx.doi.org/10.4071/isom-2012-ta51.

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Material selection is the key issue when developing a biocompatible packaging process for implantable electronic systems. To secure a reliable performance of the chip in such a package, its encapsulation has to be considered up-front in the wafer-level integration scheme. A differentiation of two main material types can be made:1) Insulating or passive materials functioning as a bi-directional diffusion barrier preventing body fluids leaking into the package causing systems malfunction due to possible materials corrosion and also avoiding a leakage of built-in materials to the in-vivo environm

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13

Wang, Pao-Hsiung, Yu-Wei Huang, and Kuo-Ning Chiang. "Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging." Micromachines 12, no. 3 (2021): 295. http://dx.doi.org/10.3390/mi12030295.

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The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simul

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14

A. Rahman, Ahmad R., and Nazrul Anuar Nayan. "Ejectorless Method for Die Attach Pick Up for Cracking Improvement on Thin High-Aspect Ratio Die." International Journal of Online and Biomedical Engineering (iJOE) 16, no. 08 (2020): 55. http://dx.doi.org/10.3991/ijoe.v16i08.14727.

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<p>The demand for producing small, thin, and light electronic devices is increasing. As a result, the design and assembly of electronic packaging technology have been developed. To meet the ever-increasing technology requirements, the critical process in the semiconductor packaging include wafer back grinding, sawing, and die attach. Given that the die thickness is lower than the previous ones, the risk of die cracking failures, which can lead to device malfunction, becomes high. In the die attach process, the ejector pin has an effect during the pick and place processes. Such impact may

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15

Karlicek, Robert F. "The Evolution of LED Packaging: New Approaches for Solid State Lighting." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 000738–55. http://dx.doi.org/10.4071/2012dpc-ta44.

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The rapid evolution of solid state lighting is driving rapid and innovative approaches to LED packaging. While the bulk of LEDs are still packaged using decades old technology, the cost and performance needs of solid state lighting are forcing the development of new light emitter packaging technology, some of it being imported from more conventional electronic packaging. Concepts like wafer level packaging, chip on flex technology and SIP technology are infiltrating the LED packaging landscape, but with innovations developing from the need to simultaneously manage input power, thermal dissipat

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16

Champagne, Tim, Jay Chao, Kazuyasu Tanaka, Ramachandran Trichur, and Rong Zhang. "Ultra-low Warpage and Anhydride-free Liquid Compression Molding Materials for Advanced Semiconductor Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (2019): 000408–28. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp2_016.

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Advanced semiconductor packaging landscape is rapidly evolving to accommodate requirements of front end node shrink and performance expectations from emerging applications in big data, artificial intelligence, mobile and autonomous driving. Multiple innovations in packaging process technology as well as processing materials enable the progress in advanced packaging. Several wafer level packaging (WLP) platforms have emerged recently using fan-in, fan-out, 2.5D and 3D packaging processes to satisfy the requirements of increased functionality, reduced form factor, lower power consumption, and hi

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17

Mauer, Laura, John Taddei, and Scott Kroeger. "Wafer Thinning for Advanced Packaging Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–26. http://dx.doi.org/10.4071/2017dpc-wp2_presentation1.

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Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discus

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18

Choubey, Anupam, E. Anzures, A. Dhoble, et al. "Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (2012): 001432–51. http://dx.doi.org/10.4071/2012dpc-wa14.

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Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and elec

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19

Karjalainen, Päivi H., and Pekka Heino. "On-Wafer Capacitors Under Mechanical Stress." Journal of Electronic Packaging 129, no. 3 (2006): 287–90. http://dx.doi.org/10.1115/1.2753918.

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New packaging materials make it possible to produce flexible system in package (SIP) and system on package (SOP) modules. However, in these the integrated circuits are exposed to increased mechanical stresses. The stresses may become even more severe when thinned chips are used. The effect of mechanical stress on the characteristics of on-wafer capacitors was studied. The mechanical stress increased clearly the resonance frequency of poly-insulator-poly capacitors, but caused only minor impedance changes for metal-insulator-metal capacitors. No fatal stress-induced phenomenon was found and the

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20

Ahmad, Shamim. "Organic semiconductors for device applications: current trends and future prospects." Journal of Polymer Engineering 34, no. 4 (2014): 279–338. http://dx.doi.org/10.1515/polyeng-2013-0267.

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Abstract With the rich experience of developing silicon devices over a period of the last six decades, it is easy to assess the suitability of a new material for device applications by examining charge carrier injection, transport, and extraction across a practically realizable architecture; surface passivation; and packaging and reliability issues besides the feasibility of preparing mechanically robust wafer/substrate of single-crystal or polycrystalline/amorphous thin films. For material preparation, parameters such as purification of constituent materials, crystal growth, and thin-film dep

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21

Caswell, Greg, Craig Hillman, Nathan Blattau, Frank Pitelli Navius, Paul Waters, and Gil Sharon. "Automate 3D Modeling of Trace and Via Structures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001753–83. http://dx.doi.org/10.4071/poster_dfr2.

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The simulation and modeling of advanced packaging has always been hindered by the duality of the design process. Electrical design packages are based on vectors, plotting, and routing compounds that align well with the physical process of fabricating substrates. However, these design files contain numerous flaws and limitations that does not allow them to be directly imported into modern CAE tools for mechanical, thermal, and electrical modeling and simulation. The resulting gap results in extended model development (physical artifacts are recreated in the CAE software), gross assumptions abou

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22

Hackler, Douglas, Dale Wilson, and Edward Prack. "Ultra-Thin Wafer-Level Chip Scale Packaging." International Symposium on Microelectronics 2019, no. 1 (2019): 000157–62. http://dx.doi.org/10.4071/2380-4505-2019.1.000157.

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Abstract IC packages are getting thinner to facilitate thinner electronics products. Labels and tags are getting smarter. Electronics are starting to bend, and reliability is in question. Semiconductor-on-Polymer™ (SoP) Chip Scale Packaging (CSP) is enabling ultra-thin flexible hybrid electronics and sensors today. This presentation shares the development, of SoP application to flexible hybrid electronics (FHE), and where SoP fits in IC packaging technologies. SoP CSP facilitates more functionality for hybrid approaches with printed electronics by allowing seamless integration of thin die into

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23

Wang, Liang, Charles G. Woychik, Guilian Gao, et al. "Challenges of Scalable 2.5D IC Assembly." Journal of Microelectronics and Electronic Packaging 12, no. 3 (2015): 123–28. http://dx.doi.org/10.4071/imaps.455.

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Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rap

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24

Cai, Shengran, Wei Li, Hongshuo Zou, et al. "Design, Fabrication, and Testing of a Monolithically Integrated Tri-Axis High-Shock Accelerometer in Single (111)-Silicon Wafer." Micromachines 10, no. 4 (2019): 227. http://dx.doi.org/10.3390/mi10040227.

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In this paper, a monolithic tri-axis piezoresistive high-shock accelerometer has been proposed that has been single-sided fabricated in a single (111)-silicon wafer. A single-cantilever structure and two dual-cantilever structures are designed and micromachined in one (111)-silicon chip to detect Z-axis and X-/Y-axis high-shock accelerations, respectively. Unlike the previous tri-axis sensors where the X-/Y-axis structure was different from the Z-axis one, the herein used similar cantilever sensing structures for tri-axis sensing facilitates design of uniform performance among the three elemen

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25

Ghaffarian, Reza. "Lift up! to IC Packaging: Trends and Assembly Reliability." International Symposium on Microelectronics 2016, S1 (2016): S1—S28. http://dx.doi.org/10.4071/isom-2016-slide-3.

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For five decades, the semiconductor industry has distinguished itself from other industries by continuously reducing IC sizes while exponentially increasing functionality (Moore's Law) that enabled IC shrinkage and lower cost. The problem now is that IC shrinkage hit a brick wall, in response, a new paradigm shift is emerged—packaging technologies. Industries now focusing on shrinking the IC packaging through stacking and system integration. This talk presents electronics packaging miniaturization trends from ball grid arrays to wafer level and stack technologies with emphasis on system to pac

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26

Mobley, Tim, Roupen Keusseyan, Tim LeClair, Konstantin Yamnitskiy, and Regi Nocon. "Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (2015): 001378–407. http://dx.doi.org/10.4071/2015dpc-wp13.

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Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specificatio

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27

Evertsen, Rogier, Nicolle Beckers, Shao Ying Wang, and Richard van der Stam. "Remote Plasma Etching of Backend Semiconductor Materials for Reliable Packaging." Solid State Phenomena 314 (February 2021): 312–17. http://dx.doi.org/10.4028/www.scientific.net/ssp.314.312.

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This paper describes a study on the remote plasma etching of silicon-based semiconductor wafers after laser separation. Several process parameters having impact on the chip reliability, expressed as changes in die material strength, have been studied and optimized. The results show the potential of fluorine-based plasma processing for cleaning dies and improving die performance and thus have a role as a process enabling advanced packaging technologies.

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Tessier, Ted. "Extending WLCSP Packaging Technology Capabilities to Enable Miniaturized Sensor and MEMS Packaging Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (2016): 000397–420. http://dx.doi.org/10.4071/2016dpc-ta23.

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WLCSP has been widely deployed in portable computing and communication devices for efficient die level packaging of integrated semiconductor and integrated passive applications. More recently with the proliferation of smart phone capabilities and applications as well as the emergence of Internet of Things and Wearable Electronics, MEMS and sensor devices in minimized package formats have become increasingly pervasive. These include image sensors, light sensors, finger print sensors as well as accelerometer, gyroscope and other MEMS motion sensing devices. It is predicted that the widespread ad

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Lee, Seong Min. "Prevention of Dicing-Induced Damage in Semiconductor Wafers." Key Engineering Materials 345-346 (August 2007): 485–88. http://dx.doi.org/10.4028/www.scientific.net/kem.345-346.485.

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Semiconductor devices are usually formed on a single silicon wafer during a batch processing method. Individual devices are separated from the wafer during the wafer sawing or dicing step. Subsequent packaging processes are then performed on the individual devices, whose edge portions are very susceptible to mechanical damage from the sawing process. Defects formed along device edges due to the dicing saw blade often provide potential sites for serious reliability problems. If the scribing area is reduced, the number of the separated devices from a single wafer increases, which results in prod

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30

Kumar, Shashi, Gaddiella Diengdoh Ropmay, Pradeep Kumar Rathore, Peesapati Rangababu, and Jamil Akhtar. "Fabrication and testing of PMOS current mirror-integrated MEMS pressure transducer." Sensor Review 40, no. 2 (2019): 141–51. http://dx.doi.org/10.1108/sr-07-2019-0182.

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Purpose This paper aims to describe the fabrication, packaging and testing of a resistive loaded p-channel metal-oxide-semiconductor field-effect transistor-based (MOSFET-based) current mirror-integrated pressure transducer. Design/methodology/approach Using the concept of piezoresistive effect in a MOSFET, three identical p-channel MOSFETs connected in current mirror configuration have been designed and fabricated using the standard polysilicon gate process and microelectromechanical system (MEMS) techniques for pressure sensing application. The channel length and width of the p-channel MOSFE

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31

Gupta, Atul, Eric Snyder, Christiane Gottschalke, et al. "First Demonstration of Fine Line RDL Yield Enhancement using an Innovative Ozone Treatment Process for Panel Fan-out and Interposers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–19. http://dx.doi.org/10.4071/2017dpc-tp1_presentation2.

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As front end transistor scaling by Moore's law faces economic and technical challenges, interconnect scaling by advanced packaging technologies has started to add value at system level for a variety of electronics applications including consumer, high performance computing and automotive. The focus on yield improvement at every node that has enabled transistor scaling is now becoming a very critical need for high volume manufacturing of advanced packaging technologies such as 2.5D interposers and high density fanout [1]. This paper describes the first demonstration of a novel atmospheric appro

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Ding, Hai, I. Charles Ume, and Cheng Zhang. "Warpage Analysis of Underfilled Wafers." Journal of Electronic Packaging 126, no. 2 (2004): 265–70. http://dx.doi.org/10.1115/1.1707036.

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Wafer-level packaging (WLP) is one of the future trends in electronic packaging. Since 1994, many companies have released various WLP licenses. One of the common concerns of WLP is wafer warpage. Warpage of wafers tends to introduce cracking or delamination during dicing and low temperature storage processes. After wafer dicing, warpage could affect the quality of the dies and shorten the life of each packaged product. Many documented works indicated that in the design and implementation of multilayer structured electronic packaging products, some key parameters must be carefully considered an

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Yoon, Seung Wook. "Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (2017): 1–20. http://dx.doi.org/10.4071/2017dpc-tp2_presentation5.

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FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries

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Teshima, J., E. Moyal, and Jamil J. Clarke. "Streamlining Sample Preparation of Semiconductor Materials with a New Site-specific Cleaving Technology." Microscopy Today 21, no. 5 (2013): 22–26. http://dx.doi.org/10.1017/s155192951300093x.

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The global consumer market wants smaller, faster, more reliable, lower-cost products. The semiconductor industry has responded by the doubling of chip transistor density every two years, closely following Moore's Law. To meet their goals, the industry has made huge investments in R&D and manufacturing to miniaturize components, increase the size of substrates (wafers), improve the productivity of factories, and invent new packaging technology.

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Hackler, Douglas, and Edward Prack. "Ultra-thin Flip-Chip Assembly for Heterogenous and Hybrid Integration." International Symposium on Microelectronics 2020, no. 1 (2020): 000146–49. http://dx.doi.org/10.4071/2380-4505-2020.1.000146.

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Abstract Flip-chip packaging of thin-die, in fact any packaging of thin-die, is one of today’s most significant challenges for die handling. Despite the difficulties presented as the thickness of chips continues to decrease, the wide range of applications they have enabled across multiple industries has led to increasing interest, as evidenced by the growth in the cumulative total number of publications on thin silicon based electronics, including Ultra-Thin Chips (UTCs), thinning of Silicon-on-Insulator, and wafer thinning. Smart devices including labels, loggers, wearables, implantable medic

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Lim, Jacinta Aman, and Vinayak Pandey. "Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology." International Symposium on Microelectronics 2017, no. 1 (2017): 000263–69. http://dx.doi.org/10.4071/isom-2017-wa42_039.

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Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technolog

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37

Purvis, Gail. "Bridging roadmaps for semiconductor packaging." III-Vs Review 19, no. 7 (2006): 37–38. http://dx.doi.org/10.1016/s0961-1290(06)71822-1.

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38

Cohen, Jonathan, Woo Young Han, Gurvinder Singh, Keith Best, Amy Shay, and Mike Marshall. "Photoresist Residue Detection in Advanced Packaging." International Symposium on Microelectronics 2017, no. 1 (2017): 000584–89. http://dx.doi.org/10.4071/isom-2017-tha36_058.

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Abstract Semiconductor manufacturers are continuously driving efforts to put more computing power and speed into less volume. At the same time, consumers are demanding devices with more functionality that integrate a variety of interconnected circuit types. The result has been an increasing reliance on advanced packaging technologies that use fab-like processes to integrate multiple chips and to provide the increased I/O capability required. With continued focus on device miniaturization, the rapid detection of trace chemical residue during intermediate processing steps becomes increasingly di

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39

Lu, Yongqiang, Sian Collins, Laura B. Mauer, John Taddei, and John Clark. "Highly Selective Wet Silicon Etch Chemistry and Process for Advanced Semiconductor Packaging." International Symposium on Microelectronics 2016, no. 1 (2016): 000463–68. http://dx.doi.org/10.4071/isom-2016-tha41.

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Abstract A wet silicon etch chemistry and a process using the chemistry as a simple and cost-effective alternative to the polish/plasma etch silicon thinning process are presented in this paper. The new etch chemistry improves the Si etch rate over traditional etchants such as tetramethylammonium hydroxide (TMAH). The chemistry has very high silicon etch selectivity (ratio of Si etch rate to another film etch rate) over SiO2 and over copper films, with etch selectivity greater than 8000:1 and 2500:1 respectively. Chemical compatibility with typical packaging materials such as polybenzoxazole (

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40

Mallory, ChesterL, EdricH Tong, and Wayne Borglum. "4907931 Apparatus for handling semiconductor wafers." Microelectronics Reliability 31, no. 2-3 (1991): i. http://dx.doi.org/10.1016/0026-2714(91)90243-z.

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41

Barbara, Bruce. "Ultra-High Density System-in-Package (SiP) for the Lowest Size Weight and Power (SWAP)." International Symposium on Microelectronics 2016, no. 1 (2016): 000309–13. http://dx.doi.org/10.4071/isom-2016-wp32.

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Abstract Fan out wafer level packages have emerged across the market in an effort to reduce size and weight of electronics used in portable and wearable applications in the commercial, industrial, and the hi-reliability products space. If it is not a stationary platform, weight and volume reduction are imperative. For the stationary platforms, size and power are most critical. Integration of multiple complex heterogeneous IC components can only be done if there are a sufficient number of interconnect layers. Additionally, multiple interconnects are needed for transmission line creation and shi

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42

Hooper, Andy, and Daragh Finn. "Analysis of Silicon Micromachining by UV Lasers, and Implications for Full Cut Laser Dicing of Ultra-Thin Semiconductor Device Wafers." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (2010): 001743–59. http://dx.doi.org/10.4071/2010dpc-wp16.

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3D packaging technologies such as FLASH rely on die-to-die stacking of ultra-thin silicon devices with individual die thicknesses below 100 um. Because ultra-thin silicon wafers are very fragile, mechanical saw dicing of sub 100 um thick wafers tends to be more challenging, requiring slower processing and reduced throughput and/or yields. These challenges make full cut laser dicing an attractive solution. This presentation provides an investigation for machining of 50 um thick silicon wafers using a Gaussian-shaped, nanosecond pulsewidth, 355 nm UV laser. A range of machining speeds and laser

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43

Ono, Masashi, Kazutaka Nonomura, Li Bo Zhou, and Jun Shimizu. "Design of Digital Filters for Si Wafer Surface Profile Measurement - Noise Reduction by Wavelet Transform -." Key Engineering Materials 447-448 (September 2010): 544–48. http://dx.doi.org/10.4028/www.scientific.net/kem.447-448.544.

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Recently in semiconductor industry, production of ever flatter, thinner and larger silicon wafers are required to fulfill the demands of high-density packaging and cost reduction. In geometric evaluation of Si wafers, according to SEMI (Semiconductor Equipment and Materials International) standards, the required wafer flatness approaches to the 22 nanometers by year 2016 [1]. For such application, uncertainty of measured data is encountered as a severe problem because high resolution instrument always incorporate a certain degree of noise. In order to precisely evaluate the wafer profile, it i

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44

NISHI, Kunihiko. "Recent Activities in Semiconductor Packaging Technology." Journal of Japan Institute of Electronics Packaging 10, no. 5 (2007): 341–43. http://dx.doi.org/10.5104/jiep.10.341.

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45

Mahalingam, M. "Thermal management in semiconductor device packaging." Proceedings of the IEEE 73, no. 9 (1985): 1396–404. http://dx.doi.org/10.1109/proc.1985.13300.

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46

Nonomura, Kazutaka, Masashi Ono, Li Bo Zhou, Jun Shimizu, and Hirotaka Ojima. "Design of Digital Filters for Si Wafer Surface Profile Measurement – Noise Reduction by Lifting Scheme Wavelet Transform." Advanced Materials Research 126-128 (August 2010): 732–37. http://dx.doi.org/10.4028/www.scientific.net/amr.126-128.732.

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Recently in semiconductor industry, production of ever flatter, thinner and larger silicon wafers are required to fulfill the demands of high-density packaging and cost reduction. In geometric evaluation of Si wafers, according to SEMI (Semiconductor Equipment and Materials International) standards, the required wafer flatness approaches to the 22 nanometers by year 2016 [1]. For such application, uncertainty of measured data is encountered as a severe problem because the requirement has met the limit of available instrument in terms of resolution and reliability. In order to precisely evaluat

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47

Bluck, Terry, Chris Smith, and Paul Werbaneth. "Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation." International Symposium on Microelectronics 2018, no. 1 (2018): 000748–53. http://dx.doi.org/10.4071/2380-4505-2018.1.000748.

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Abstract Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. In fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. For these RDL barrier/seed layers, PVD cluster tools, wafer transport architectures that have been widely used since the mid-1980s, are the current Process of Record (POR) in advanced pa

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48

Lukianoff, George. "4575630 Electron-beam testing of semiconductor wafers." Microelectronics Reliability 27, no. 1 (1987): 193. http://dx.doi.org/10.1016/0026-2714(87)90737-2.

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49

Pfahl, Robert C. "Materials in Electronic Manufacturing: Electronic Packaging." MRS Bulletin 17, no. 4 (1992): 38–41. http://dx.doi.org/10.1557/s0883769400041051.

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Electronic packaging involves using an appropriate combination of conductive and dielectric materials to electrically interconnect and mechanically support electronic components in a reliable and cost-effective manner. Since the invention of the integrated circuit in 1959 and mass wave-soldering in 1958, the vast majority of electronic packaging has involved a planar substrate to which semiconductor devices in protective packages are attached by melting eutectic solder. The planar substrates or printed circuit boards (PCBs) were invented in 1940, but their widespread implementation was limited

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50

Teixeira, Ricardo C., Koen De Munck, Piet De Moor, et al. "Stress Analysis on Ultra Thin Ground Wafers." Journal of Integrated Circuits and Systems 3, no. 2 (2008): 83–89. http://dx.doi.org/10.29292/jics.v3i2.286.

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Grinding wafers is a well established process for thinning wafers down to 100 μm for use in smart cards and stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in Si wafers thinned down to ~20μm by means of an IR time-of-flight like technique. Such aggressive thinning is a requirement for high density vias interconnect, stacked die packaging and flexible electronics. We found that the thinning process used did not add significant stress value on the thinned wafer.

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