Bibliografie tematiche / Application specific instruction-set processor (ASIP)

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Letteratura scientifica selezionata sul tema "Application specific instruction-set processor (ASIP)"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 25 luglio 2025

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Articoli di riviste sul tema "Application specific instruction-set processor (ASIP)"

Imai, Masaharu, Yoshinori Takeuchi, Keishi Sakanushi, and Nagisa Ishiura. "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)." IPSJ Transactions on System LSI Design Methodology 3 (2010): 161–78. http://dx.doi.org/10.2197/ipsjtsldm.3.161.

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Sharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.

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Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Applica

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Mukherji, Rana, and Manishita Das. "System Level Modeling Methodology of Application Specific Instruction Set Processor (Asip) Using Systemc." DIU Journal of Science & Technology 7, no. 1 (2024): 44–49. https://doi.org/10.5281/zenodo.13733703.

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In recent years, the development of application specific instruction set processors (ASIP) is the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that constructing such architecture is a difficult assignment that needs skilled knowledge in distinct domains: application software development tools, processor hardware implementation, and system integration and verification. To specify the design and implementation of such systems and incorporate the functionality implemented in both hardware and software forms, we are compelled to move on from traditional Ha

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Xin, Yao, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song, and Theodore W. Berger. "An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics." IEEE/ACM Transactions on Computational Biology and Bioinformatics 12, no. 5 (2015): 1034–47. http://dx.doi.org/10.1109/tcbb.2015.2440248.

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Safaei Mehrabani, Yavar. "Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm." International Journal of Electronics Letters 7, no. 2 (2018): 154–65. http://dx.doi.org/10.1080/21681724.2018.1477182.

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Andorno, M., M. Andersen, G. Borghello, et al. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.

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Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard vers

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Zhang, Diandian, Li Lu, Jeronimo Castrillon, et al. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.

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Spinlocks are a common technique in Multi-Processor Systems-on-Chip (MPSoCs) to protect shared resources and prevent data corruption. Without a priori application knowledge, the control of spinlocks is often highly random which can degrade the system performance significantly. To improve this, a centralized control mechanism for spinlocks is proposed in this paper, which utilizes application-specific information during spinlock control. The complete control flow is presented, which starts from integrating high-level user-defined information down to a low-level realization of the control. An Ap

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Zhou, Xinbing, Yi Man, Peng Hao, et al. "ASIP Performance Enhancement by Hazard Control through Scoreboard." Micromachines 15, no. 11 (2024): 1287. http://dx.doi.org/10.3390/mi15111287.

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The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific domains, low power consumption, high flexibility and low silicon consumption. One of the challenges for DSP design is to handle problems induced by datapath acceleration. The datapath acceleration (instruction fusion, black box instructions) induces control complexities. To most efficiently utilize hardware, control challenges can be summarized as RA

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Engroff, Alian, Marcelo Romanssini, Lucas Compassi-Severo, Paulo C. C. de Aguirre, and Alessandro Girardi. "ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications." Electronics 12, no. 2 (2023): 401. http://dx.doi.org/10.3390/electronics12020401.

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The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interp

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Iwaizumi, Hiroki, Shingo Yoshizawa, and Yoshikazu Miyanaga. "A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems." VLSI Design 2013 (March 18, 2013): 1–10. http://dx.doi.org/10.1155/2013/625019.

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A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power des

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Tesi sul tema "Application specific instruction-set processor (ASIP)"

Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

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Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring

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Packiaraj, Vivek. "Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task." Thesis, Linköping University, Electronics System, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52314.

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<p>There is a lot of literature already available describing well-structured approach for embeddeddesign and implementation of Application Specific Integrated Processor (ASIP) micro processorcore.</p><p>This concept features hardware structured approach for implementation of processor core fromminimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIPprocessor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. Thereport is a well structured

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Cheung, Newton Computer Science &amp Engineering Faculty of Engineering UNSW. "Design automation methodologies for extensible processor platform." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/26118.

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This thesis addresses two ubiquitous trends in the embedded system world - the increasing importance of design turnaround time as a design metric, and the move towards closing the design productivity gap. Adopting the right choice of design approach has been recognised as an integral part of the design flow in order to meet desired characteristics such as increasing software content, satisfying the growing complexities of an application, reusing off-the-shelf components, and exploring design metrics tradeoff, which closes the design productivity gap. The importance of design turnaround time is

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Mikó, Albert. "Akcelerace aplikací pomocí specializovaných instrukcí." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255444.

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The design of specialized instructions for application specific processors is a challenging task. This thesis describes the issues of effective specification and use of specialized instructions for optimization of applications. It focuses on improvements of the outputs and usability of the semiatomatic method of selection of specialized instructions to allow the optimization of complicated applications. This method combines manual selection of instructions by marking a section of source code in the application and automatic generation of the instruction description in the modelling language.

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Šulek, Jakub. "Verifikace ASIP založena na formálních tvrzeních." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-264941.

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This thesis introduces the concept of assertion-based verifi cation of application-specifi c instruction set processors (ASIPs). The proposed design is implemented in SystemVerilog Assertions language as a part of veri fication environment created using Codasip Framework. The implemented concept is simulated in QuestaSim tool using model of Codix RISC processor. Main outcome of this thesis is the verifi cation concept usable not only on other processors, but as a part of system that automates the processor design as well.

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Vogt, Timo. "A reconfigurable application-specific instruction-set processor for trellis-based channel decoding /." Kaiserslautern : Techn. Univ. Kaiserslautern, 2008. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016537958&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.

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Shee, Seng Lin Computer Science &amp Engineering Faculty of Engineering UNSW. "ADAPT : architectural and design exploration for application specific instruction-set processor technologies." Awarded by:University of New South Wales, 2007. http://handle.unsw.edu.au/1959.4/35404.

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This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy

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Yassin, Yahya H. "ULTRA LOW POWER APPLICATION SPECIFIC INSTRUCTION-SET PROCESSOR DESIGN : for a cardiac beat detector algorithm." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9914.

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<p>High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and h

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Husár, Adam. "Implementace obecného assembleru." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2007. http://www.nusl.cz/ntk/nusl-412779.

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This thesis describes the design of the universal assembler that represents a part of the Lissom project. You will be provided with the description of the assembler architectures and their usual tasks. Special attention is paid to GNU assembler. Designed assembler consists of the fixed and the generated part. The generated part is created automatically from the description of instruction set, that is defined using architecture and instructions set description language ISAC. Using this approach, it is possible to change assembler target architecture automatically. The second part of thesis desc

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Bytyn, Andreas [Verfasser], Gerd [Akademischer Betreuer] Ascheid, and Rainer [Akademischer Betreuer] Leupers. "Efficiency and scalability exploration of an application-specific instruction-set processor for deep convolutional neural networks / Andreas Bytyn ; Gerd Ascheid, Rainer Leupers." Aachen : Universitätsbibliothek der RWTH Aachen, 2020. http://d-nb.info/1230325506/34.

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Libri sul tema "Application specific instruction-set processor (ASIP)"

Nelson, Victor P. 74AS-EVM-16: A microprogramming approach to application-specific instruction set processor design : register-transfer level design : laboratory manual no. 1. Texas Instruments, 1987.

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Liu, Dake. Embedded DSP Processor Design: Application Specific Instruction Set Processors. Elsevier Science & Technology Books, 2008.

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Embedded DSP processor design: Application specific instruction set processors. Morgan Kaufmann, 2008.

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Leupers, Rainer, and Kingshuk Karuri. Application Analysis Tools for ASIP Design: Application Profiling and Instruction-set Customization. Springer, 2014.

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Capitoli di libri sul tema "Application specific instruction-set processor (ASIP)"

Chakravarthi, Veena S., and Shivananda R. Koteshwar. "Application-Specific Instruction Set Processor." In SOC-Based Solutions in Emerging Application Domains. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-85044-8_7.

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Choi, Seung-Hyun, Neungsoo Park, Yong Ho Song, and Seong-Won Lee. "ASiPEC: An Application Specific Instruction-Set Processor for High Performance Entropy Coding." In Ubiquitous Computing Application and Wireless Sensor. Springer Netherlands, 2015. http://dx.doi.org/10.1007/978-94-017-9618-7_7.

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Wenger, Erich. "A Lightweight ATmega-Based Application-Specific Instruction-Set Processor for Elliptic Curve Cryptography." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40392-7_1.

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Karuri, Kingshuk, Rainer Leupers, Gerd Ascheid, and Heinrich Meyr. "A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03138-0_22.

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Nevezi-Strango, Dávid, Daniel Grosu, and Sorin Valcan. "The Development of an Application-Specific Instruction Set Processor Specialized on a Convolutional Neural Network Trained on MNIST." In Communications in Computer and Information Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-70248-8_8.

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Zhang, Diandian, Jeronimo Castrillon, Stefan Schürmans, Gerd Ascheid, Rainer Leupers, and Bart Vanthournout. "System-Level Analysis of MPSoCs with a Hardware Scheduler." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6034-2.ch014.

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Efficient runtime resource management in heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) for achieving high performance and energy efficiency is one key challenge for system designers. In the past years, several IP blocks have been proposed that implement system-wide runtime task and resource management. As the processor count continues to increase, it is important to analyze the scalability of runtime managers at the system-level for different communication architectures. In this chapter, the authors analyze the scalability of an Application-Specific Instruction-Set Processor (ASIP) fo

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Puusaari, Kimmo, Timo Yli-Pietilä, and Kim Rounioja. "Application Specific Instruction Set Processor for UMTS-FDD Cell Search." In Customizable Embedded Processors. Elsevier, 2007. http://dx.doi.org/10.1016/b978-012369526-0/50015-2.

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Thompson Matthew, Padget Julian, and Satoh Ken. "Describing Legal Policies as Story Tropes in Normative Systems." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2016. https://doi.org/10.3233/978-1-61499-726-9-207.

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TropICAL is a Domain Specific Language (DSL) for the description of abstract legal policies. Taking inspiration from narrative tropes, our DSL enables the creation of component &ldquo;policies&rdquo; that may be reused between case descriptions. These components are compiled to social institutions, which are realised in Answer Set Programming (ASP) code. In this way, the actions of defendant and plaintiff take the shape of a story which must conform to the rules in the ASP description. We propose the use of our DSL in a tool designed for lawyers to generate arguments for the argumentat

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Atti di convegni sul tema "Application specific instruction-set processor (ASIP)"

Cui, Songqiao, and Josep Balasch. "Configurable Loop Shuffling via Instruction Set Extensions." In 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2024. http://dx.doi.org/10.1109/asap61560.2024.00021.

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Huang, Junzhe, Qiang Dou, and Li Shen. "Extending the RISC-V Instruction Set for High Performance Data Compression Hardware Acceleration." In 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2024. http://dx.doi.org/10.1109/asap61560.2024.00035.

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Attari, Mohammad, Jesús Rodríguez Sánchez, Ove Edfors, and Liang Liu. "A 1095 pJ/b 219 Mb/s Application-specific Instruction-set Processor for Distributed Massive MIMO in 22FDX." In 2024 IEEE European Solid-State Electronics Research Conference (ESSERC). IEEE, 2024. http://dx.doi.org/10.1109/esserc62670.2024.10719451.

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Liu, Dake. "ASIP (Application Specific Instruction-set Processors) design." In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351271.

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Mazurek, Przemyslaw. "BOSON - Application-Specific Instruction Set Processor (ASIP) for Educational Purposes." In 2020 16th International Conference on Control, Automation, Robotics and Vision (ICARCV). IEEE, 2020. http://dx.doi.org/10.1109/icarcv50220.2020.9305396.

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Huang, Wei-pei, Ray C. C. Cheung, and Hong Yan. "An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation." In 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2019. http://dx.doi.org/10.1109/asap.2019.00-36.

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Hu, Jingwei, Wangchen Dai, Liu Yao, and Ray C. C. Cheung. "An application specific instruction set processor (ASIP) for the niederreiter cryptosystem." In 2018 6th International Symposium on Digital Forensic and Security (ISDFS). IEEE, 2018. http://dx.doi.org/10.1109/isdfs.2018.8355364.

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Hussain, Waqar, Xiaolin Chen, Gerd Ascheid, and Jari Nurmi. "A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing." In 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2013. http://dx.doi.org/10.1109/asap.2013.6567599.

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Fathy, Amr, Tsuyoshi Isshiki, Dongju Li, and Hiroaki Kunieda. "Custom instruction search for application specific instruction-set processor using guided simulated annealing." In 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2014. http://dx.doi.org/10.1109/apccas.2014.7032796.

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