Bibliografie tematiche / Field Programmable Gate Arrays

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Letteratura scientifica selezionata sul tema "Field Programmable Gate Arrays"

Autore: Grafiati
Pubblicato: 4 giugno 2021
Ultima modifica: 25 luglio 2025

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Articoli di riviste sul tema "Field Programmable Gate Arrays"

1

Marchal, Pierre. "Field-programmable gate arrays." Communications of the ACM 42, no. 4 (1999): 57–59. http://dx.doi.org/10.1145/299157.299594.

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Verma, H. "Field programmable gate arrays." IEEE Potentials 18, no. 4 (1999): 34–36. http://dx.doi.org/10.1109/45.796099.

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Lombardi, F. "Field Programmable Gate-Arrays." IEEE Design & Test of Computers 15, no. 1 (1998): 8–9. http://dx.doi.org/10.1109/mdt.1998.655176.

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Bhatia, Dinesh. "Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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Hurst, S. L. "Field programmable gate arrays." Microelectronics Journal 28, no. 1 (1997): 102. http://dx.doi.org/10.1016/s0026-2692(97)87854-8.

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Hurst, S. L. "Field-programmable gate arrays." Microelectronics Journal 25, no. 1 (1994): 77–78. http://dx.doi.org/10.1016/0026-2692(94)90166-x.

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Jay, Christopher. "Field programmable gate arrays." Microprocessors and Microsystems 17, no. 7 (1993): 370. http://dx.doi.org/10.1016/0141-9331(93)90058-f.

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Greene, J., E. Hamdy, and S. Beal. "Antifuse field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (1993): 1042–56. http://dx.doi.org/10.1109/5.231343.

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Leon, A. F. "Field programmable gate arrays in space." IEEE Instrumentation & Measurement Magazine 6, no. 4 (2003): 42–48. http://dx.doi.org/10.1109/mim.2003.1251482.

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10

Rose, J., A. El Gamal, and A. Sangiovanni-Vincentelli. "Architecture of field-programmable gate arrays." Proceedings of the IEEE 81, no. 7 (1993): 1013–29. http://dx.doi.org/10.1109/5.231340.

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Tesi sul tema "Field Programmable Gate Arrays"

1

Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Abstract (sommario):
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.<br>Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
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Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays." Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.

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As the logic capacity of FPGAs continues to increase with deep submicron technology, performing a full recompilation for small iterative changes in a large design is an extremely time-consuming and costly process. To address this issue, this thesis presents a new incremental placement algorithm for FPGAs named "iPlace" that significantly reduces the time required for recompilation. The iPlace algorithm is based on shifting, compaction, and annealing. Key ideas from the algorithm include a placement super-grid that is larger than the physical size of the FPGA. The super-grid allows insert
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Messa, Norman C. "Design implementation into field programmable gate arrays." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

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Niu, Jianyong. "Digital control using field programmable gate arrays." Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.

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Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.

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Карнаушенко, В. П., and А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between Field Programmable Gates Arrays (FPGA) and Application Specified Integrated Circuits (ASICs) for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.
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Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.

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Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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Libri sul tema "Field Programmable Gate Arrays"

1

Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0.

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D, Brown Stephen, ed. Field-programmable gate arrays. Kluwer Academic Publishers, 1992.

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Brown, Stephen D. Field-Programmable Gate Arrays. Springer US, 1992.

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4

1955-, Trimberger Stephen, ed. Field-programmable gate array technology. Kluwer Academic Publishers, 1994.

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5

Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Kluwer Academic Publishers, 1995.

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6

Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. PTR Prentice Hall, 1993.

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7

Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Logic Synthesis for Field-Programmable Gate Arrays. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1.

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Vuillamy, Jean-Michel. Performance enhancement in field-programmable Gate Arrays. National Library of Canada, 1991.

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9

Messa, Norman C. Design implementation into field programmable gate arrays. Naval Postgraduate School, 1991.

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10

Murgai, Rajeev. Logic Synthesis for Field-Programmable Gate Arrays. Springer US, 1995.

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Capitoli di libri sul tema "Field Programmable Gate Arrays"

1

Gu, Changyi. "Field-Programmable Gate Arrays." In Building Embedded Systems. Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-1919-5_9.

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Barkalov, Alexander, Larysa Titarenko, and Małgorzata Mazurkiewicz. "Field Programmable Gate Arrays." In Foundations of Embedded Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11961-4_4.

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de Dinechin, Florent, and Martin Kumm. "Field Programmable Gate Arrays." In Application-Specific Arithmetic. Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-42808-1_4.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Introduction to FPGAs." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_1.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Commercially Available FPGAs." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_2.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Technology Mapping for FPGAs." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_3.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Logic Block Architecture." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_4.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Routing for FPGAs." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_5.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "Flexibility of FPGA Routing Architectures." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_6.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. "A Theoretical Model for FPGA Routing." In Field-Programmable Gate Arrays. Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_7.

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Atti di convegni sul tema "Field Programmable Gate Arrays"

1

Jyothi, Vinayaka, Ashik Poojari, Richard Stern, and Ramesh Karri. "Fingerprinting Field Programmable Gate Arrays." In 2017 IEEE 35th International Conference on Computer Design (ICCD). IEEE, 2017. http://dx.doi.org/10.1109/iccd.2017.58.

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DeHon, A. "Entropy, Counting, and Programmable Interconnect." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242346.

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Pérez López, Daniel, Aitor López Hernández, Andrés Macho Ortiz, Prometheus DasMahapatra, and José Capmany Francoy. "Towards field-programmable photonic gate arrays." In Smart Photonic and Optoelectronic Integrated Circuits XXII, edited by Sailing He and Laurent Vivien. SPIE, 2020. http://dx.doi.org/10.1117/12.2551289.

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Chow, P., P. G. Gulak, and P. Chow. "A Field-Programmable Mixed-Analog-Digital Array." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242048.

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Lombardi, F., D. Ashen, Xiaotao Chen, and Wei Kang Huang. "Diagnosing Programmable Interconnect Systems for FPGAs." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242436.

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Tong Liu, Wei Kang Huang, and F. Lombardi. "Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242145.

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Vi Cuong Chan and D. M. Lewis. "Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242343.

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Lamoureux, Julien, and Steven Wilton. "Activity Estimation for Field-Programmable Gate Arrays." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311199.

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Bratt, A., and I. Macbeth. "Design and Implementation of a Field Programmable Analogue Array." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242434.

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Chan, Pak K., and Martine D. F. Schlag. "Parallel placement for field-programmable gate arrays." In the 2003 ACM/SIGDA eleventh international symposium. ACM Press, 2003. http://dx.doi.org/10.1145/611817.611825.

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Rapporti di organizzazioni sul tema "Field Programmable Gate Arrays"

1

Mumbru, Jose, George Panotopoulos, and Demetri Psaltis. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems. Defense Technical Information Center, 2004. http://dx.doi.org/10.21236/ada421336.

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Stepaniak, Michael J., Maarten Uijt de Haag, and Frank Van Graas. Field Programmable Gate Array-Based Attitude Stabilization. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada485525.

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Manohar, Rajit. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2015. http://dx.doi.org/10.21236/ada614130.

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Wawrzynek, J., and K. Asanovic. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture. Defense Technical Information Center, 2009. http://dx.doi.org/10.21236/ada519578.

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Tyler, Stephen C. The Design of a Frequency Domain Interference Excision Processor Using Field Programmable Gate Arrays. Defense Technical Information Center, 2005. http://dx.doi.org/10.21236/ada432369.

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Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas, and Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada492273.

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Manohar, Rajit. A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing. Defense Technical Information Center, 2012. http://dx.doi.org/10.21236/ada559184.

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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Office of Scientific and Technical Information (OSTI), 2011. http://dx.doi.org/10.2172/1013229.

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Don, Michael, and Mitchell Grabner. A Field-Programmable Gate Array (FPGA)-Based Instrumentation System for an Embedded Flight Controller. DEVCOM Army Research Laboratory, 2022. http://dx.doi.org/10.21236/ad1156875.

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Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada514601.

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