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Rozprawy doktorskie na temat „ASIC”

Autor: Grafiati
Data publikacji: 4 czerwca 2021
Data aktualizacji: 25 lipca 2025

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1

Lothian, Angus, Ivar Härnqvist, Adam Jakobsson, et al. "B-ASIC - Better ASIC Toolbox : En verktygslåda som förenklar design och optimering av ASIC." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167069.

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Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte var att utveckla en verktygslåda i Python och C++ för att konstruera signalbehandlade kretsar. Denna verktygslåda är tänkt att användas inom laborationer i kursen TSTE87 Applikationsspecfika integrerande kretsar vid Linköpings universitet och inom forskning för utveckling av ASIC:s. Projektet resulterade i produkten B-ASIC. B-ASIC är ett bibliotek för programmeringsspråket Python som är skrivet i Python
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Arumugam, Prakash. "Investigations into ASIC desensitization." Connect to resource, 2006. http://hdl.handle.net/1811/6036.

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Thesis (Honors)--Ohio State University, 2006.<br>Title from first page of PDF file. Document formattted into pages: contains 16 p.; also includes graphics. Includes bibliographical references (p. 16). Available online via Ohio State University's Knowledge Bank.
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Ghuman, Parminder, Salman Sheikh, Steve Koubek, Scott Hoy, and Andrew Gray. "High Rate Digital Demodulator ASIC." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609676.

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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California<br>The architecture of the High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation other than CMOS technology such as Galliu
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4

Ramsten, Johannes, and Markus Klum. "Implementation av fältbuss ASIC i FPGA." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-4523.

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<p>HMS Industrial Networks AB is in need of changing a communications solution that iscurrently based on an ASIC. This will be achieved by moving the communications solution toa FPGA with the help of the programming language VHDL. By doing this, it is possible toreduce the need for specific circuits, get a more flexible platform and thus get a cheapersolution.</p><p>This report describes a solution for how to move a network protocol from an ASIC to anFPGA. The report shows that the network slave device is working under the guidelines forthis project. This means that it is quite realistic to im
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Harrison, Andrew. "ASIC based recorders of electrophysiological signals." Thesis, University of Nottingham, 1995. http://eprints.nottingham.ac.uk/13305/.

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The ability of application specific integrated circuits (ASICs) to minimise the size and power consumption of electronic circuitry, makes their application to the design of ambulatory monitoring equipment, an attractive option. To this end, a multi-purpose mixed analogue and digital ASIC has been fabricated and incorporated into both a long-term recorder of adult heart rate (HR) and a recorder of electrophysiological signals. The adult HR recorder has been employed in a study of long-term daily HR patterns, which verified the ambulatory nature of this instrument, as well as its suitability for
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Dobson, Jonathan M. "ASIC implementations of the Viterbi Algorithm." Thesis, University of Edinburgh, 1999. http://hdl.handle.net/1842/13669.

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The Viterbi Algorithm is a popular method for decoding convolutional codes, receiving signals in the presence of intersymbol-interference, and channel equalization. In 1981 the European Telecommunications Administration (CEPT) created the Groupe Special Mobile (GSM) Committee to devise a unified pan-European digital mobile telephone standard. The proposed GSM receiver structure brings together Viterbi decoding and equilization. This thesis presents three VLSI designs of the Viterbi Algorithm with specific attention paid to the use of such modules within a GSM receiver. The first design uses a
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7

Perumalla, Anvesh Kumar. "A Genetic Algorithm for ASIC Floorplanning." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1484236480221006.

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8

Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.

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Droste, Dirk. "Realisierung eines Wellenfrontsensors mit einem ASIC." [S.l. : s.n.], 1999. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB8337986.

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10

Hussain, Waqar Muhammad. "Low Power Implantable ASIC forBio-Impedance Measurements." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-105098.

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Electrical bio-impedance can give a lot of insight into the basic physiological parameters of human body and concentration of glucose is one of those vital parameters.In order to control diabetes mellitus, it is critically essential to maintain blood glucose concentrations within the normal physiological range to avoid diabetes related complications.Consequently, accurate in-vivo and in-vitro measurement of glucose concentration in physiological uids has long been a central goal of bio sensor research.The correlation between glucose levels in human body and bio-impedance is more potently descr
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11

Khawaja, Jaleed Ejaz. "Asic gas sensors based on ratiometric principles." Thesis, University of Warwick, 2009. http://wrap.warwick.ac.uk/2230/.

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The wide-scale usage of VOCs in industrial processes requires monitoring the concentrations of these vapours to keep a safe operating environment. Most combustible hydrocarbons can be ignited as a gas-air mixture in the range of 0.5% to 15% by volume. This has led to the development of several portable air quality monitoring instruments. However, the high costs and lack of durability of these instruments has remained an issue to be addressed. This PhD thesis reports on the development and characterization of a novel low cost smart gas sensor technology adaptable for use in a portable instrumen
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12

Guzmán, Jesús García. "Smart ratiometric ASIC chip for VOC monitoring." Thesis, University of Warwick, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422141.

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13

Le, Thai Q. (Thai Quoc) Carleton University Dissertation Engineering Electrical. "Application specific integrated circuit (ASIC) hardwired microcontroller." Ottawa, 1991.

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Bryksin, Vladyslav Sergeevich. "ASIC life extension through hardware patch interfaces." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1464873.

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Thesis (M.S.)--University of California, San Diego, 2009.<br>Title from first page of PDF file (viewed July 2, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 46-47).
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15

Paschou, Michail. "ASIC implementation of LSTM neural network algorithm." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254290.

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LSTM neural networks have been used for speech recognition, image recognition and other artificial intelligence applications for many years. Most applications perform the LSTM algorithm and the required calculations on cloud computers. Off-line solutions include the use of FPGAs and GPUs but the most promising solutions include ASIC accelerators designed for this purpose only. This report presents an ASIC design capable of performing the multiple iterations of the LSTM algorithm on a unidirectional and without peepholes neural network architecture. The proposed design provides arithmetic level
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16

CHENG, WEISHUAI. "Development of ASIC for SiPM sensor readout." Doctoral thesis, Politecnico di Torino, 2020. http://hdl.handle.net/11583/2842529.

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17

Mehrez, Fatima. "Design and test of a readout ASIC for a SiPM - based camera : ALPS (ASIC de lecture pour un photodétecteur SiPM)." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT131/document.

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Cette thèse est la R&amp;D de l’électronique de front-end destinée à la camera de deuxième génération du télescope de grande taille LST de projet CTA, étant basée sur les détecteurs de type SiPM. Cette étude rassemble des équipes du LAPP, de l’université de Padoue, de l’INFN et du MPI de Munich. La première partie de cette thèse porte sur les tests de caractérisations d’une matrice de 16 SiPMs fabriquée par Hamamatsu. Les résultats de ces tests ont souligné les avantages qui pourraient être apportés par l’utilisation de tels détecteurs. Un cahier des charges pour l’électronique a été défini à
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18

Ehliar, Andreas. "Performance driven FPGA design with an ASIC perspective." Doctoral thesis, Linköpings universitet, Datorteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16372.

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FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be
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19

Sadiq, Ejaz. "Short Message Network-On-Chip Interconnect for ASIC." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175761.

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The rise of large scale integration has resulted in large number of processing elements/cores on a single ASIC. Thus an efficient interconnect scheme between the different processing elements and interfaces is required. Bus based interconnect poses problems such as non-scalability. This thesis explores the Network-on-Chip (NOC) as a global interconnect scheme on a state of the art ASIC. Different On-chip interconnect techniques proposed by the academia/industry are summarized and Design space exploration of NOC schemes is performed. A Network-on-Chip interconnect, primarily utilized for short
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20

Han, Tony. "SWASAD Smith & Waterman-algorithm-specific ASIC design /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16391.pdf.

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21

Dvořák, Vojtěch. "Implementace výpočtu FFT v obvodech FPGA a ASIC." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-220087.

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The aim of this thesis is to design the implementation of fast Fourier transform algorithm, which can be used in FPGA or ASIC circuits. Implementation will be done in Matlab and then this form of implementation will be used as a reference model for implementation of fast Fourier transform algorithm in VHDL. To verify the correctness ofdesign verification enviroment will be created and verification process wil be done. Program that will generate source code for various parameters of the module performing a fast Fourier transform will be created in the last part of this thesis.
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22

DUTTA, MADHULIKA. "DESIGN OF AN INTEGRATED DETECTION SYSTEM FOR THE CHARACTERIZATION OF A BIOSENSOR ARRAY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1054128572.

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Olsson, Martin. "Portning och utökning av processor för ASIC och FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18250.

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<p>In this master thesis, the possibilities of customizing a low-cost microprocessor with the purpose of replacing an existing microprocessor solution are investigated. A brief survey of suitable processors is carried out wherein a replacement is chosen. The replacement processor is then analyzed and extended with accelerators in order to match set requirements.</p><p>The result is a port of the processor Lattice Mico32 for the FPGA curcuit Xilinx Virtex-5 which replaces an earlier solution using Xilinx MicroBlaze. To reach the set requirements, accelerators for floating point arithmetics and
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Yesil, Soner. "A High-speed Asic Implementation Of The Rsa Cryptosystem." Master's thesis, METU, 2003. http://etd.lib.metu.edu.tr/upload/3/1124783/index.pdf.

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This thesis presents the ASIC implementation of the RSA algorithm, which is one of the most widely used Public Key Cryptosystems (PKC) in the world. In RSA Cryptosystem, modular exponentiation of large integers is used for both encryption and decryption processes. The security of the RSA increases as the number of the bits increase. However, as the numbers become larger (1024-bit or higher) the challenge is to provide architectures, which can be implemented in hardware, operate at high clock speeds, use a minimum of resources and can be used in real-time
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Venditti, Michael B. "Receiver, transmitter, and ASIC design for optoelectronic-VLSI applications." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84444.

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In modern digital systems, off-chip and intra-chip electrical interconnections suffer from a multitude of limitations as integrated circuits (ICs) continue to grow in size and processing capacity. Optical interconnects are capable of meeting the increasing I/O bandwidth needs in these systems. Optoelectronic-VLSI (OE-VLSI) technology incorporates optical I/O with ICs through the integration of arrays of optoelectronic devices with on-chip receiver and transmitter circuits. These optical I/Os are intended to replace or complement electrical interconnects for off-chip connections, and for
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Simpson, Zachary P. "Optimization of RSA Cryptography for FPGA and ASIC Applications." Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1609146/.

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RSA cryptography is one of the most widely used cryptosystems in the world. FPGA/ASIC implementations for the classic RSA cryptosystem have high resource utilization due to the use of the Extended Euclid's algorithm for MOD inverse generation, the MOD exponent operation for encryption and decryption, and through non finite-field arithmetic. This thesis translates the RSA cryptosystem into the finite-field domain of arithmetic which greatly increases the range of encryption and decryption keys and replaces the MOD exponent with a multiplication. A new algorithm, the SPX algorithm, is presented
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Zuo, Yongbo. "Fair Comparison of ASIC Performance for SHA-3 Finalists." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/33446.

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In the last few decades, secure algorithms have played an irreplaceable role in the protection of private information, such as applications of AES on modems, as well as online bank transactions. The increasing application of secure algorithms on hardware has made implementations on ASIC benchmarks extremely important. Although all kinds of secure algorithms have been implemented into various devices, the effects from different constraints on ASIC implementation performance have never been explored before. In order to analyze the effects from different constraints for secure algorithms, SHA-3
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Gilda, Shubham. "ASIC design to monitor current for low frequency applications." University of Cincinnati / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1291390501.

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KUGATHASAN, RAMSHAN. "Low-Power Mixed-Signal ASIC for Cryogenic SiPM Readout." Doctoral thesis, Politecnico di Torino, 2020. http://hdl.handle.net/11583/2842523.

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Suikkanen, E. (Essi). "Detection algorithms and ASIC designs for MIMO–OFDM downlink receivers." Doctoral thesis, Oulun yliopisto, 2017. http://urn.fi/urn:isbn:9789526215013.

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Abstract Future wireless systems will require high data rate with low transmit and processing power consumption. A combination of multiple-input multiple-output (MIMO) transmission with orthogonal frequency division multiplexing (OFDM) is a promising approach for offering better performance in terms of the capacity and quality of service (QoS). The detector in the wireless receiver is one of the highest power consuming parts. In order to minimize the power consumption, it is desirable for the detector to be able to change the detection algorithm to suit the channel conditions. In this thesis w
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31

Dulipovici, Andrei. "Signatures des circuits ASIC - approche pour détermination des pannes systématiques." Mémoire, École de technologie supérieure, 2011. http://espace.etsmtl.ca/886/1/DULIPOVICI_Andrei.pdf.

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Ce mémoire explore diverses stratégies de dépistage des pannes systématiques dans les circuits VLSI s’appuyant sur la notion de signatures construites à partir des erreurs détectées par les bascules des circuits sous test. Faisant l'hypothèse que les noeuds d’un circuit et la surface qu’ils occupent sont reliés à l’apparition des pannes dans une puce, on peut calculer la probabilité d’une panne systématique et la signature de défectuosités spécifiques de cette puce. En créant différentes signatures par l’utilisation des différentes informations, le projet analyse l’apport des information
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Murphy, Julian. "Standard cell and full custom power-balanced logic : ASIC implementation." Thesis, University of Newcastle Upon Tyne, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.533690.

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Auras, Dominik [Verfasser], Gerd [Akademischer Betreuer] Ascheid, and Andreas [Akademischer Betreuer] Burg. "MIMO Detector ASIC Design / Dominik Auras ; Gerd Ascheid, Andreas Burg." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/116249963X/34.

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Nygård, Skalman Jonas. "CO2 Sensor Core on FPGA : ASIC prototyping and cost estimates." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-35963.

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Demand of CO2 gas sensors is expected to continue to increase in the foreseeable future, due to an increasing awareness of air pollution and fossil fuel emissions. A truly low cost and accurate NDIR sensor has the potential of greatly benefiting the environment by an increased human awareness due to CO2 measurements. In the objective to reach these goals, a CO2 sensor core on an ASIC needs to be investigated. In this study an ASIC prototype design is tested on an FPGA and evaluated towards logic resource requirements, power analysis and estimated cost impacts towards a full ASIC. The results s
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Green, Forrest Oliver Reece. "ALA ASIC : a standard cell library for Asynchronous Logic Automata." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/61160.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 83-84).<br>This thesis demonstrates a hardware library with related tools and designs for Asynchronous Logic Automata (ALA) gates in a generic 90nm process development kit that allows a direct one-to-one mapping from software to hardware. Included are basic design tools to enable writing ALA software, the necessary hardware designs for implementation, and simulation techniques for quickly verifyi
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Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.

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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where re
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Lin, Cheng-Hsien Kenny. "An ASIC application for DNA sequencing by Smith-Waterman algorithm (DNASSWA) /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe18716.pdf.

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Mahnke, Torsten. "Low power ASIC design using voltage scaling at the logic level." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=970311974.

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Demirci, Kemal Safak. "Chemical microsystem based on integration of resonant microsensor and CMOS ASIC." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41182.

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The main topic of this thesis is the development of a chemical microsystem based on integration of a silicon-based resonant microsensor and a CMOS ASIC for portable sensing applications. Cantilever and disk-shape microresonators have been used as mass-sensitive sensors. Based on the characteristics of the microresonators, CMOS integrated interface and control electronics have been implemented. The CMOS ASIC utilizes the self-oscillation method, which incorporates the microresonator in an amplifying feedback loop as the frequency determining element. In this manner, the ASIC includes a main fee
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McIntosh, James Alexander. "Implementation of an ASIC for detector instrumentation in nuclear physics applications." Thesis, University of Edinburgh, 1996. http://hdl.handle.net/1842/1781.

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A prototype ASIC (EFT1) for silicon strip detector instrumentation has been designed and tested. The ASIC design contains the electronics necessary for preamplification, shaping, hit detection, and data readout control. The specific­ ation of the ASIC makes it suitable for charged particle spectroscopy applications with the implementation of multiple channels on a single chip reducing the cost compared to expensive discrete instrumentation. The ASIC contains features which have not been implemented before, or are at least unusual, on integrated instrumentation such as the ability to select two
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McMahon, Michael, Albert Rhoads, Frank Winter, and Graham Pierson. "A VERSATILE PROGRAMMABLE FUNCTION RF ASIC FOR SPACE-BASED RF SYSTEMS." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608302.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>A programmable RF ASIC is described which provides most of the RF functions within a next generation S-band transponder for space applications. The unique 18-contact LCC device can be programmed to perform a variety of RF and analog functions. This single space qualified high speed bipolar "function toolbox" is used in 39 locations throughout the transponder to provide a flexible radio architecture. The ASIC design process, internal electrical design, circuit appl
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Ke, Chen-Maih, and 柯清邁. "ASIC implementationof DCT." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/95414103571037761257.

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碩士<br>義守大學<br>電子工程學系<br>88<br>With the significant property of high signal density, discrete cosine transform (DCT) has been applied in many fields of digital signal processing. The design of the DCT or IDCT chips need to consider several important factors such as the chip area, running frequency and delay time. In this paper, we develop an architectures for DCT computation and compared with architectures that other authors presented before. The ASIC implementation for these DCT architectures is carry out by using Verilog hardware description language to synthesis the cell-based and an Altera
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Adarsha, Rao S. J. "Polymorphic ASIC : For Video Decoding." Thesis, 2013. http://etd.iisc.ac.in/handle/2005/3291.

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Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degr
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Adarsha, Rao S. J. "Polymorphic ASIC : For Video Decoding." Thesis, 2013. http://hdl.handle.net/2005/3291.

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Video applications are becoming ubiquitous in recent times due to an explosion in the number of devices with video capture and display capabilities. Traditionally, video applications are implemented on a variety of devices with each device targeting a specific application. However, the advances in technology have created a need to support multiple applications from a single device like a smart phone or tablet. Such convergence of applications necessitates support for interoperability among various applications, scalable performance meet the requirements of different applications and a high degr
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邱志豪. "An Economic Evaluator for ASIC Development." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/51823616215903670442.

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碩士<br>中華大學<br>電機工程研究所<br>86<br>Cost, quality, and time to market are the basic constraints of any design project. The costs developing a ASIC include design costs, production costs, and test costs. Costs of components are sensitive to competition. For example, changing cost by $1 may change list price by $3~$4. Without understanding the relationship of cost to list price the component designer may not understand the impact on list price of adding, deleting, or replacing components. 　　The feature of eletronic products is high volume and short lifetime. The short lifetimes have made it increasin
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Philipp, Torsten Scarbata Gerd. "Layoutsynthese von Datenwegstrukturen für den ASIC-Entwurf /." 1991. http://www.gbv.de/dms/ilmenau/toc/019694709.PDF.

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He, Yi-Ru, and 何宜儒. "Buffer Insertion for ASIC and FPGA Designs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/51612808809154222102.

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碩士<br>國立清華大學<br>資訊工程學系<br>95<br>With the technology process going into nanometer regime, the interconnect delay is a crucial determining factor of circuit performance in modern VSLI designs. Buffer insertion is one of the effective technique to improve the circuit performance. We explore two different problems related to buffer insertion in ASIC and FPGA designs in this thesis. In modern ASIC designs, a large number of buffers need to be inserted to a large number of nets to improve performance and/or signal integrity. These buffers increase the power consumption and occupy silicon area. So i
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Mlynek, Mario Beierke Stefan. "Entwicklung und Validierung von ASIC-Testsystemen am Beispiel eines zu entwickelnden Rapid Prototyping Testsystems für einen RFIDAutomotive Reader ASIC /." 2008. http://www.gbv.de/dms/ilmenau/abs/564558451mlyne.txt.

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Yu, Zhengtao. "Rotary clock based high-frequency ASIC design methodology." 2007. http://www.lib.ncsu.edu/theses/available/etd-10252007-214239/.

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Hsiao, Yi-Mao, and 蕭詣懋. "High Speed ASIC Design for IPv6 Routing Lookup." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/29901660472776506666.

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碩士<br>國立中正大學<br>電機工程所<br>94<br>For the IP-based network today, there are three main issues of router design— link speed, router performance, and routing lookup. Routing lookup is a bottleneck inside a router. With the growth of Internet users and services, IP address has been exhaustedly used. In order to solve this problem of exhaustion, the quick solution like CIDR is presented, and the future will be IPv6. In this paper, a routing lookup system for IPv6 is presented. The system is composed of routing lookup ASIC and off-chip memory set. The off-chip memory set is a two-level hierarchical
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