Zaloguj się

Gotowe bibliografie tematyczne / Complementary Metal-Oxide-Semiconductor (CMOS) Technology / Artykuły w czasopismach

Kliknij ten link, aby zobaczyć inne rodzaje publikacji na ten temat: Complementary Metal-Oxide-Semiconductor (CMOS) Technology.

Artykuły w czasopismach na temat „Complementary Metal-Oxide-Semiconductor (CMOS) Technology”

Autor: Grafiati

Data publikacji: 3 czerwca 2025

Data aktualizacji: 31 lipca 2025

Utwórz poprawne odniesienie w stylach APA, MLA, Chicago, Harvard i wielu innych

Wybierz rodzaj źródła:

Sprawdź 50 najlepszych artykułów w czasopismach naukowych na temat „Complementary Metal-Oxide-Semiconductor (CMOS) Technology”.

Przycisk „Dodaj do bibliografii” jest dostępny obok każdej pracy w bibliografii. Użyj go – a my automatycznie utworzymy odniesienie bibliograficzne do wybranej pracy w stylu cytowania, którego potrzebujesz: APA, MLA, Harvard, Chicago, Vancouver itp.

Możesz również pobrać pełny tekst publikacji naukowej w formacie „.pdf” i przeczytać adnotację do pracy online, jeśli odpowiednie parametry są dostępne w metadanych.

Przeglądaj artykuły w czasopismach z różnych dziedzin i twórz odpowiednie bibliografie.

1

Xu, Haoran, Jianghua Ding, and Jian Dang. "Design and Characteristics of CMOS Inverter based on Multisim and Cadence." Journal of Physics: Conference Series 2108, no. 1 (2021): 012034. http://dx.doi.org/10.1088/1742-6596/2108/1/012034.

Pełny tekst źródła

Streszczenie:

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF cir

Style APA, Harvard, Vancouver, ISO itp.

2

Parameswaran, M., Lj Ristic, A. C. Dhaded, H. P. Baltes, W. Allegretto, and A. M. Robinson. "Fabrication of microbridges in standard complementary metal oxide semiconductor technology." Canadian Journal of Physics 67, no. 4 (1989): 184–89. http://dx.doi.org/10.1139/p89-032.

Pełny tekst źródła

Streszczenie:

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by fir

Style APA, Harvard, Vancouver, ISO itp.

3

Abbas, b. NOORI. "Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles." INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY RESEARCH AND ANALYSIS 07, no. 03 (2024): 1238–43. https://doi.org/10.5281/zenodo.10851659.

Pełny tekst źródła

Streszczenie:

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operati

Style APA, Harvard, Vancouver, ISO itp.

4

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

Pełny tekst źródła

Streszczenie:

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semi

Style APA, Harvard, Vancouver, ISO itp.

5

Sardar, Rupam, Sudip Ghosh, and Bimal Datta. "Designing Half-Adder with CMOS Technology using Artificial Neural Network with Verilog Implementation." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 03 (2024): 1–9. http://dx.doi.org/10.55041/ijsrem29025.

Pełny tekst źródła

Streszczenie:

In this study we want to design a Half-Adder with the help of Artificial Neural Network and design will be made by Complementary metal oxide semiconductor(CMOS).When we design any COMS circuit always we keep in mind that should be in minimum at cost .In this study we have used multi layer ANN to design the circuit. In our study neurons are treated like transistors and weights are used to adjust the value; like negative value as an inverter. Keywords: Half Adder, Complementary Metal Oxide Semiconductor, Artificial Neural Network, Verilog HDL

Style APA, Harvard, Vancouver, ISO itp.

6

Weng, Chun Jen. "Etching Process Effects of CMOS Transistor Gate Manufacturing Nanotechnology Fabrication Integration." Applied Mechanics and Materials 83 (July 2011): 91–96. http://dx.doi.org/10.4028/www.scientific.net/amm.83.91.

Pełny tekst źródła

Streszczenie:

As the nanotechnology gate is scaling down, the fabrication technology of gate spacer for CMOS transistor becomes more critical in manufacturing processes. For CMOS technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. A sidewall spacer patterning technology yields critical dimension variations of minimum-sized features much smaller than that achieved by optical Complementary Metal–Oxide–Semiconductor (CMOS) fabrication processes integration. The present study is to overcome the fabricati

Style APA, Harvard, Vancouver, ISO itp.

7

Li, Yucheng, Shiqi Zhang, and Jianjun Song. "A Germanium Based Quantum Well Complementary Metal-Oxide-Semiconductor Transistor." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (2022): 1245–55. http://dx.doi.org/10.1166/jno.2022.3308.

Pełny tekst źródła

Streszczenie:

Germanium is recognized as an important prospective material due to its great carrier mobility. The current design and research of GeSn channel field effect transistors are far from mature. Especially the complementary Ge-based CMOS device is rarely reported. It significantly limits the application and development of Ge-based MOS technology. Based on this, a Si0.2Ge0.66Sn0.14-Ge0.82Sn0.18-Ge double heterojunction quantum well NMOS and PMOS are proposed. Benefiting from the high carrier mobility of Ge and the increased mobility brought by the quantum well, the proposed NMOS and PMOS device achi

Style APA, Harvard, Vancouver, ISO itp.

8

Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

Pełny tekst źródła

Streszczenie:

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-

Style APA, Harvard, Vancouver, ISO itp.

9

Maity, N. P., Reshmi Maity, and Srimanta Baishya. "Design of a Low Noise Active Pixel Sensor using Complementary Metal-Oxide-Semiconductor Technology." Science & Technology Journal 4, no. 2 (2016): 130–36. http://dx.doi.org/10.22232/stj.2016.04.02.07.

Pełny tekst źródła

Streszczenie:

In this paper, our focus is on designing of complementary metal-oxide-semiconductor (CMOS) photodiode based active pixel sensor (APS) and performance analysis and achievements for CMOS image sensor. Different important design parameters like photocurrent, conversion gain, conversion factor, dynamic range, readout speed, and quantum efficiency have been calculated. Noise is also considered for the design at different phase of operations of CMOS APS. Various design parameters of our design are computed and compared with simulated results. Noise calculation shows that the pixel noise is dominated

Style APA, Harvard, Vancouver, ISO itp.

10

Awan, Waseem. "Digital Modulator using Digitally Programmable Complementary metal–oxide–semiconductor Differential Voltage Current Conveyor." Academic Journal of Research and Scientific Publishing 6, no. 65 (2024): 21–40. http://dx.doi.org/10.52132/ajrsp.e.2024.65.2.

Pełny tekst źródła

Streszczenie:

This study aims to Developing a digital modulation system using a new technology and idea, which is the digitally programmable CMOS (Complementary metal–oxide–semiconductor), Integrate the CMOS DVCC circuit as a modulator in the communication systems, as will be explained in chapter 3, Finally, simulate this new idea in communication by using a simulation program, which is PSpice software, and analyzing the results. By focusing on How to use digital programmable CMOS (Complementary Metal–Oxide–Semiconductor) in a communication system as a digital modulator, Verifying the effectiveness of the s

Style APA, Harvard, Vancouver, ISO itp.

11

Awang Salleh, Dayang Nur Salmi Dharmiza, and Rohana Sapawi. "A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes." Applied Mechanics and Materials 833 (April 2016): 135–39. http://dx.doi.org/10.4028/www.scientific.net/amm.833.135.

Pełny tekst źródła

Streszczenie:

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

Style APA, Harvard, Vancouver, ISO itp.

12

Yoon, Daseul, Ji-Hoon Kim, and Sung Min Park. "Complementary Metal-Oxide-Semiconductor Symmetric Current-Conveyor Transimpedance Amplifier." Journal of Nanoscience and Nanotechnology 20, no. 8 (2020): 4793–98. http://dx.doi.org/10.1166/jnn.2020.17808.

Pełny tekst źródła

Streszczenie:

This paper presents a novel symmetric current-conveyor transimpedance amplifier (SCC-TIA) implemented in a 0.13-μm CMOS technology for the applications of LiDAR systems, where a modifiedcascode configuration is newly proposed for input current buffer to deliver the photo-currents to the following voltage-mode inverter TIA without signal loss. Measured results of the proposed SCC-TIA demonstrate 69-dBΩ transimpedance gain, 410-MHz bandwidth, 13-pA/sqrt (Hz) average noise current spectral density, and 20-mW power dissipation from a single 1.2-V supply. Chip core occupies the area of 280×130 μm2.

Style APA, Harvard, Vancouver, ISO itp.

13

Lee, Kitae, Sihyun Kim, Daewoong Kwon, and Byung-Gook Park. "Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation." Applied Sciences 10, no. 14 (2020): 4977. http://dx.doi.org/10.3390/app10144977.

Pełny tekst źródła

Streszczenie:

Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed a

Style APA, Harvard, Vancouver, ISO itp.

14

Thakur, Randhir P. S., Yuanning Chen, Edward H. Poindexter, and Rajendra Singh. "Silicon-Based Ultrathin Dielectrics." Electrochemical Society Interface 8, no. 2 (1999): 20–23. http://dx.doi.org/10.1149/2.f05992if.

Pełny tekst źródła

Streszczenie:

The phenomenal sustained growth of the electronics industry in the last three decades is primarily due to the success of silicon integrated circuit technology. As compared to any other technology, complementary metal-oxide silicon (CMOS) transistor based integrated circuits have dominated the field of semiconductor manufacturing.

Style APA, Harvard, Vancouver, ISO itp.

15

Roy, Spandan. "Design of CMOS Circuit Based on NAND Function at 150nm Channel Length for Low-Power and High-Speed IC Fabrication." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (2022): 2305–8. http://dx.doi.org/10.22214/ijraset.2022.44299.

Pełny tekst źródła

Streszczenie:

Abstract: In this paper the low-power and high-speed design approach of one Complementary Metal Oxide Semiconductor (CMOS) circuit based on NAND function has been reported. The CMOS design methodology has been followed to construct the circuit. The design has been carried out at 150 nm channel length of Metal Oxide Semiconductor (MOS) transistor. Average power consumption and gate delay of the circuit has been measured. Power-delay product (PDP) of the circuit has been calculated for optimized operation. The simulation of the circuit has been carried out with the help of Tanner SPICE (T-SPICE)

Style APA, Harvard, Vancouver, ISO itp.

16

Ko, Ji Wang, and Woo Young Choi. "Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits." Journal of Nanoscience and Nanotechnology 20, no. 7 (2020): 4176–81. http://dx.doi.org/10.1166/jnn.2020.17790.

Pełny tekst źródła

Streszczenie:

Monolithic-three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) hybrid reconfigurable logic (RL) circuits are compared and analyzed with CMOS-only RL ones in the 130-nm CMOS technology node. M3D CMOS-NEM hybrid RL circuits are superior to CMOS-only ones in terms of power consumption and signal transfer speed thanks to the NEM memory switches. As well as in the routing part, it has many advantages in the logic part following the switch.

Style APA, Harvard, Vancouver, ISO itp.

17

Notario-Estévez, Almudena, Xavier López, and Coen de Graaf. "Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)." Dalton Transactions 50, no. 16 (2021): 5540–51. http://dx.doi.org/10.1039/d1dt00731a.

Pełny tekst źródła

Streszczenie:

This computational study presents the molecular conduction properties of polyoxovanadates V<sub>6</sub>O<sub>19</sub> (Lindqvist-type) and V<sub>18</sub>O<sub>42</sub>, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

Style APA, Harvard, Vancouver, ISO itp.

18

Yang, Lung-Jieh, Wei-Cheng Wang, Chandrashekhar Tasupalli, Balasubramanian Esakki, and Mahammed Inthiyaz Shaik. "Sensors on Flapping Wings (SOFWs) Using Complementary Metal–Oxide–Semiconductor (CMOS) MEMS Technology." Eng 6, no. 1 (2025): 15. https://doi.org/10.3390/eng6010015.

Pełny tekst źródła

Streszczenie:

This article presents a framework of using MEMS sensors to investigate unsteady flow speeds of a flapping wing or the new concept of sensors on flapping wings (SOFWs). Based on the implemented self-heating flow sensor using U18 complementary metal–oxide–semiconductor (CMOS) MEMS foundry provided by the Taiwan Semiconductor Research Institute (TSRI), the compact sensing region of the flow sensor was incorporated for in situ diagnostics of biomimetic flapping issues. The sensitivity of the CMOS MEMS flow sensor, packaged with a parylene coating of 10 μm thick to prolong the lifetime, was observe

Style APA, Harvard, Vancouver, ISO itp.

19

Shen, Chih-Hsiung, Yun-Ying Yeh, and Chi-Feng Chen. "A Thermopile Device with Subwavelength Structure by CMOS-MEMS Technology." Applied Sciences 9, no. 23 (2019): 5118. http://dx.doi.org/10.3390/app9235118.

Pełny tekst źródła

Streszczenie:

Besides the application of the photonic crystal for the photodetector in the visible range, the infrared devices proposed with subwavelength structure are numerically and experimentally investigated thoroughly for infrared radiation sensing in this research. Several complementary metal oxide semiconductor (CMOS) compatible thermopiles with subwavelength structure (SWS) are proposed and simulated by the FDTD method. The proposed thermopiles are fabricated by the 0.35 μm 2P4M CMOS-MEMS process in TSMC (Taiwan Semiconductor Manufacturing Company). The measurement and simulation results show that

Style APA, Harvard, Vancouver, ISO itp.

20

Ghanim, Thiab Hasan, Jadu Ali Kamil, and Hlal Mutlaq Ali. "Design of current controlled instrumental amplifier by using complementary metallic oxide semiconductor technology." Design of current controlled instrumental amplifier by using complementary metallic oxide semiconductor technology 29, no. 2 (2023): 652–57. https://doi.org/10.11591/ijeecs.v29.i2.pp652-657.

Pełny tekst źródła

Streszczenie:

In this paper, a complementary metal oxide semiconductor (CMOS) instrumental amplifier was designed and implemented in order to provide the possibility of controlling the current and voltage gain. The proposed instrumentation amplifier consists of three conveyors with active resistor. The parasitic resistance value (Rx) was reduced with a large bandwidth level in addition to achieving a high common mode rejection ratio (CMRR). Simulation was performed by using 0.35 µm CMOS technology by using the advanced design system (ADS) software. The results obtained prove that the proposed circuit

Style APA, Harvard, Vancouver, ISO itp.

21

Pilipenka, U. A., V. A. Saladukha, H. A. Siarheichyk, and D. U. Shestouski. "Impact Produced by Recrystallization of Mechanically Destroyed Layer on Planar Side of Silicon Wafer Upon Electrical Parameters of CMOS Microcircuits." Doklady BGUIR 22, no. 3 (2024): 21–27. http://dx.doi.org/10.35596/1729-7648-2024-22-3-21-27.

Pełny tekst źródła

Streszczenie:

The influence of recrystallization of a mechanically damaged layer on the working side of a silicon wafer using rapid heat treatment (1000 °C, 20 s) on the electrical parameters of complementary metal-oxide-semiconductor microcircuits has been established. The analyzed characteristics of n- and p-channel transistors were selected: drain current from the gate voltage when diode-connected; output characteristics at various gate voltages; drain current from the drain voltage without applying potential to the gate; percentage of yield of suitable products. These parameters were compared with micro

Style APA, Harvard, Vancouver, ISO itp.

22

Zlatanski, M., W. Uhring, J. P. Le Normand, C. V. Zint, and D. Mathiot. "Streak camera in standard (Bi)CMOS (bipolar complementary metal-oxide-semiconductor) technology." Measurement Science and Technology 21, no. 11 (2010): 115203. http://dx.doi.org/10.1088/0957-0233/21/11/115203.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

23

Azadmousavi, Tayebeh, and Ebrahim Ghafar-Zadeh. "Complementary Metal–Oxide–Semiconductor-Based Magnetic and Optical Sensors for Life Science Applications." Sensors 24, no. 19 (2024): 6264. http://dx.doi.org/10.3390/s24196264.

Pełny tekst źródła

Streszczenie:

Optical and magnetic sensing methods are integral to both research and clinical applications in biological laboratories. The ongoing miniaturization of these sensors has paved the way for the development of point-of-care (PoC) diagnostics and handheld sensing devices, which are crucial for timely and efficient healthcare delivery. Among the various competing sensing and circuit technologies, CMOS (complementary metal–oxide–semiconductor) stands out due to its distinct cost-effectiveness, scalability, and high precision. By leveraging the inherent advantages of CMOS technology, recent developme

Style APA, Harvard, Vancouver, ISO itp.

24

Sardar, Rupam. "2:1 Multiplexer, 1:2 De-multiplexer,2:4 Decoder and 4:2 Encoder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 03 (2024): 1–11. http://dx.doi.org/10.55041/ijsrem29098.

Pełny tekst źródła

Streszczenie:

The goal of this project is to create a De-multiplexer gate using a complementary metal oxide semiconductor (CMOS) and an artificial neural network.When designing any COMS circuit, we always keep in mind that the lowest possible cost should be the aim.In this work, the circuit was designed using a multilayer artificial neural network. We utilize weights to alter the value and treat negative values as inverters and neurons as transistors in our work.We are also developing Verilog-HdL code to easily apply the De-multiplexer for experimenting with an artificial neural network and set weights to a

Style APA, Harvard, Vancouver, ISO itp.

25

Hasan, Ghanim Thiab, Kamil Jadu Ali, and Ali Hlal Mutlaq. "Design of current controlled instrumental amplifier by using complementary metallic oxide semiconductor technology." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 2 (2023): 652. http://dx.doi.org/10.11591/ijeecs.v29.i2.pp652-657.

Pełny tekst źródła

Streszczenie:

<p>In this paper, a complementary metal oxide semiconductor (CMOS) instrumental amplifier was designed and implemented in order to provide the possibility of controlling the current and voltage gain. The proposed instrumentation amplifier consists of three conveyors with active resistor. The parasitic resistance value (Rx) was reduced with a large bandwidth level in addition to achieving a high common mode rejection ratio (CMRR). Simulation was performed by using 0.35μm CMOS technology by using the advanced design system (ADS) software. The results obtained prove that the proposed circui

Style APA, Harvard, Vancouver, ISO itp.

26

Rajesh, Durgam, Subramanian Tamil, Nikhil Raj, and Bharti Chourasia. "Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier." Bulletin of Electrical Engineering and Informatics 11, no. 2 (2022): 765–71. http://dx.doi.org/10.11591/eei.v11i2.3306.

Pełny tekst źródła

Streszczenie:

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a

Style APA, Harvard, Vancouver, ISO itp.

27

Rajesh, Durgam, Tami Subramanian, Raj Nikhil, and Chourasia Bharti. "Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier." Bulletin of Electrical Engineering and Informatics 11, no. 2 (2022): 765–71. https://doi.org/10.11591/eei.v11i2.3306.

Pełny tekst źródła

Streszczenie:

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a

Style APA, Harvard, Vancouver, ISO itp.

28

Reid, Dave, Campbell Millar, Scott Roy, et al. "Enabling cutting-edge semiconductor simulation through grid technology." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1897 (2009): 2573–84. http://dx.doi.org/10.1098/rsta.2009.0031.

Pełny tekst źródła

Streszczenie:

The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS p

Style APA, Harvard, Vancouver, ISO itp.

29

You, Haolin. "Ferroelectric HfO2: a promising material for next-generation ferroelectric memory devices." Applied and Computational Engineering 7, no. 1 (2023): 1–7. http://dx.doi.org/10.54254/2755-2721/7/20230306.

Pełny tekst źródła

Streszczenie:

Recently, ferroelectric material is playing a more and more important role in the applications of semiconductor devices, especially in random access memory(RAM) devices, and transistors. Compared with traditional flash memories, FRAMs have advantages such as low operation voltage, a huge number of writes, non-volatile properties, and high write speed. However, in the early stage, the main materials used to produce FRAMs are perovskites with crystal structures. Those materials like PbTiO3/PbZr0.3Ti0.7O3 are restricted by the size and the complementary-metal-oxide-semiconductor (CMOS) technology

Style APA, Harvard, Vancouver, ISO itp.

30

Xiaoyan, Chen, and Yu Xian. "Research of Low Power Humidity Sensor Based on Complementary Metal Oxide Semiconductor Technology in Power Monitoring." Journal of Nanoelectronics and Optoelectronics 18, no. 6 (2023): 687–91. http://dx.doi.org/10.1166/jno.2023.3441.

Pełny tekst źródła

Streszczenie:

With the decrease of the size of semiconductor, the humidity sensor can be miniaturized and integrated by CMOS technology, and the humidity sensor chip can be made in large scale and low cost. In this paper, the technology structure of integrated capacitive humidity sensor chip is designed and fabricated by using UMC40nm semiconductor technology, it provides a reference for realizing the highly integrated technology of humidity sensor. This paper also analyzes the common micro-capacitance detection methods of humidity sensor, and combines the advantages of capacitor charge-discharge and pulse-

Style APA, Harvard, Vancouver, ISO itp.

31

Liu, Haotian, Li Zhang, King Li, and Ooi Tan. "Microhotplates for Metal Oxide Semiconductor Gas Sensor Applications—Towards the CMOS-MEMS Monolithic Approach." Micromachines 9, no. 11 (2018): 557. http://dx.doi.org/10.3390/mi9110557.

Pełny tekst źródła

Streszczenie:

The recent development of the Internet of Things (IoT) in healthcare and indoor air quality monitoring expands the market for miniaturized gas sensors. Metal oxide gas sensors based on microhotplates fabricated with micro-electro-mechanical system (MEMS) technology dominate the market due to their balance in performance and cost. Integrating sensors with signal conditioning circuits on a single chip can significantly reduce the noise and package size. However, the fabrication process of MEMS sensors must be compatible with the complementary metal oxide semiconductor (CMOS) circuits, which impo

Style APA, Harvard, Vancouver, ISO itp.

32

Sun, Shou Lei, Gui Tang Wang, Ying Ge Li, and Zheng Li. "Research on Testing Technology of CMOS Camera Module." Applied Mechanics and Materials 378 (August 2013): 408–12. http://dx.doi.org/10.4028/www.scientific.net/amm.378.408.

Pełny tekst źródła

Streszczenie:

After the completion of the CMOS(Complementary Metal-Oxide-Semiconductor Transistor) camera module assembly,in order to test the image quality of module. In this paper, based on the ISO12233 standard chart proposing a CMOS camera module modulation transfer function MTF (modulation transfer function) of test method, MTF average value calculated for each module with high contrast and grayscale method, and validation processing to detect unqualified imaging module. The results show that MTF detection method used in this paper can quickly and accurately detect the quality camera module, and stable

Style APA, Harvard, Vancouver, ISO itp.

33

Yu, Le, Yaozu Guo, Haoyu Zhu, Mingcheng Luo, Ping Han, and Xiaoli Ji. "Low-Cost Microbolometer Type Infrared Detectors." Micromachines 11, no. 9 (2020): 800. http://dx.doi.org/10.3390/mi11090800.

Pełny tekst źródła

Streszczenie:

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the C

Style APA, Harvard, Vancouver, ISO itp.

34

Gao, Yan, Xiu Liu, Jin Jiang He, Hao Zeng, Xiao Dong Xiong, and Yue Wang. "Replacement of High-Purity Copper Target by High-Purity Copper Alloy Target in Very Large Scale Integrated Circuit." Materials Science Forum 848 (March 2016): 430–34. http://dx.doi.org/10.4028/www.scientific.net/msf.848.430.

Pełny tekst źródła

Streszczenie:

With the development of semiconductor technology, the size of complementary metal oxide semiconductor (CMOS) devices has been scaled down to nanoscale dimensions. The technology of copper interconnection is the mainstream technology, so the request of the copper target is more and more rigor. This article analyzes the impact factors on the copper alloy target capability, including oxidation and strength. The aim of this investigation is to set up a bridge between the vendors of copper targets and the foundries of integrated circuit (IC) chip, and the base for the next generation copper targets

Style APA, Harvard, Vancouver, ISO itp.

35

Nomura, Kenji. "(Invited) Recent Advances in Oxide-TFT Technology for Next-Generation Sustainable Electronics." ECS Meeting Abstracts MA2024-02, no. 20 (2024): 1795. https://doi.org/10.1149/ma2024-02201795mtgabs.

Pełny tekst źródła

Streszczenie:

Metal-oxide semiconductors and the relevant electronic devices, particularly thin-film transistor technology are nowadays acknowledged as promising elements for the development of next-generation ubiquitous sustainable electronics. Due to their superior characteristics, such as high electron mobility even in disordered structures, wide-bandgap nature, and low-temperature processability, these technologies offer high-performance, low-power device operation, and cost-effective fabrication processes. A n-channel oxide-TFT using amorphous In-Ga-Zn-O (a-IGZO) channel has already been successfully c

Style APA, Harvard, Vancouver, ISO itp.

36

Sunkara, Sowmya. "Performance Analysis of 8x4 Barrel Shifters in CMOS and FINFET Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 10 (2024): 65–75. http://dx.doi.org/10.22214/ijraset.2024.64448.

Pełny tekst źródła

Streszczenie:

Shifters are essential components in digital circuits, enabling data manipulation and routing for a wide range of computational tasks. This study presents a comprehensive performance analysis of 8x4 barrel shifters implemented in two distinct semiconductor technologies: Complementary Metal-Oxide-Semiconductor (CMOS) and FinFET. This study compares and evaluates the important parameters for these shifters at both technological nodes, such as power consumption. Additionally, we examine the effects of scaling on CMOS barrel shifters. Conversely, FinFET technology, recognized for overcoming certai

Style APA, Harvard, Vancouver, ISO itp.

37

Xu, Hanyuan. "A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect." Journal of Physics: Conference Series 2383, no. 1 (2022): 012055. http://dx.doi.org/10.1088/1742-6596/2383/1/012055.

Pełny tekst źródła

Streszczenie:

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce th

Style APA, Harvard, Vancouver, ISO itp.

38

Miyake, Masayasu, Toshio Kobayashi, Yutaka Sakakibara, Kimiyoshi Deguchi, and Mitsutoshi Takahashi. "Deep-Submicron Single-Gate Complementary Metal Oxide Semiconductor (CMOS) Technology Using Channel Preamorphization." Japanese Journal of Applied Physics 37, Part 1, No. 3B (1998): 1050–53. http://dx.doi.org/10.1143/jjap.37.1050.

Pełny tekst źródła

Style APA, Harvard, Vancouver, ISO itp.

39

Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini, and Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors." Electronics 10, no. 17 (2021): 2114. http://dx.doi.org/10.3390/electronics10172114.

Pełny tekst źródła

Streszczenie:

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38

Style APA, Harvard, Vancouver, ISO itp.

40

Roberto, Marani, and Gina Perri Anna. "A procedure to analyze digital circuits in CNTFET and CMOS technology by ADS." i-manager’s Journal on Electronics Engineering 13, no. 4 (2023): 1. http://dx.doi.org/10.26634/jele.13.4.20048.

Pełny tekst źródła

Streszczenie:

This paper proposes a procedure to analyze digital circuits in both Carbon Nanotube Field-Effect Transistors (CNTFET) and Complementary Metal-Oxide-Semiconductor (CMOS) technology for the purpose of comparison. The procedure is applied to study a NAND gate, with an emphasis on its applicability to analyze other digital circuits. To demonstrate this versatility, the procedure is also used to analyze a NOT gate in both CNTFET and CMOS technology. The paper presents the improvements achieved with CNTFET technology compared to CMOS. All simulations are conducted using the Advanced Design System (A

Style APA, Harvard, Vancouver, ISO itp.

41

Kawanago, Takamasa, Takahiro Matsuzaki, Ryosuke Kajikawa, et al. "Experimental demonstration of high-gain CMOS inverter operation at low V _dd down to 0.5 V consisting of WSe₂ n/p FETs." Japanese Journal of Applied Physics 61, SC (2022): SC1004. http://dx.doi.org/10.35848/1347-4065/ac3a8e.

Pełny tekst źródła

Streszczenie:

Abstract In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (V dd ), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer/aluminum oxide (AlO x ) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping techni

Style APA, Harvard, Vancouver, ISO itp.

42

Radamson, Henry H., Huilong Zhu, Zhenhua Wu, et al. "State of the Art and Future Perspectives in Advanced CMOS Technology." Nanomaterials 10, no. 8 (2020): 1555. http://dx.doi.org/10.3390/nano10081555.

Pełny tekst źródła

Streszczenie:

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to th

Style APA, Harvard, Vancouver, ISO itp.

43

Chen, Mengguo, Chunhui Jing, and Haoran Mou. "Third generation semiconductor device research: Optimizing CMOS and HEMT designs." Applied and Computational Engineering 39, no. 1 (2024): 201–8. http://dx.doi.org/10.54254/2755-2721/39/20230601.

Pełny tekst źródła

Streszczenie:

The third-generation semiconductor device known as High Electron Mobility Transistors (HEMT) has found extensive applications in high-frequency and high-speed electronic systems. Its widespread usage in critical technologies such as radio telescopes, satellite broadcast receivers, and cellular base stations has established HEMT as a foundational technology underpinning our information and communication society. This paper provides an in-depth exploration of these semiconductor advancements. Firstly, the paper utilizes the CMOS inverter as a representative example to elucidate the fundamental s

Style APA, Harvard, Vancouver, ISO itp.

44

Sardar1, Rupam, Sudip Ghosh2, and Bimal Datta3. "Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 03 (2024): 1–11. http://dx.doi.org/10.55041/ijsrem29060.

Pełny tekst źródła

Streszczenie:

The goal of this research is to create Full-Adder gate using a Complementary Metal Oxide Semiconductor (CMOS) and an Artificial Neural Network.We constantly bear in mind that any COMS circuit we design should be as inexpensive as possible.Multilayer ANN was employed in this work to create the circuit. Weights are employed to modify the value in our study, treating neurons as transistors and treating negative values as inverters.We are also designing Verilog-HdL Code to simply apply the full adder for experimenting an artificial neural network assigning weights to get appropriate results. Keywo

Style APA, Harvard, Vancouver, ISO itp.

45

Wong, Hei, Jieqiong Zhang, and Jun Liu. "Contacts at the Nanoscale and for Nanomaterials." Nanomaterials 14, no. 4 (2024): 386. http://dx.doi.org/10.3390/nano14040386.

Pełny tekst źródła

Streszczenie:

Contact scaling is a major challenge in nano complementary metal–oxide–semiconductor (CMOS) technology, as the surface roughness, contact size, film thicknesses, and undoped substrate become more problematic as the technology shrinks to the nanometer range. These factors increase the contact resistance and the nonlinearity of the current–voltage characteristics, which could limit the benefits of the further downsizing of CMOS devices. This review discusses issues related to the contact size reduction of nano CMOS technology and the validity of the Schottky junction model at the nanoscale. The

Style APA, Harvard, Vancouver, ISO itp.

46

Filipovic, Lado, and Siegfried Selberherr. "Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors." Nanomaterials 12, no. 20 (2022): 3651. http://dx.doi.org/10.3390/nano12203651.

Pełny tekst źródła

Streszczenie:

During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication techniqu

Style APA, Harvard, Vancouver, ISO itp.

47

Yang, Tongtong, Yan Wang, and Ruifeng Yue. "Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique." Journal of Semiconductors 43, no. 8 (2022): 082801. http://dx.doi.org/10.1088/1674-4926/43/8/082801.

Pełny tekst źródła

Streszczenie:

Abstract In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measureme

Style APA, Harvard, Vancouver, ISO itp.

48

Liang, Wenbin, Zhenzhen Luo, Xian Yu, and Xiaoyan Chen. "Design of Low Power Temperature Sensor Based on 180 nm Complementary Metal Oxide Semiconductor Technology." Journal of Nanoelectronics and Optoelectronics 18, no. 5 (2023): 551–57. http://dx.doi.org/10.1166/jno.2023.3422.

Pełny tekst źródła

Streszczenie:

CMOS temperature sensor is widely used in power monitoring system, power consumption is an important index. The digital filter power consumption is one of the main sources of the temperature sensor power consumption, and limiting the Digital filter power consumption becomes an important method to realize the low power consumption of the temperature sensor. Based on this, a low power digital filter for CMOS temperature sensors is designed, and a precision adaptive digital filter is proposed, the filter is cascaded by a recursive CIC filter and a FIR filter based on a shift adder, the order of C

Style APA, Harvard, Vancouver, ISO itp.

49

Joubert, James, and Deepak Sharma. "Using CMOS Cameras for Light Microscopy." Microscopy Today 19, no. 4 (2011): 22–28. http://dx.doi.org/10.1017/s155192951100054x.

Pełny tekst źródła

Streszczenie:

The push in consumer electronics over past decades has been toward smaller, faster, and cheaper products but with same or improved capabilities. The consumer imaging world has been no exception with the integration, for example, of functional complementary metal-oxide-semiconductor (CMOS) cameras into ever smaller cellular phones. The CMOS sensors have continued to develop and improve with increasing numbers of smaller, more sensitive pixels with larger photo-response capacity providing higher dynamic range. This technological expansion has inevitably spilled over into even the scientific imag

Style APA, Harvard, Vancouver, ISO itp.

50

Choi, Kyu-Jin, Jae-Hyun Park, Seong-Kyun Kim, and Byung-Sung Kim. "K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology." Electronics 10, no. 8 (2021): 890. http://dx.doi.org/10.3390/electronics10080890.

Pełny tekst źródła

Streszczenie:

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the propose

Style APA, Harvard, Vancouver, ISO itp.

Oferujemy zniżki na wszystkie plany premium dla autorów, których prace zostały uwzględnione w tematycznych zestawieniach literatury. Skontaktuj się z nami, aby uzyskać unikalny kod promocyjny!