Gotowe bibliografie tematyczne / CONVENTIONAL CLOCK GATING

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Gotowa bibliografia na temat „CONVENTIONAL CLOCK GATING”

Autor: Grafiati

Data publikacji: 11 września 2023

Data aktualizacji: 31 lipca 2025

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Artykuły w czasopismach na temat "CONVENTIONAL CLOCK GATING"

Titus, Joby. "LEAKAGE AND SWITCHING POWER OPTIMIZATION IN CMOS PROCESSORS USING LOW-POWER RECONFIGURABLE MATCH TABLE-BASED CLOCK GATING CONTROLLERS." ICTACT Journal on Microelectronics 11, no. 1 (2025): 2011–18. https://doi.org/10.21917/ijme.2025.0342.

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Modern CMOS processors face a significant challenge in power consumption, primarily due to switching and leakage power. With rising demands for energy-efficient systems, especially in mobile and IoT devices, managing dynamic and static power has become essential. Conventional clock gating techniques lack adaptability to workload variability, leading to inefficient power savings. Fixed gating schemes either over-constrain performance or underperform in power savings. This work proposes a Low-Power Reconfigurable Match Table (RMT)- based Clock Controller that dynamically adjusts clock gating gra

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Jyothula, Sudhakar. "Low power aware pulse triggered flip flops using modified clock gating approaches." World Journal of Engineering 15, no. 6 (2018): 792–803. http://dx.doi.org/10.1108/wje-09-2017-0309.

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PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-powe

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Jung, Jun Mo, and Jong-Wha Chong. "A Low Power FIR Filter Design for Image Processing." VLSI Design 12, no. 3 (2001): 391–97. http://dx.doi.org/10.1155/2001/54974.

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In this paper, a new low power design method of the FIR filter for image processing is proposed. Because the correlation between adjacent pixels is very high in image data, the clock gating technique can be a good candidate for low power strategy. However, the conventional clock gating strategy that is applied independently to every flip-flop of the filter give rise to too much additional area overhead and couldn't get a good result in the power reduction. In our method, each tap register, which is used to delay the input data in the filter, is partitioned into two sub-registers according to t

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Varsha, K. Pavithra, and Dr V. Sumalatha. "Design of Power Optimised Truncated Approximate Booth Multiplier." International Journal for Research in Applied Science and Engineering Technology 12, no. 11 (2024): 948–55. http://dx.doi.org/10.22214/ijraset.2024.65245.

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Abstract: In digital signal processing and arithmetic circuits, Booth multipliers are widely used for efficient multiplication of signed numbers. However, conventional Booth multipliers consume significant power due to their full precision operation. This paper explores efficient approximation techniques for Booth multipliers enhanced with flip-flop clock gating to reduce power consumption. Booth multipliers traditionally consume significant power due to their full precision operations. In this approach it mainly focuses on truncating less significant bits in the Booth encoding to lower comput

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Sam, D. S. Shylu, P. Sam Paul, Joel Samuel, and Vimukth John. "A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 22 (December 31, 2023): 195–205. http://dx.doi.org/10.37394/23201.2023.22.22.

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Counters play an inevitable role in many VLSI circuits such as timers, frequency dividers, memories, and ADC/DAC. Integrating the timing discriminator, Pulse Swallow, and Correlated double sampling are various approaches used in counters for low power consumption. The main objective was to minimize the power consumption and device count. In this work, a new embedded clock gating technique is used in an 8-bit counter to reduce the switching activity. A clock gating circuit and clock buffer network pattern are used in the proposed algorithm to reduce the power consumption of synchronous counters

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Jeong, Seoyeong, Junhyuk Jang, Kichang Lee, and Jaemyung Lim. "P‐249: Late‐News Poster: A Low Power Digital Logic Structure for High Resolution and High Frame Rate OLEDoS Micro Displays." SID Symposium Digest of Technical Papers 55, no. 1 (2024): 1705–8. http://dx.doi.org/10.1002/sdtp.17898.

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This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6 % compared to the conventional data signal tree structure, enabling a low‐power design.

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Ramalinga Reddy Kotapati. "Advanced Clock Tree Synthesis Optimization: A Multi-Source Approach to Minimizing Skew and Power in Sub-7nm ASIC Designs." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 6 (2024): 2275–83. https://doi.org/10.32628/cseit2410612440.

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Clock tree synthesis (CTS) optimization remains a critical challenge in advanced node ASIC physical design, particularly as semiconductor technologies continue to scale down. This article presents a comprehensive methodology for optimizing multi-source clock distribution networks while addressing power consumption and timing accuracy concerns. The article introduces an integrated approach that combines functional clock gating strategies with sophisticated skew management techniques to achieve optimal performance in high-frequency designs. The proposed framework incorporates latch-based timing

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Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.

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<p>The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant b

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Laskar, Nivedita, Suman Debnath, Alak Majumder, and Bidyut Kumar Bhattacharyya. "A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%." Journal of Circuits, Systems and Computers 27, no. 03 (2017): 1850049. http://dx.doi.org/10.1142/s0218126618500494.

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The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to [Formula: see text]d[Formula: see text]/d[Formula: see text]. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor

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Touil, Lamjed, Abdelaziz Hamdi, Ismail Gassoumi, and Abdellatif Mtibaa. "Design of Low-Power Structural FIR Filter Using Data-Driven Clock Gating and Multibit Flip-Flops." Journal of Electrical and Computer Engineering 2020 (July 10, 2020): 1–9. http://dx.doi.org/10.1155/2020/8108591.

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Optimization for power is one of the most important design objectives in modern digital signal processing (DSP) applications. The digital finite duration impulse response (FIR) filter is considered to be one of the most essential components of DSP, and consequently a number of extensive works had been carried out by researchers on the power optimization of the filters. Data-driven clock gating (DDCG) and multibit flip-flops (MBFFs) are two low-power design methods that are used and often treated separately. The combination of these methods into a single algorithm enables further power saving o

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Rozprawy doktorskie na temat "CONVENTIONAL CLOCK GATING"

MULANI, JUNED ALTAF. "POWER, PERFORMANCE AND AREA METRICS IN VLSI DESIGN: AN ANALYTICAL APPROACH." Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19849.

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Power consumption, performance, and area utilization are critical considerations in VLSI design. This paper presents an analytical approach to optimize these metrics using a proposed clock gating technique. The objective is to achieve power-efficient and high-performance VLSI designs while minimizing the area overhead. The proposed clock gating technique utilizes a sophisticated control logic that selectively enables clock signals to the circuit components based on their activity. By dynamically controlling the clock distribution, unnecessary switching and power dissipation are red

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