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Artykuły w czasopismach na temat „Formal verification”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 25 lipca 2025

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1

Meenakshi, B. "Formal verification." Resonance 10, no. 5 (2005): 26–38. http://dx.doi.org/10.1007/bf02871329.

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Kaushik Velapa Reddy. "Formal Verification with ABV : A Superior Alternative to UVM for Complex Computing Chips." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 6 (2024): 90–98. http://dx.doi.org/10.32628/cseit24106157.

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This article explores the evolution and effectiveness of formal verification enhanced with Assertion-Based Verification (ABV) as a superior alternative to traditional Universal Verification Methodology (UVM) in complex computing chip design. Through analysis of implementation data from major semiconductor companies, including Intel's Core i7 and IBM's POWER processors, the article demonstrates how formal methods achieve up to 100% coverage of critical modules compared to UVM's typical 80-85% coverage. The research presents quantitative evidence of formal verification's advantages, including a

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3

Bjesse, Per. "What is formal verification?" ACM SIGDA Newsletter 35, no. 24 (2005): 1. http://dx.doi.org/10.1145/1113792.1113794.

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Schlipf, T., T. Buechner, R. Fritz, M. Helms, and J. Koehl. "Formal verification made easy." IBM Journal of Research and Development 41, no. 4.5 (1997): 567–76. http://dx.doi.org/10.1147/rd.414.0567.

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5

Sauvage, Laurent, Tarik Graba, and Thibault Porteboeuf. "Multi-level formal verification." Journal of Cryptographic Engineering 7, no. 1 (2016): 87–95. http://dx.doi.org/10.1007/s13389-016-0144-3.

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6

Niculaescu, Oana. "What's formal software verification?" XRDS: Crossroads, The ACM Magazine for Students 25, no. 4 (2019): 64–65. http://dx.doi.org/10.1145/3341815.

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7

Flores, Sonia, Salvador Lucas, and Alicia Villanueva. "Formal Verification of Websites." Electronic Notes in Theoretical Computer Science 200, no. 3 (2008): 103–18. http://dx.doi.org/10.1016/j.entcs.2008.04.095.

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8

Staroletov, Sergey Mikhailovich, Dmitry Alexandrovich Kondratyev, Natalia Olegovna Garanina, and Irina Vladimirovna Shoshmina. "VeHa-2023 Formal Verification Contest: The Experience." Proceedings of the Institute for System Programming of the RAS 36, no. 2 (2024): 141–68. http://dx.doi.org/10.15514/ispras-2024-36(2)-11.

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To create modern competitive and trusted software, it is necessary to use knowledge of formal methods. Currently, a huge number of students are studying specialties related to programming. However, when studying at a university, it is difficult to gain the skill of practical application of theoretical knowledge. Short competitions with non-standard, industrial-related problems can arouse students' interest in the field of formal methods. The article describes the first experience of organizing a competition in formal verification of programs among students of Russian universities. The competit

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9

Harrison, John. "Floating-Point Verification." JUCS - Journal of Universal Computer Science 13, no. (5) (2007): 629–38. https://doi.org/10.3217/jucs-013-05-0629.

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This paper overviews the application of formal verification techniques to hardware ingeneral, and to floating-point hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible andverifiable way.

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10

Greengard, Samuel. "Formal software verification measures up." Communications of the ACM 64, no. 7 (2021): 13–15. http://dx.doi.org/10.1145/3464933.

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11

Michael, James Bret, Doron Drusinsky, and Duminda Wijesekera. "Formal Verification of Cyberphysical Systems." Computer 54, no. 9 (2021): 15–24. http://dx.doi.org/10.1109/mc.2021.3055883.

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12

Qian, Junyan, and Baowen Xu. "Formal Verification for C Program." Informatica 18, no. 2 (2007): 289–304. http://dx.doi.org/10.15388/informatica.2007.178.

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13

Tristan, Jean-Baptiste, and Xavier Leroy. "Formal verification of translation validators." ACM SIGPLAN Notices 43, no. 1 (2008): 17–27. http://dx.doi.org/10.1145/1328897.1328444.

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14

Moghissi, Gholam Reza, and Ali Payandeh. "Formal Verification of NTRUEncrypt Scheme." International Journal of Computer Network and Information Security 8, no. 4 (2016): 44–55. http://dx.doi.org/10.5815/ijcnis.2016.04.06.

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15

Geraldes, André A., Luca Geretti, Davide Bresolin, et al. "Formal Verification of Medical CPS." ACM Transactions on Cyber-Physical Systems 2, no. 4 (2018): 1–29. http://dx.doi.org/10.1145/3140237.

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16

Alur, Rajeev. "Next steps in formal verification." ACM Computing Surveys 28, no. 4es (1996): 115. http://dx.doi.org/10.1145/242224.242373.

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17

Henzinger, Thomas A. "Some myths about formal verification." ACM Computing Surveys 28, no. 4es (1996): 119. http://dx.doi.org/10.1145/242224.242378.

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18

BCS. "Hot topic: Formal program verification." Computer Bulletin 46, no. 6 (2004): 32. http://dx.doi.org/10.1093/combul/46.6.32-a.

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19

Cortier, Véronique. "Formal verification of e-voting." ACM SIGLOG News 2, no. 1 (2015): 25–34. http://dx.doi.org/10.1145/2728816.2728823.

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20

Guaspari, D., C. Marceau, and W. Polak. "Formal verification of Ada programs." IEEE Transactions on Software Engineering 16, no. 9 (1990): 1058–75. http://dx.doi.org/10.1109/32.58790.

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21

Kern, Christoph, and Mark R. Greenstreet. "Formal verification in hardware design." ACM Transactions on Design Automation of Electronic Systems 4, no. 2 (1999): 123–93. http://dx.doi.org/10.1145/307988.307989.

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22

Park, Taeshin, and Paul I. Barton. "Formal verification of sequence controllers." Computers & Chemical Engineering 23, no. 11-12 (2000): 1783–93. http://dx.doi.org/10.1016/s0098-1354(99)00327-0.

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23

Filkorn, Th, M. Hölzlein, P. Warkentin, and M. Weiβ. "Formal verification of PLC-programs." IFAC Proceedings Volumes 32, no. 2 (1999): 1513–18. http://dx.doi.org/10.1016/s1474-6670(17)56256-4.

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24

Guang-hui, Li, and Li Xiao-wei. "Formal verification under unknown constraints." Wuhan University Journal of Natural Sciences 10, no. 1 (2005): 43–46. http://dx.doi.org/10.1007/bf02828614.

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25

Chockler, Hana, Orna Kupferman, and Moshe Vardi. "Coverage metrics for formal verification." International Journal on Software Tools for Technology Transfer 8, no. 4-5 (2006): 373–86. http://dx.doi.org/10.1007/s10009-004-0175-4.

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26

Huffman, Brian. "Formal verification of monad transformers." ACM SIGPLAN Notices 47, no. 9 (2012): 15–16. http://dx.doi.org/10.1145/2398856.2364532.

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27

Taft, Tucker. "SPARK Formal Verification for Security." ACM SIGAda Ada Letters 39, no. 1 (2020): 83–99. http://dx.doi.org/10.1145/3379106.3379117.

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28

Young, F. C. D., and J. A. Houston. "Formal verification and legacy redesign." IEEE Aerospace and Electronic Systems Magazine 14, no. 3 (1999): 31–36. http://dx.doi.org/10.1109/62.750426.

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29

Abadir, Magdy S., Kenneth L. Albin, John Havlicek, Narayanan Krishnamurthy, and Andrew K. Martin. "Formal Verification Successes at Motorola." Formal Methods in System Design 22, no. 2 (2003): 117–23. http://dx.doi.org/10.1023/a:1022917321255.

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30

Dai, Guiping. "Formal Verification for KMB09 Protocol." International Journal of Theoretical Physics 58, no. 11 (2019): 3651–57. http://dx.doi.org/10.1007/s10773-019-04232-2.

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31

Mittelmann, Munyque, Bastien Maubert, Aniello Murano, and Laurent Perrussel. "Formal Verification of Bayesian Mechanisms." Proceedings of the AAAI Conference on Artificial Intelligence 37, no. 10 (2023): 11621–29. http://dx.doi.org/10.1609/aaai.v37i10.26373.

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In this paper, for the first time, we study the formal verification of Bayesian mechanisms through strategic reasoning. We rely on the framework of Probabilistic Strategy Logic (PSL), which is well-suited for representing and verifying multi-agent systems with incomplete information. We take advantage of the recent results on the decidability of PSL model checking under memoryless strategies, and reduce the problem of formally verifying Bayesian mechanisms to PSL model checking. We show how to encode Bayesian-Nash equilibrium and economical properties, and illustrate our approach with differen

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32

Xie, Guojun, Huanhuan Yang, Hao Deng, Zhengpu Shi, and Gang Chen. "Formal Verification of Robot Rotary Kinematics." Electronics 12, no. 2 (2023): 369. http://dx.doi.org/10.3390/electronics12020369.

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With the widespread application of robots in aerospace, medicine, automation, and other fields, their motion safety is essential for the well-being of humans and the accomplishment of vital socially beneficial programs. Conventional robot hardware and software designs mainly rely on experiential knowledge and manual testing to ensure safety, but this fails to cover all possible testing paths and adds risks. Alternatively, formal, mathematically rigorous verifications can provide predictable and reliable guarantees of robot motion safety. To demonstrate the feasibility of this approach, we form

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33

ASPERTI, ANDREA, HERMAN GEUVERS, and RAJA NATARAJAN. "Social processes, program verification and all that." Mathematical Structures in Computer Science 19, no. 5 (2009): 877–96. http://dx.doi.org/10.1017/s0960129509990041.

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In a controversial paper (De Millo et al. 1979) at the end of the 1970's, R. A. De Millo, R. J. Lipton and A. J. Perlis argued against formal verifications of programs, mostly motivating their position by an analogy with proofs in mathematics, and, in particular, with the impracticality of a strictly formalist approach to this discipline. The recent, impressive achievements in the field of interactive theorem proving provide an interesting ground for a critical revisiting of their theses. We believe that the social nature of proof and program development is uncontroversial and ineluctable, but

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34

Nallamalli, Ranjana, and Durg Singh Chauhan. "Rapid Formal Verification as Requirements Stage Verification and Validation Technique." International Review on Computers and Software (IRECOS) 14, no. 1 (2019): 27. http://dx.doi.org/10.15866/irecos.v14i1.17684.

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35

Woodcock, Jim, and Richard Banach. "The Verification Grand Challenge." JUCS - Journal of Universal Computer Science 13, no. (5) (2007): 661–68. https://doi.org/10.3217/jucs-013-05-0661.

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This paper overviews the Verification Grand Challenge, a large scale multinationalintiative designed to significantly increase the interoperability, applicability and uptake of formal development techniques. Results to date are reviewed, and next steps are outlined.

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36

Brewka, Lukasz, José Soler, and Michael Berger. "The MODUS Approach to Formal Verification." Business Systems Research Journal 5, no. 1 (2014): 21–33. http://dx.doi.org/10.2478/bsrj-2014-0002.

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Abstract Background: Software reliability is of great importance for the development of embedded systems that are often used in applications that have requirements for safety. Since the life cycle of embedded products is becoming shorter, productivity and quality simultaneously required and closely in the process of providing competitive products Objectives: In relation to this, MODUS (Method and supporting toolset advancing embedded systems quality) project aims to provide small and medium-sized businesses ways to improve their position in the embedded market through a pragmatic and viable so

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37

Koch, Alexander, Michael Schrempp, and Michael Kirsten. "Card-Based Cryptography Meets Formal Verification." New Generation Computing 39, no. 1 (2021): 115–58. http://dx.doi.org/10.1007/s00354-020-00120-0.

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AbstractCard-based cryptography provides simple and practicable protocols for performing secure multi-party computation with just a deck of cards. For the sake of simplicity, this is often done using cards with only two symbols, e.g., $$\clubsuit $$ ♣ and $$\heartsuit $$ ♡ . Within this paper, we also target the setting where all cards carry distinct symbols, catering for use-cases with commonly available standard decks and a weaker indistinguishability assumption. As of yet, the literature provides for only three protocols and no proofs for non-trivial lower bounds on the number of cards. As

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38

Benabbou, Amel, Safia Nait Bahloul, and Dhaussy Philippe. "Context-aware approach for formal verification." EAI Endorsed Transactions on Context-aware Systems and Applications 3, no. 7 (2016): 151085. http://dx.doi.org/10.4108/eai.12-2-2016.151085.

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39

Herklotz, Yann, James D. Pollard, Nadesh Ramanathan, and John Wickerson. "Formal verification of high-level synthesis." Proceedings of the ACM on Programming Languages 5, OOPSLA (2021): 1–30. http://dx.doi.org/10.1145/3485494.

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High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any

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40

Huuck, Ralf. "Formal Verification, Engineering and Business Value." Electronic Proceedings in Theoretical Computer Science 105 (December 29, 2012): 1–4. http://dx.doi.org/10.4204/eptcs.105.1.

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Lee, Tae-Hoon, and Gi-Hwon Kwon. "Formal Verification of Embedded Java Program." KIPS Transactions:PartD 12D, no. 7 (2005): 931–36. http://dx.doi.org/10.3745/kipstd.2005.12d.7.931.

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42

Razali, Rozilawati, and Paul Garratt. "Usability Requirement of Formal Verification Tools." Asia-Pacific Journal of Information Technology and Multimedia 01, no. 02 (2012): 37–52. http://dx.doi.org/10.17576/apjitm-2012-0102-04.

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43

Kishi, Tomoji, and Natsuko Noda. "Formal verification and software product lines." Communications of the ACM 49, no. 12 (2006): 73–77. http://dx.doi.org/10.1145/1183236.1183270.

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Kumar, Jayanand Asok, and Shobha Vasudevan. "Formal Probabilistic Timing Verification in RTL." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 5 (2013): 788–801. http://dx.doi.org/10.1109/tcad.2012.2232706.

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Pixley, C. "Formal verification of commercial integrated circuits." IEEE Design and Test of Computers 18, no. 4 (2001): 4–5. http://dx.doi.org/10.1109/mdt.2001.936243.

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46

Srivas, M., and M. Bickford. "Formal verification of a pipelined microprocessor." IEEE Software 7, no. 5 (1990): 52–64. http://dx.doi.org/10.1109/52.57892.

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Jones, R. B., J. W. O'Leary, C. J. H. Seger, M. D. Aagaard, and T. F. Melham. "Practical formal verification in microprocessor design." IEEE Design & Test of Computers 18, no. 4 (2001): 16–25. http://dx.doi.org/10.1109/54.936245.

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Choppy, Christine, Kais Klai, and Hacene Zidani. "Formal verification of UML state diagrams." ACM SIGSOFT Software Engineering Notes 36, no. 1 (2011): 1–8. http://dx.doi.org/10.1145/1921532.1921561.

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Chen, Xi, Harry Hsieh, Felice Balarin, and Yosinori Watanabe. "Formal Verification for Embedded System Designs." Design Automation for Embedded Systems 8, no. 2/3 (2003): 139–53. http://dx.doi.org/10.1023/b:daem.0000003959.60964.4d.

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Lukyanov, Georgy, Andrey Mokhov, and Jakob Lechner. "Formal Verification of Spacecraft Control Programs." ACM Transactions on Embedded Computing Systems 19, no. 5 (2020): 1–18. http://dx.doi.org/10.1145/3391900.

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