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Artykuły w czasopismach na temat „Stencil printing”

Autor: Grafiati

Data publikacji: 4 czerwca 2021

Data aktualizacji: 6 lutego 2022

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1

Lee, Yong‐Won, Keun‐Soo Kim, and Katsuaki Suganuma. "The behaviour of solder pastes in stencil printing with electropolishing process." Soldering & Surface Mount Technology 25, no. 3 (June 21, 2013): 164–74. http://dx.doi.org/10.1108/ssmt-12-2012-0027.

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PurposeThe purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.Design/methodology/approachDuring the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared

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Vallabhajosyula, Phani. "Stencil Print solutions for Advance Packaging Applications." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000646–51. http://dx.doi.org/10.4071/isom-2017-poster1_124.

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Abstract This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging. As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high-performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are re

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Wickström, Henrika, Rajesh Koppolu, Ermei Mäkilä, Martti Toivakka, and Niklas Sandler. "Stencil Printing—A Novel Manufacturing Platform for Orodispersible Discs." Pharmaceutics 12, no. 1 (January 1, 2020): 33. http://dx.doi.org/10.3390/pharmaceutics12010033.

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Stencil printing is a commonly used printing method, but it has not previously been used for production of pharmaceuticals. The aim of this study was to explore whether stencil printing of drug containing polymer inks could be used to manufacture flexible dosage forms with acceptable mass and content uniformity. Formulation development was supported by physicochemical characterization of the inks and final dosage forms. The printing of haloperidol (HAL) discs was performed using a prototype stencil printer. Ink development comprised of investigations of ink rheology in combination with printab

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4

YAMADA, Hiromichi. "Stencil Printing Ink." Journal of the Japan Society of Colour Material 70, no. 11 (1997): 751–56. http://dx.doi.org/10.4011/shikizai1937.70.751.

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5

Yu, JiangYou, Le Cao, Hao Fu, and Jun Guo. "A method for optimizing stencil cleaning time in solder paste printing process." Soldering & Surface Mount Technology 31, no. 4 (September 2, 2019): 233–39. http://dx.doi.org/10.1108/ssmt-10-2018-0037.

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PurposeStencil cleaning is an important operation in solder paste printing process. Frequent cleaning may interrupt printing process and increase idle time, as well as loss for performing cleaning. This paper aims to propose a method to optimize the stencil cleaning time and reduce unnecessary cleaning operations and losses.Design/methodology/approachThis paper uses a discrete-time, discrete-state homogeneous Markov chain to model the stencil printing performance degradation process, and the quality loss during the stencil printing process is estimated based on this degradation model. A stenci

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6

Pei-Lim, Sze, Kenneth Thum, and Andy Mackie. "Challenges in Fine Feature Solder Paste Printing for SiP Applications." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000245–49. http://dx.doi.org/10.4071/isom-2016-wp12.

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Abstract The rapid development in the Internet of Things (IoT) has seen a surge in demand for System-in-Package (SiP), which is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller components and greater density. 01005 passive components are being used in most of the current SiP technology and the industry is looking at utilizing 008004 passive components for the next generation SiP. The stencil aperture design for 008004 will likely be about half of 0100

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7

Sriperumbudur, Sai Srinivas, Michael Meilunas, and Martin Anselm. "Solder paste volume effects on assembly yield and reliability for bottom terminated components." Soldering & Surface Mount Technology 29, no. 2 (April 3, 2017): 99–109. http://dx.doi.org/10.1108/ssmt-05-2016-0010.

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Purpose Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower lim

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W. Kay, Robert, Gerard Cummins, Thomas Krebs, Richard Lathrop, Eitan Abraham, and Marc Desmulliez. "Statistical analysis of stencil technology for wafer-level bumping." Soldering & Surface Mount Technology 26, no. 2 (April 1, 2014): 71–78. http://dx.doi.org/10.1108/ssmt-07-2013-0017.

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Purpose – Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues. Design/methodology/approach – In this paper, the authors present a statistical evaluation of the impact of stencil tech

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9

Whitmore, Mark, and Clive Ashmore. "Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000502–8. http://dx.doi.org/10.4071/isom-2011-wa2-paper2.

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As electronics assemblies continue to shrink in form factor, forcing designers towards smaller components with decreasing pitches, the Surface Mount assembly process is becoming increasingly challenged. A new “active” squeegee printing process has been developed to assist in the stencil printing of solder pastes for next generation ultra fine pitch components such as 0.3mm pitch CSP’s. Results indicate that today’s accepted stencil area ratio rules, which govern solder paste transfer efficiency can be significantly pushed to extend stencil printing process capabilities to stencil apertures hav

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10

Vallabhajosyula, Phani. "Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–18. http://dx.doi.org/10.4071/2017dpc-poster_vallabhajosyula.

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Mixed technology applications for Flip-Chip (FC) / SMT require special step stencil designs where flux is printed first for the FC and SMD paste printed next with a second stencil that has a relief pocket etched or formed in the FC area. Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, Step Stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and

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11

Kenny, Stephen, Sven Lamprecht, Kai Matejat, and Bernd Roelfs. "Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 000671–707. http://dx.doi.org/10.4071/2010dpc-ta31.

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Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to

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12

Whitmore, Mark, and Jeff Schake. "The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000667–74. http://dx.doi.org/10.4071/isom-2016-thp55.

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Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looki

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13

Huang, Chien-Yi. "Applying the Taguchi parametric design to optimize the solder paste printing process and the quality loss function to define the specifications." Soldering & Surface Mount Technology 30, no. 4 (September 3, 2018): 217–26. http://dx.doi.org/10.1108/ssmt-03-2017-0010.

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Purpose This research aims to study the stencil printing process of the quad flat package (QFP) component with a pin pitch of 0.4 mm. After the optimization of the printing process, the desired inspection specification is determined to reduce the expected total process loss. Design/methodology/approach Static Taguchi parametric design is applied while considering the noise factors possibly affecting the printing quality in the production environment. The Taguchi quality loss function model is then proposed to evaluate the two types of inspection strategies. Findings The optimal parameter-level

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14

Chunxian Zou, Ling, Milos Dusek, Martin Wickham, and Christopher Hunt. "Fine pitch stencil printing using enclosed printing systems." Soldering & Surface Mount Technology 15, no. 1 (April 2003): 43–49. http://dx.doi.org/10.1108/09540910310455725.

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15

Krammer, Oliver, László Jakab, Balazs Illes, David Bušek, and Ivana Beshajová Pelikánová. "Investigating the attack angle of squeegees with different geometries." Soldering & Surface Mount Technology 30, no. 2 (April 3, 2018): 112–17. http://dx.doi.org/10.1108/ssmt-09-2017-0023.

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Purpose The attack angle of stencil printing squeegees with different geometries was analysed using finite element modelling. Design/methodology/approach A finite element model (FEM) was developed to determine the attack angle during the stencil printing. The material properties of the squeegee were included in the model according to the parameters of steel AISI 4340, and the model was validated by experimental measurements. Two geometric parameters were investigated; two different unloaded angles (45° and 60°) and four overhang sizes of the squeegee (6, 15, 20 and 25 mm). Findings It was foun

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16

Whitmore, Mark, Jeff Schake, and Clive Ashmore. "Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000569–73. http://dx.doi.org/10.4071/isom-2013-wa54.

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With the form factor of electronic assemblies continuing to shrink, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, todays accepted stencil area ratio rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. With aperture geometries shrinking, anything which can influence solder paste transfer efficiency

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17

Asghar, Rafiq, Faisal Rehman, Ali Aman, Kashif Iqbal, and Agha Ali Nawaz. "Defect minimization and process improvement in SMT lead-free solder paste printing: a comparative study." Soldering & Surface Mount Technology 32, no. 1 (September 19, 2019): 1–9. http://dx.doi.org/10.1108/ssmt-05-2019-0019.

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Purpose The purpose of this paper is to investigate and minimize the printing-related defects in the surface mount assembly (SMA) process. Design/methodology/approach This paper uses an experimental approach to explore process parameter and printing defects during the SMA process. Increasing printing performance, various practices of solder paste (Ag3.0/Cu0.5/Sn) storage and handling are suggested. Lopsided paste problem is studied by varying squeegee pressure and the results are presented. Unfilled pads problems are observed for ball grid array (BGA) and quad flat package (QFP) which is mitig

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18

Aravamudhan, Srinivasa, Daryl Santos, Gerald Pham-Van-Diep, and Frank Andres. "Characterization of the Solder Paste Release From Small Stencil Apertures in the Stencil Printing Process." Journal of Electronic Packaging 127, no. 3 (December 10, 2004): 340–52. http://dx.doi.org/10.1115/1.1938208.

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Stencil printing is a critical first step in surface mount assembly. However, its robustness can be called into question because of the fact that about 50% or more of the defects found in the assembly of printed circuit boards (PCBs) are attributed to stencil printing 1. Manufacturing techniques for the assembly of certain flip chips, chip scale packages, 0201s, and fine pitch ball grid arrays are testing the limits of current stencil printing capabilities. This paper focuses on understanding the release of solder paste from the stencil, based on experimental and modeling approaches. The prima

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19

Weise, Thomas, and Raymond Chiong. "A Novel Extremal Optimization Approach for the Template Design Problem." International Journal of Organizational and Collective Intelligence 2, no. 2 (April 2011): 1–16. http://dx.doi.org/10.4018/joci.2011040101.

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This paper presents a novel algorithm based on extremal dynamics for tackling the template design problem, a constrained optimization problem that originated in the printing industry. The template design problem involves printing several variations of a design onto one or more stencil sheets, where the aims are to minimize the number of stencils as well as the overproduction of prints of a particular design. In this paper, the authors introduce several search operators to be used in conjunction with the proposed algorithm. Different combinations of these search operators are tested via extensi

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20

Krammer, Oliver, Benjámin Gyarmati, András Szilágyi, Richárd Storcz, László Jakab, Balázs Illés, Attila Géczy, and Karel Dušek. "Investigating the thixotropic behaviour of Type 4 solder paste during stencil printing." Soldering & Surface Mount Technology 29, no. 1 (February 6, 2017): 10–14. http://dx.doi.org/10.1108/ssmt-10-2016-0022.

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Purpose A measurement method has been developed to reveal the viscosity change of solder pastes during stencil printing. This paper aimed to investigate thixotropic behaviour, the viscosity change of a lead-free solder paste (Type 4). Design/methodology/approach The viscosity change of the solder paste during stencil printing cycles was characterised in such a way that the time-gap between the printing cycles was modelled with a rest period between every rheological measurement. This period was set as 15, 30 and 60 s during the research. The Cross model was fitted to the measurement results, a

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21

Kenny, Stephen, Kai Matejat, Sven Lamprecht, and Olivier Mann. "Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000729–34. http://dx.doi.org/10.4071/isom-2012-wa63.

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Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications. This paper describes latest developments in the electrolytic depositio

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Briggs, Ed. "Optimal SMT Electronics Assembly Guidelines for Stencil Printing." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000126–34. http://dx.doi.org/10.4071/isom-2015-tp46.

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The continuing miniaturization of personal electronics devices, such as mobile phones, personal music devices, and personal computing devices has driven the need for increasingly smaller active and passive electrical components. Not too long ago, 0402 (40 × 20mils) passives were seen as the ultimate in miniaturization, but recently 0201 and now 01005 passives have arrived, with predictions of even smaller sizes to come. For active components, the 30mil CSP (a chip-scale package with the solder balls on 30mil/0.75mm centers) has virtually become a requirement for enabling the many features requ

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Sahay, C., L. M. Head, R. Shereen, P. Dujari, J. H. Constable, and G. Westby. "Study of Print Release Process in Solder Paste Printing." Journal of Electronic Packaging 117, no. 3 (September 1, 1995): 230–34. http://dx.doi.org/10.1115/1.2792097.

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Solder paste printing is central to the mass reflow soldering process for surface mount technology. The miniaturization of components has put an increased demand on the printing process and requires it to successfully print 75 μm-100 μm(3 to 4 mil) wide apertures. The amount of solder paste deposited is a matter of concern. This study presents results from experiments on printing with apertures having circular, rectangular, square and triangular geometries. The ratio of the printed volume to the aperture volume has been used as a definition of print quality. It was observed that acceptable pri

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Shorina, O., and J. Müller. "Improvement of ampacity of LTCC conductors." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (September 1, 2012): 000385–87. http://dx.doi.org/10.4071/cicmt-2012-wa47.

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Improvement of the current load-carrying capacity can be achieved by combining different technologies in Low Temperature Cofired Ceramics (LTCC). Screen and stencil printing, full tape thickness features (FTTF) and embossing in LTCC were investigated. Silver paste conductors with 80 – 200 μm line width are included in the study. The structures on the test substrates are fed with an increasing current until the surface reaches an equilibrium temperature of 100°C measured by an infrared camera. 200 μm lines created by screen printing and stencil printing are able to bear 4.3 A and 14 A, respecti

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Krammer, Olivér, László Milán Molnár, László Jakab, and András Szabó. "Modelling the effect of uneven PWB surface on stencil bending during stencil printing process." Microelectronics Reliability 52, no. 1 (January 2012): 235–40. http://dx.doi.org/10.1016/j.microrel.2011.08.012.

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Lazarus, Nathan, Sarah S. Bedair, and Iain M. Kierzewski. "Ultrafine Pitch Stencil Printing of Liquid Metal Alloys." ACS Applied Materials & Interfaces 9, no. 2 (January 9, 2017): 1178–82. http://dx.doi.org/10.1021/acsami.6b13088.

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Clements, David J., Marc P. Y. Desmulliez, and Eitan Abraham. "The evolution of paste pressure during stencil printing." Soldering & Surface Mount Technology 19, no. 3 (July 3, 2007): 9–14. http://dx.doi.org/10.1108/09540910710843720.

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Kay, Robert, and Marc Desmulliez. "A review of stencil printing for microelectronic packaging." Soldering & Surface Mount Technology 24, no. 1 (February 3, 2012): 38–50. http://dx.doi.org/10.1108/09540911211198540.

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Li, Y., R. L. Mahajan, and N. Nikmanesh. "Fine Pitch Stencil Printing Process Modeling and Optimization." Journal of Electronic Packaging 118, no. 1 (March 1, 1996): 1–6. http://dx.doi.org/10.1115/1.2792121.

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In this paper, we present a statistical-neural network modeling approach to process optimization of fine pitch stencil printing for solder paste deposition on pads of printed circuit boards (PCB). The overall objective was to determine the optimum settings of the design parameters that would result in minimum solder paste height variation for the new board designs with 20-mil, 25-mil, and 50-mil pitch pad patterns. As a first step, a Taguchi orthogonal array, L27, was designed to capture the main effects of the six important printing machinery parameters and the PCBs pad conditions. Some of th

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HASLEHURST, L., and N. N. EKERE. "PARAMETER INTERACTIONS IN STENCIL PRINTING OF SOLDER PASTE." Journal of Electronics Manufacturing 06, no. 04 (December 1996): 307–16. http://dx.doi.org/10.1142/s0960313196000251.

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STACEY, H. J. "Improvements in or connected with Stencil Printing Apparatus." Journal of the Society of Dyers and Colourists 23, no. 10 (October 22, 2008): 255. http://dx.doi.org/10.1111/j.1478-4408.1907.tb00389.x.

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Li, L., and P. Thompson. "Stencil printing process development for flip chip interconnect." IEEE Transactions on Electronics Packaging Manufacturing 23, no. 3 (July 2000): 165–70. http://dx.doi.org/10.1109/6104.873243.

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Seong, Kwang-dong, Jae-Yeong Jung, Jeongmin Kang, Da-Seul Kim, Lulu Lyu, Soonmin Seo, Ju-Hyung Kim, and Yuanzhe Piao. "Direct printing of high-performance micro-supercapacitors on flexible substrates using polymeric stencil masks with highly precise interdigitated patterns." Journal of Materials Chemistry A 8, no. 48 (2020): 25986–94. http://dx.doi.org/10.1039/d0ta09811f.

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A direct printing method for micro-supercapacitors, based on metal–organic deposition inks and polymeric stencil masks, is presented, facilitating simultaneous fabrication of multiple devices with outstanding electrochemical properties.

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Kaneko, Tsukasa, Kazuki Iwata, and Makiko Kobayashi. "Piezoelectric sol-gel composite film fabrication by stencil printing." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 62, no. 9 (September 2015): 1686–95. http://dx.doi.org/10.1109/tuffc.2014.006870.

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Lin, Jhih-Fong, Melinda Mohl, Mikko Nelo, Geza Toth, Ákos Kukovecz, Zoltán Kónya, Srividya Sridhar, et al. "Facile synthesis of nanostructured carbon materials over RANEY® nickel catalyst films printed on Al2O3 and SiO2 substrates." Journal of Materials Chemistry C 3, no. 8 (2015): 1823–29. http://dx.doi.org/10.1039/c4tc02442g.

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Films of porous RANEY® Ni catalyst particles deposited on substrates by stencil printing offer a facile platform for synthesizing nanostructured carbon/nickel composites for direct use as electrodes in electrochemical and field emitter devices.

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Li, Y., R. L. Mahajan, and G. Subbarayan. "The Effect of Stencil Printing Optimization on Reliability of CBGA and PBGA Solder Joints." Journal of Electronic Packaging 120, no. 1 (March 1, 1998): 54–60. http://dx.doi.org/10.1115/1.2792286.

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As a follow-up and conclusion to previous work in stencil printing process modeling and optimization (Li et al., 1996), we investigate the effect of stencil printing optimization on the reliability of the ceramic and plastic ball grid arrays. For ceramic ball grid arrays, the eutectic solder fillet shape is calculated using a series of simple mathematical equations. The thermal strain distributions within the solder joints after two cycles of accelerated thermal cycling test are estimated using three-dimensional finite element models. The modified Coffin-Manson relationship is applied to calcu

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Krammer, Oliver, Tareq I. Al-Ma’aiteh, Balazs Illes, David Bušek, and Karel Dušek. "Numerical investigation on the effect of solder paste rheological behaviour and printing speed on stencil printing." Soldering & Surface Mount Technology 32, no. 4 (June 23, 2020): 219–23. http://dx.doi.org/10.1108/ssmt-11-2019-0037.

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Purpose The purpose of this paper is to investigate the effect of different viscosity models (Cross and Al-Ma’aiteh) and different printing speeds on the numerical results (e.g. pressure over stencil) of a numerical model regarding stencil printing. Design/methodology/approach A finite volume model was established for describing the printing process. Two types of viscosity models for non-Newtonian fluid properties were compared. The Cross model was fitted to the measurement results in the initial state of a lead-free solder paste, and the parameters of a Al-Ma’aiteh material model were fitted

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Zhang, Teng, Xiaoqing Mu, Ming Jiang, Leping Huang, and Jinchao Zhao. "Use of electrospun fiber membrane as the screen printing stencil for high definition printing." Materials Research Express 6, no. 11 (November 8, 2019): 1150h7. http://dx.doi.org/10.1088/2053-1591/ab51d2.

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Rodriguez, G., and D. F. Baldwin. "Analysis of Solder Paste Release in Fine Pitch Stencil Printing Processes." Journal of Electronic Packaging 121, no. 3 (September 1, 1999): 169–78. http://dx.doi.org/10.1115/1.2792680.

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Advanced electronics packaging technologies such as chip scale packages, fine pitch ball grid arrays, and flip chip are pushing solder paste stencil printing to the limit. In order to achieve solder print deposits of the sizes required for emerging electronic packaging technology, a rigorous understanding of the process is required. This paper seeks to expand our understanding of the physical characteristics of stencil printing specifically focusing on the solder paste release process based on experimental and analytical approaches. First, designed experiments were conducted to identify the ma

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Ezawa, Hirokazu, Masaharu Seto, Masahiro Miyata, and Hiroshi Tazawa. "Polymer film deposition with fine pitch openings by stencil printing." Microelectronics Reliability 43, no. 3 (March 2003): 473–79. http://dx.doi.org/10.1016/s0026-2714(02)00327-x.

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Khader, Nourma, and Sang Won Yoon. "Online control of stencil printing parameters using reinforcement learning approach." Procedia Manufacturing 17 (2018): 94–101. http://dx.doi.org/10.1016/j.promfg.2018.10.018.

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Khader, Nourma, Jaehwan Lee, Duk Lee, Sang Won Yoon, and Haeyong Yang. "Multi-objective optimization approach to enhance the stencil printing quality." Procedia Manufacturing 38 (2019): 163–70. http://dx.doi.org/10.1016/j.promfg.2020.01.022.

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Partridge, S. A. "The Rôle of the Stencil in High Definition Screen Printing." Circuit World 13, no. 2 (January 1987): 4–13. http://dx.doi.org/10.1108/eb043860.

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Barajas, Leandro G., Magnus B. Egerstedt, Edward W. Kamen, and Alex Goldstein. "Stencil Printing Process Modeling and Control Using Statistical Neural Networks." IEEE Transactions on Electronics Packaging Manufacturing 31, no. 1 (January 2008): 9–18. http://dx.doi.org/10.1109/tepm.2007.914236.

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Mannan, S. H., N. N. Ekere, I. Ismail, and E. K. Lo. "Squeegee deformation study in the stencil printing of solder pastes." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A 17, no. 3 (1994): 470–76. http://dx.doi.org/10.1109/95.311758.

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Lau, J. H., and C. Chang. "Taguchi design of experiment for wafer bumping by stencil printing." IEEE Transactions on Electronics Packaging Manufacturing 23, no. 3 (July 2000): 219–25. http://dx.doi.org/10.1109/6104.873251.

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Ishak, M. H. H., M. S. Abdul Aziz, M. H. S. Abdul Samad, Farzad Ismail, and M. A. A. Mohd Salleh. "Influence of squeegee impact on stencil printing process: CFD approach." IOP Conference Series: Materials Science and Engineering 957 (November 25, 2020): 012065. http://dx.doi.org/10.1088/1757-899x/957/1/012065.

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Tsai, Tsung-Nan. "Modeling and optimization of stencil printing operations: A comparison study." Computers & Industrial Engineering 54, no. 3 (April 2008): 374–89. http://dx.doi.org/10.1016/j.cie.2007.08.001.

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Rangelow, I. W., F. Shi, P. Hudek, I. Kostic, E. Hammel, H. Löschner, G. Stengl, and E. Cekan. "Silicon stencil masks for masked ion beam lithography proximity printing." Microelectronic Engineering 30, no. 1-4 (January 1996): 257–60. http://dx.doi.org/10.1016/0167-9317(95)00240-5.

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Khader, Nourma, and Sang Won Yoon. "Adaptive optimal control of stencil printing process using reinforcement learning." Robotics and Computer-Integrated Manufacturing 71 (October 2021): 102132. http://dx.doi.org/10.1016/j.rcim.2021.102132.

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