Bibliografias temáticas / PCM memory

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Literatura científica selecionada sobre o tema "PCM memory"

Autor: Grafiati

Publicado: 7 de julho de 2024

Última modificação: 31 de julho de 2025

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Artigos de revistas sobre o assunto "PCM memory"

Priya, Bhukya Krishna, and N. Ramasubramanian. "Improving the Lifetime of Phase Change Memory by Shadow Dynamic Random Access Memory." International Journal of Service Science, Management, Engineering, and Technology 12, no. 2 (2021): 154–68. http://dx.doi.org/10.4018/ijssmet.2021030109.

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Emerging NVM are replacing the conventional memory technologies due to their huge cell density and low energy consumption. Restricted writes is one of the major drawbacks to adopt PCM memories in real-time environments. The non-uniform writes and process variations can damage the memory cell with intensive writes, as PCM memory cells are having restricted write endurance. To prolong the lifetime of a PCM, an extra DRAM shadow memory has been added to store the writes that comes to the PCM and to level out the wearing that occurs on the PCM. An extra address directory will store the address of

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Arjomand, Mohammad, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita R. Das. "HL-PCM: MLC PCM Main Memory with Accelerated Read." IEEE Transactions on Parallel and Distributed Systems 28, no. 11 (2017): 3188–200. http://dx.doi.org/10.1109/tpds.2017.2705125.

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Jabarov, Elkhan, Byung-Won On, Gyu Choi, and Myong-Soon Park. "R-Tree for phase change memory." Computer Science and Information Systems 14, no. 2 (2017): 347–67. http://dx.doi.org/10.2298/csis160620008j.

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Nowadays, many applications use spatial data for instance-location information, so storing spatial data is important.We suggest using R -Tree over PCM. Our objective is to design a PCM-sensitive R -Tree that can store spatial data as well as improve the endurance problem. Initially, we examine how R -Tree causes endurance problems in PCM, and we then optimize it for PCM. We propose doubling the leaf node size, writing a split node to a blank node, updating parent nodes only once and not merging the nodes after deletion when the minimum fill factor requirement does not meet. Based on our experi

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Macyna, Wojciech, and Michal Kukowski. "Adaptive Merging on Phase Change Memory." Fundamenta Informaticae 188, no. 2 (2023): 103–26. http://dx.doi.org/10.3233/fi-222144.

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Indexing is a well-known database technique used to facilitate data access and speed up query processing. Nevertheless, the construction and modification of indexes are very expensive. In traditional approaches, all records in the database table are equally covered by the index. It is not effective, since some records may be queried very often and some never. To avoid this problem, adaptive merging has been introduced. The key idea is to create an index adaptively and incrementally as a side-product of query processing. As a result, the database table is indexed partially depending on the quer

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Antolini, Alessio, Francesco Zavalloni, Andrea Lico, et al. "The Role of Phase-Change Memory in Edge Computing and Analog In-Memory Computing: An Overview of Recent Research Contributions and Future Challenges." Sensors 25, no. 12 (2025): 3618. https://doi.org/10.3390/s25123618.

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Phase Change Memory (PCM) has emerged as a promising non-volatile memory technology with significant applications in both edge computing and analog in-memory computing. This paper synthesizes recent research contributions on the use of PCM for smart sensing, structural health monitoring, neural network acceleration, and binary pattern matching. By examining key advancements, challenges, and potential future developments, this work provides a comprehensive state-of-the-art overview of PCM in these domains, highlighting the possible employments of PCM technology in further edge computing scenari

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Hong, Jeong Beom, Young Sik Lee, Yong Wook Kim, and Tae Hee Han. "Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory." Electronics 9, no. 4 (2020): 626. http://dx.doi.org/10.3390/electronics9040626.

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Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where t

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Tang, Pu, Jing Xiao, and Ming Tao. "Thermal Crosstalk Analysis of Phase Change Memory Considering Thermoelectric Effect and Thermal Boundary Resistance." Journal of Physics: Conference Series 2624, no. 1 (2023): 012020. http://dx.doi.org/10.1088/1742-6596/2624/1/012020.

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Abstract Phase change memory (PCM) has emerged as a promising memory for next-generation applications due to its high-speed read and write capabilities as well as non-volatility. However, as PCM scales down to smaller feature sizes, it faces the challenge of thermal crosstalk. During the reset operation, a large amount of heat is generated and dissipated in the PCM array, potentially affecting adjacent memory cells, compromising device stability, and limiting high-density integration. To accurately investigate the thermal crosstalk in the PCM array, the conventional finite element model of the

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Ding, Feilong, Baokang Peng, Xi Li, et al. "A review of compact modeling for phase change memory." Journal of Semiconductors 43, no. 2 (2022): 023101. http://dx.doi.org/10.1088/1674-4926/43/2/023101.

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Abstract Phase change memory (PCM) attracts wide attention for the memory-centric computing and neuromorphic computing. For circuit and system designs, PCM compact models are mandatory and their status are reviewed in this work. Macro models and physics-based models have been proposed in different stages of the PCM technology developments. Compact modeling of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical, thermal and phase transition dynamics as well as their interactions. Realizations of the PCM operations including threshold sw

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Sun, Hao, Lan Chen, Xiaoran Hao, Chenji Liu, and Mao Ni. "An Energy-Efficient and Fast Scheme for Hybrid Storage Class Memory in an AIoT Terminal System." Electronics 9, no. 6 (2020): 1013. http://dx.doi.org/10.3390/electronics9061013.

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Conventional main memory can no longer meet the requirements of low energy consumption and massive data storage in an artificial intelligence Internet of Things (AIoT) system. Moreover, the efficiency is decreased due to the swapping of data between the main memory and storage. This paper presents a hybrid storage class memory system to reduce the energy consumption and optimize IO performance. Phase change memory (PCM) brings the advantages of low static power and a large capacity to a hybrid memory system. In order to avoid the impact of poor write performance in PCM, a migration scheme impl

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Stern, Keren, Yair Keller, Christopher M. Neumann, Eric Pop, and Eilam Yalon. "Temperature-dependent thermal resistance of phase change memory." Applied Physics Letters 120, no. 11 (2022): 113501. http://dx.doi.org/10.1063/5.0081016.

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One of the key challenges of phase change memory (PCM) is its high power consumption during the reset operation, when the phase change material (typically Ge2Sb2Te5, i.e., GST) heats up to ∼900 K or more in order to melt. Here, we study the temperature-dependent behavior of PCM devices by probing the reset power at ambient temperatures from 80 to 400 K. We find that different device structures exhibit contrasting temperature-dependent behavior. The reset power in our confined-type PCM is nearly unchanged with ambient temperature, corresponding to a temperature-dependent thermal resistance, whe

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Teses / dissertações sobre o assunto "PCM memory"

Grönberg, Axel. "Emerging Non-Volatile Memory and Initial Experiences with PCM Main Memory." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-407070.

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A group of new non-volatile memory technologies with characteristics making them worthy of consideration for different parts of the memory hierarchy, including the main memory, are emerging. In this thesis I discuss the state of STT-RAM, ReRAM and PCM technologies which are three of the front runners in this group of new technologies. I also simulate the performance of PCM used as main memory using Intel’s binary instrumentation framework Pin and compare it to DRAM to explore three research questions. Firstly, in the case of horizontally integrated PCM and DRAM I test a data mapping policy whe

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Seong, Nak Hee. "A reliable, secure phase-change memory as a main memory." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50123.

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The main objective of this research is to provide an efficient and reliable method for using multi-level cell (MLC) phase-change memory (PCM) as a main memory. As DRAM scaling approaches the physical limit, alternative memory technologies are being explored for future computing systems. Among them, PCM is the most mature with announced commercial products for NOR flash replacement. Its fast access latency and scalability have led researchers to investigate PCM as a feasible candidate for DRAM replacement. Moreover, the multi-level potential of PCM cells can enhance the scalability by increasin

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SELMO, SIMONE. "Functional analysis of In-based nanowires for low power phase change memory applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/153247.

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Phase change memories (PCMs), based on chalcogenide alloys (mainly Ge2Sb2Te5), are the most promising candidate for the realization of “Storage Class Memories”, which would fill the gap between ‘‘operation’’ and ‘‘storage’’ memories. PCMs are also one of the few currently available technologies for the implementation of nanoeletronic synapses in high density neuromorphic systems. The main improvements needed in order to exploit the full potential of PCMs in these innovative applications are the reduction of the programming currents and power consumption, and further cell downscaling. Thanks to

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Garbin, Daniele. "Etude de la variabilité des technologies PCM et OxRAM pour leur utilisation en tant que synapses dans les systèmes neuromorphiques." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT133/document.

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Le cerveau humain est composé d’un grand nombre de réseaux neuraux interconnectés, dont les neurones et les synapses en sont les briques constitutives. Caractérisé par une faible consommation de puissance, de quelques Watts seulement, le cerveau humain est capable d’accomplir des tâches qui sont inaccessibles aux systèmes de calcul actuels, basés sur une architecture de type Von Neumann. La conception de systèmes neuromorphiques vise à réaliser une nouvelle génération de systèmes de calcul qui ne soit pas de type Von Neumann. L’utilisation de mémoire non-volatile innovantes en tant que synapse

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Balasubramanian, Sanchayeni. "Improving Hard Disk Drive Write IO Performance with Phase Change Memory as a Buffer Cache." University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1511881125562903.

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Baek, Seungcheol. "High-performance memory system architectures using data compression." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51863.

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The Chip Multi-Processor (CMP) paradigm has cemented itself as the archetypal philosophy of future microprocessor design. Rapidly diminishing technology feature sizes have enabled the integration of ever-increasing numbers of processing cores on a single chip die. This abundance of processing power has magnified the venerable processor-memory performance gap, which is known as the ”memory wall”. To bridge this performance gap, a high-performing memory structure is needed. An attractive solution to overcoming this processor-memory performance gap is using compression in the memory hierarchy. In

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Trabelsi, Ahmed. "Modulation des niveaux de résistance dans une mémoire PCM pour des applications neuromorphiques." Electronic Thesis or Diss., Université Grenoble Alpes, 2024. http://www.theses.fr/2024GRALT027.

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La croissance exponentielle des données au cours des dernières années a entraîné une augmentation significative de la consommation d'énergie, créant ainsi un besoin urgent de technologies de mémoire innovantes pour surmonter les limitations des solutions conventionnelles. Cette inondation de données a entraîné une augmentation prévue de la consommation dans les centres de données, avec une multiplication par quatre des données d'ici 2025 par rapport au volume actuel. Pour relever ce défi, des technologies de mémoire émergentes telles que la RRAM (RAM résistive), la PCM (mémoire à changement de

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Jensen, Peter, and Christopher Thacker. "A NEW GENERATION OF RECORDING TECHNOLOGY THE SOLID STATE RECORDER." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/607372.

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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California<br>The Test & Evaluation community is starting to migrate toward solid state recording. This paper outlines some of the important areas that are new to solid state recording as well as examining some of the issues involved in moving to a direct recording methodology. Some of the parameters used to choose a solid state memory architecture are included. A matrix to compare various methods of data recording, such as solid state and magnetic tape r

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Kiouseloglou, Athanasios. "Caractérisation et conception d' architectures basées sur des mémoires à changement de phase." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT128/document.

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Les mémoires à base de semi-conducteur sont indispensables pour les dispositifs électroniques actuels. La demande croissante pour des dispositifs mémoires fortement miniaturisées a entraîné le développement de mémoires non volatiles fiables qui sont utilisées dans des systèmes informatiques pour le stockage de données et qui sont capables d'atteindre des débits de données élevés, avec des niveaux de dissipation d'énergie équivalents voire moindres que ceux des technologies mémoires actuelles.Parmi les technologies de mémoires non-volatiles émergentes, les mémoires à changement de phase (PCM) s

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Navarro, Gabriele. "Analyse de la fiabilité de mémoires à changement de phase embarquées basées sur des matériaux innovants." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01061792.

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Les Mémoires ont de plus en plus importance à l'époque actuelle, et sont fondamentales pour la définition de tous les systèmes électroniques avec lesquels nous entrons en contact dans notre vie quotidienne. Les mémoires non-volatiles (NVM), représentées par la technologie Flash, ont pu suivre jusqu'à présent l'effort à la miniaturisation pour satisfaire la demande croissante de densité de mémoire exigée par le marché. Cependant, la réduction de la taille du dispositif de mémoire est de plus en plus difficile et la complexité technologique demandé a augmenté le coût par octet. Dans ce contexte,

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Livros sobre o assunto "PCM memory"

Wadlow, Thomas A. Memory resident programming on the IBM PC. Addison-Wesley, 1987.

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Prosise, Jeff. PCmagazine DOS 6 memory management with utilities. Ziff-Davis Press, 1993.

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Hyman, Michael I. Memory resident utilities, interrupts, and disk management with MS and PC DOS. Management Information Source, 1986.

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Mueller, Scott. Upgrading and repairing PCs. Que, 1998.

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Mueller, Scott. Upgrading and repairing PCs. Que, 2001.

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Prosise, Jeff. PC magazine DOS 6 memory management with utilities. Ziff-Davis Press, 1993.

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Store, Linux General, ed. Upgrading and repairing PCs. Que, 2000.

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Scott, Mueller. Upgrading and repairing PCs. 4th ed. Que, 1994.

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Scott, Mueller. Upgrading and Repairing PCs. Pearson Education, 2005.

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Scott, Mueller. Upgrading and repairing PCs. Que, 2003.

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Capítulos de livros sobre o assunto "PCM memory"

Gleixner, Robert. "PCM Main Reliability Features." In Phase Change Memory. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_5.

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Villa, Corrado. "PCM Array Architecture and Management." In Phase Change Memory. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_10.

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Sousa, Véronique, and Gabriele Navarro. "Material Engineering for PCM Device Optimization." In Phase Change Memory. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_7.

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Atwood, Gregory. "PCM Applications and an Outlook to the Future." In Phase Change Memory. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_11.

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Noé, Pierre, and Françoise Hippert. "Structure and Properties of Chalcogenide Materials for PCM." In Phase Change Memory. Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69053-7_6.

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Kong, Dejiang, and Fei Wu. "Visual Dialog with Multi-turn Attentional Memory Network." In Advances in Multimedia Information Processing – PCM 2018. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-00776-8_56.

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Rahiman, Amir Rizaan Abdul, and Putra Sumari. "Probability Based Page Data Allocation Scheme in Flash Memory." In Advances in Multimedia Information Processing - PCM 2009. Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10467-1_26.

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Noh, Tae Hoon, and Se Jin Kwon. "Memory Management Strategy for PCM-Based IoT Cloud Server." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1059-1_7.

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Chen, Kaimeng, Peiquan Jin, and Lihua Yue. "Efficient Buffer Management for PCM-Enhanced Hybrid Memory Architecture." In Web Technologies and Applications. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-25255-1_3.

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Li, Fu, Shaowu Yang, Xiaodong Yi, and Xuejun Yang. "Towards Visual SLAM with Memory Management for Large-Scale Environments." In Advances in Multimedia Information Processing – PCM 2017. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77383-4_76.

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Trabalhos de conferências sobre o assunto "PCM memory"

Piccinini, E., N. Giuliani, M. Baldo, et al. "Simulation of Ge-rich PCM Device Material Evolution from Post-Deposition Anneal to Programming Operations." In 2025 IEEE International Memory Workshop (IMW). IEEE, 2025. https://doi.org/10.1109/imw61990.2025.11026941.

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Boybat, I., T. Boesch, M. Allegra, et al. "Heterogeneous Embedded Neural Processing Units Utilizing PCM-Based Analog In-Memory Computing." In 2024 IEEE International Electron Devices Meeting (IEDM). IEEE, 2024. https://doi.org/10.1109/iedm50854.2024.10873479.

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Ferreira, Alexandre P., Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem, and Daniel Mosse. "Increasing PCM main memory lifetime." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5456923.

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Liu, Yining, Chuangshi Zhou, and Xiaohua Cheng. "Hybrid SSD with PCM." In 2011 11th Annual Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2011. http://dx.doi.org/10.1109/nvmts.2011.6137103.

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Chang, Yu-Ming, Yuan-Hao Chang, Hsiu-Chang Chen, and Tei-Wei Kuo. "Enabling Hybrid PCM Memory System with Inherent Memory Management." In RACS '16: International Conference on Research in Adaptive and Convergent Systems. ACM, 2016. http://dx.doi.org/10.1145/2987386.2987398.

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Arjomand, Mohammad, Amin Jadidi, Mahmut T. Kandemir, Anand Sivasubramaniam, and Chita Das. "MLC PCM main memory with accelerated read." In 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 2016. http://dx.doi.org/10.1109/ispass.2016.7482082.

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Jeong, Hongsik. "High density PCM(phase change memory) technology." In 2016 International SoC Design Conference (ISOCC). IEEE, 2016. http://dx.doi.org/10.1109/isocc.2016.7799850.

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Boybat, I., S. R. Nandakumar, M. Le Gallo, et al. "Impact of conductance drift on multi-PCM synaptic architectures." In 2018 Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2018. http://dx.doi.org/10.1109/nvmts.2018.8603100.

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Calderoni, A., M. Ferro, D. Ventrice, P. Fantini, and D. Ielmini. "Physical Modeling and Control of Switching Statistics in PCM Arrays." In 2011 3rd IEEE International Memory Workshop (IMW). IEEE, 2011. http://dx.doi.org/10.1109/imw.2011.5873230.

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Bez, Roberto. "Chalcogenide PCM: a memory technology for next decade." In 2009 IEEE International Electron Devices Meeting (IEDM). IEEE, 2009. http://dx.doi.org/10.1109/iedm.2009.5424415.

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Relatórios de organizações sobre o assunto "PCM memory"

Murphy, Richard C. Building more powerful less expensive supercomputers using Processing-In-Memory (PIM) LDRD final report. Office of Scientific and Technical Information (OSTI), 2009. http://dx.doi.org/10.2172/993898.

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Mott, Joanna, Heather Brown, Di Kilsby, Emily Eller, and Tshering Choden. Ferramenta de auto-avaliação de Igualdade de Género e Inclusão Social. The Sanitation Learning Hub, Institute of Development Studies, 2022. http://dx.doi.org/10.19088/slh.2022.021.

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Este guia foi criado para o pessoal de implementação, projectos de investigação e organizações de WASH, que está empenhado em melhorar a prática de IGIS nos seus projectos e organizações. Destina-se a gestores de programas, assessores IGIS e investigadores de IGIS e qualquer membro do pessoal da sua organização interessado em melhorar a prática de IGIS. O guia detalha as funções e responsabilidades específicas do Ponto de Contacto (PC), do facilitador, dos participantes e auxiliares do processo de auto-avaliação.

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