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1
Vykydal, Lukáš. "Mikroprogramem řízený RAM BIST." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316440.
Анотація:
The goal of this work is to understand types of defects in semiconductor memories and algorithms for their testing. In the second part the work describes design and implementation of programmable BIST controller with small digital block size requirments.
2
Boutobza, Slimane. "Outils de génération de structures BIST/BISR pour mémoires." Grenoble INPG, 2002. http://www.theses.fr/2002INPG0166.
Анотація:
Les Systems on Chip (SoC) actuels intègrent en général une grande proportion de mémoires enterrées. Ces mémoires sont de plus en plus denses et occupent des surfaces très importantes dans le circuit (jusqu'à 80%). Ces mémoires peuvent présenter un grand taux de défauts affectant ainsi d'une façon conséquente le rendement total du circuit. La qualité de la mémoire et donc cruciale pour la qualité de l'ensemble du circuit. D'autre part, la réduction du coût du développement passe par la réduction du coût du test. Enfin, le management de la complexité de test des structures de plus en plus complexes (e. G. , il existe actuellement des SoC contenant plus de 400 mémoires enterrées !), ne peut se faire d'une manière efficace sans la disposition et l'intégration des techniques de test les plus avancées. La clé du succès d'une bonne stratégie de test passe par les exigences d'une qualité élevée du test et de son automatisation. À travers la première partie des travaux réalisés dans cette thèse, nous avons tenté de répondre à l'exigence de la qualité de test en présentant un ensemble assez diversifié de solutions de test intégré (BIST) pour mémoires. Ces solutions couvrent les différents types de test d'une mémoire: test de caractérisation et de débuggage des processus de fabrication instables, test de production, test durant la phase opérationnelle et test d'analyse des défauts. Ces solutions permettent de palier aux limitations des techniques BIST existantes, telles que le meilleur compromis couverture de fautes/coût en surface et la garantie d'un test à la fréquence nominale. Ce dernier point a été pris en compte en proposant une technique d'optimisation temporelle (appelée Rapid BIST) des architectures BISTs élaborées, qui permet une réduction du temps de test et une meilleure couverture de faute en assurant un test à la fréquence nominale même pour les mémoires très rapides (afin de couvrir les fautes de délai). Ces différents avantages sont offerts sans pour autant négliger le coût additionnel en surface. Nous avons également développé une technique CBISR (Column BISR) qui permet d'assurer un rendement de production élevé et une durée de vie prolongée en particulier pour les mémoires de grandes tailles. La seconde partie de cette thèse adressait le problème de la génération automatique des solutions élaborées en concevant et implémentant un outil de synthèse de structures BIST/BISR pour mémoires. Cet outil innove à la fois par l'approche de son implémentation et par les fonctionnalités offertes. Afin de permettre une implémentation efficace, il utilise une approche originale de synthèse de BIST pour les tests de mémoires. Cette approche est basée sur la notion de perturbation par rapport à un axe médian représenté par les tests Marchs. Hormis quelques tests électriques, cette approche de synthèse permet de synthétiser (sur le tas) n'importe quel algorithme de test pour mémoires en une architecture BIST compacte. D'autre part, cette approche est suffisamment flexible pour pouvoir supporter la synthèse des algorithmes de test qui pourront être développés. Il suffit pour cela de supporter leurs perturbations. Les blocs matériels bas niveau sont conçus en utilisant un langage de description spéciale (CHDL) qui est lui-même modélisé sous forme de structure de données écrites dans un langage haut niveau (C++). L'outil implémente un ensemble assez large de solutions BIST/BISR notamment ceux développés dans le cadre de cette thèse. Il offre une indépendance vis à vis de : - La technologie à utiliser, en offrant des descriptions RTL synthétisables. - L'environnement de conception, en générant des scripts de synthèse pour une variété d'outils de synthèse (AMBIT, Design Compiler), et des scripts de simulation pour les simulateurs les plus connus. - Du langage de description de matériel supporté par l'environnement de conception, en décrivant les architectures implémentées dans un langage interne de haut niveau (CHDL) qui pourront ensuite être translatées en langage VHDL et/ou VERILOG. Il offre enfin un mécanisme pour explorer l'espace des solutions en prenant en compte différentes stratégies d'optimisation afin de délivrer l'architecture optimale, suivant le coût en surface, et/ou la fréquence de fonctionnement, et/ou la couverture de faute et/ou la capacité de réparationModern Systems on Chip usually include large embedded memories. These memories occupy the largest part of the circuit (up to 80% of the total circuit area). Furthermore, memories are more dense than logic and thus, more prone to faults. Therefore, the quality of the memory is crucial for the overall quality of the chip. On the other hand, the reduction of the development cost passes from the reduction of the test cost. Finally, the management of the test complexity of the increasingly complex structures cannot be made with an effective manner without the provision and integration of the advanced test techniques. In the first part of the present thesis, we try to answer to test quality requirement by presenting various memory Built In Self-Test (BIST) solutions that cover all the tests required for memory: characterization test, production test, field test and defects analysis test. The proposed solutions allow handling the limitations of the existing memory BIST techniques, such as the selection of the best trade-off between fault coverage/area overhead and the guarantee of the at-speed testing. We developed also a CBISR (Column Built In Self Repair) technique that allows a significant yield improvement and a prolonged product life in particular for large memories. The second part of this thesis addresses the problem of the automation of the BIST/BISR solutions generation. This is done by designing and implementing a synthesis tool for memories BIST/BISR. This tool innovates at the same time by its implementation approach and the offered features. In order to allow an effective implementation, it uses an original approach of BIST synthesis of the memory tests. This approach is based on the concept of disturbance by report to a median axis represented by the March tests. Except some electric tests, this synthesis approach allows to synthesize any memory test algorithm. Furthermore, by supporting the disturbances of these algorithms, this approach is flexible enough to allow supporting the synthesis of new test algorithms that could be introduced in the future. It offers finally, a mechanism to explore the solutions space by taking into account various optimization strategies in order to deliver optimal architecture, with respect to area cost, the operation frequency, the fault coverage and the repair efficiency
3
Gadde, Priyanka. "A BIST Architecture for Testing LUTs in a Virtex-4 FPGA." University of Toledo / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1375316199.
4
Zaourar, Lilia Koutchoukali. "Recherche opérationnelle et optimisation pour la conception testable de circuits intégrés complexes." Grenoble, 2010. http://www.theses.fr/2010GRENM055.
Анотація:
Le travail de cette thèse est à l'interface des dom aines de la recherche opérationnelle et de la micro -électronique. Il traite de l'utilisation des techniques d'optimisation combinatoire pour la DFT (Design For Test) des Circuits Intégrés (CI). Avec la croissance rapide et la complexité des CI actuels, la qualité ainsi que le coût du test sont devenus des paramètres importants dans l'industrie des semi-conducteurs. Afin de s'assurer du bon fonctionnement du CI, l'étape de test est plus que jamais une étape essentielle et délicate dans le processus de fabrication d'un CI. Pour répondre aux exigences du marché, le test doit être rapide et efficace dans la révélation d'éventuels défauts. Pour cela, il devient incontournable d'appréhender la phase de test dès les étapes de conception du CI. Dans ce contexte, la conception testable plus connue sous l'appellation DFT vise à améliorer la testabilité des CI. Plusieurs problèmes d'optimisation et d'aide à la décision découlent de la micro-électronique. La plupart de ces travaux traitent des problèmes d'optimisation combinatoire pour le placement et routage des circuits. Nos travaux de recherche sont à un niveau de conception plus amont, la DFT en présynthèse au niveau transfert de registres ou RTL (Register Transfer Level). Cette thèse se découpe en trois parties. Dans la première partie nous introduisons les notions de bases de recherche opérationnelle, de conception et de test des CI. La démarche suivie ainsi que les outils de résolution utilisés dans le reste du document sont présentés dans cette partie. Dans la deuxième partie, nous nous intéressons au problème de l'optimisation de l'insertion des chaîne s de scan. A l'heure actuelle, le "scan interne" est une des techniques d'amélioration de testabilité ou de DFT les plus largement adoptées pour les circuits intégrés numériques. Il s'agit de chaîner les éléments mémoires ou bascules du circuit de sorte à former des chaînes de scan qui seront considérées pendant la phase de test comme points de contrôle et d'observation de la logique interne du circuit. L'objectif de notre travail est de développer des algorithmes permettant de générer pour un CI donné et dès le niveau RTL des chaînes de scan optimales en termes de surface, de temps de test et de consommation en puissance, tout en respectant des critères de performance purement fonctionnels. Ce problème a été modélisé comme la recherche de plus courtes chaînes dans un graphe pondéré. Les méthodes de résolution utilisées sont basées sur la recherche de chaînes hamiltoniennes de longueur minimale. Ces travaux ont été réalisés en collaboration avec la start-up DeFacTo Technologies. La troisième partie s'intéresse au problème de partage de blocs BIST (Built In Self Test) pour le test des mémoires. Le problème peut être formulé de la façon suivante : étant données des mémoires de différents types et tailles, ainsi que des règles de partage des colliers en série et en parallèle, il s'agit d'identifier des solutions au problème en associant à chaque mémoire un collier. La solution obtenue doit minimiser à la fois la surface, la consommation en puissance et le temps de test du CI. Pour résoudre ce problème, nous avons conçu un prototype nommé Memory BIST Optimizer (MBO). Il est constitué de deux phases de résolution et d'une phase de validation. La première phase consiste à créer des groupes de compatibilité de mémoires en tenant compte des règles de partage et d'abstraction des technologies utilisées. La deuxième phase utilise les algorithmes génétiques pour l'optimisation multi-objectifs afin d'obtenir un ensemble de solutions non dominées. Enfin, la validation permet de vérifier que la solution fournie est valide. De plus, elle affiche l'ensemble des solutions à travers une interface graphique ou textuelle. Cela permet à l'utilisateur de choisir la solution qui lui correspond le mieux. Actuellement, l'outil MBO est intégré dans un flot d'outils à ST-microelectronics pour une utilisation par ses clientsThis thesis is a research contribution interfacing operations research and microelectronics. It considers the use of combinatorial optimization techniques for DFT (Design For Test) of Integrated Circuits (IC). With the growing complexity of current IC both quality and cost during manufacturing testing have become important parameters in the semiconductor industry. To ensure proper functioning of the IC, the testing step is more than ever a crucial and difficult step in the overall IC manufacturing process. To answer market requirements, chip testing should be fast and effective in uncovering defects. For this, it becomes essential to apprehend the test phase from the design steps of IC. In this context, DFT techniques and methodologies aim at improving the testability of IC. In previous research works, several problems of optimization and decision making were derived from the micro- electronics domain. Most of previous research contributions dealt with problems of combinatorial optimization for placement and routing during IC design. In this thesis, a higher design level is considered where the DFT problem is analyzed at the Register Transfer Level (RTL) before the logic synthesis process starts. This thesis is structured into three parts. In the first part, preliminaries and basic concepts of operations research, IC design and manufacturing are introduced. Next, both our approach and the solution tools which are used in the rest of this work are presented. In the second part, the problem of optimizing the insertion of scan chains is considered. Currently, " internal scan" is a widely adopted DFT technique for sequential digital designs where the design flip-flops are connected into a daisy chain manner with a full controllability and observability from primary inputs and outputs. In this part of the research work, different algorithms are developed to provide an automated and optimal solution during the generation of an RTL scan architecture where several parameters are considered: area, test time and power consumption in full compliance with functional performance. This problem has been modelled as the search for short chains in a weighted graph. The solution methods used are based on finding minimal length Hamiltonian chains. This work was accomplished in collaboration with DeFacTo Technologies, an EDA start-up close to Grenoble. The third part deals with the problem of sharing BIST (Built In Self Test) blocks for testing memories. The problem can be formulated as follows: given the memories with various types and sizes, and sharing rules for series and parallel wrappers, we have to identify solutions to the problem by associating a wrapper with each memory. The solution should minimize the surface, the power consumption and test time of IC. To solve this problem, we designed a prototype called Memory BIST Optimizer (MBO). It consists of two steps of resolution and a validation phase. The first step creates groups of compatibility in accordance with the rules of abstraction and sharing that depend on technologies. The second phase uses genetic algorithms for multi-objective optimization in order to obtain a set of non dominated solutions. Finally, the validation verifies that the solution provided is valid. In addition, it displays all solutions through a graphical or textual interface. This allows the user to choose the solution that fits best. The tool MBO is currently integrated into an industrial flow within ST-microelectronics
5
Johnson, Patricia Lynn. "The Influence of Individual Differences on Emotional Processing and Emotional Memory." Scholar Commons, 2014. https://scholarcommons.usf.edu/etd/5245.
Анотація:
Emotional material is better remembered than neutral material and some suggest this is reflected in different Event Related potentials (ERPs) to affective stimuli by valence. Inconsistent results may be due to individual differences, specifically the behavioral inhibition/behavioral activation (BIS/BAS) motivational system. This study sought to examine the relationship between motivational systems, emotional memory, and psychophysiological response to emotional pictures. While using EEG recording, subjects were shown 150 affective pictures and given a recall and yes/no recognition task after a 20 and 30-minute delay, respectively. Overall, differences were found by valence, but not consistently based on individual trait. Controlling for arousal and mood, results did not support previous research that suggested high BIS was more responsive to negative pictures while higher BAS was more responsive to positive images. The role of ERP methodology and arousal are discussed, along with future directions.
6
Chandran, Pravin Chander. "Design of ALU and Cache memory for an 8 bit microprocessor." Connect to this title online, 2007. http://etd.lib.clemson.edu/documents/1202498822/.
7
Sumransub, Parisuth. "Cultural and linguistic adaptation of the BIRT Memory and Information Processing Battery and the Prospective and Retrospective Memory Questionnaire for Thailand." Thesis, University of Glasgow, 2018. http://theses.gla.ac.uk/30623/.
8
Pimentel, Sobrinho Alvaro Caetano. "A contribuição do conceito do bit quântico(q-bit) para os fundamentos teóricos da ciência da informação." Universidade Federal do Rio de Janeiro / Instituto Brasileiro de Informação em Ciência e Tecnologia, 2013. http://ridi.ibict.br/handle/123456789/670.
Анотація:
Made available in DSpace on 2015-10-19T11:49:43Z (GMT). No. of bitstreams: 1
pimentelsobrinho2013.pdf: 2616020 bytes, checksum: abbcfacc53dbab0dc8ddca2f8ac2b67b (MD5)
Previous issue date: 2013-03-27Study about contributions of the concept of quantum bit (q-bit) and analyze the possibilities in quantum computers processing and increase the data storage capacity for devices memory. From the analysis of the q-bit is possible to notice changing in mental and social structures beyond their direct interference in the process of memory as a way of preserving information in different formats. Observations in the contributions from Quantum Mechanics, by measuring process, for Information Science and theoretical-epistemic confluence between the two sciences complemented by some opinions around the issues that still needing answer. Insertion of terms entanglement and superposition that were identified as fundamental to understanding the concept of q-bit is the basis to accept the updates in the concepts, formulations and descriptions established in Information Science
Estudo das contribuições do conceito do bit quântico (q-bit) e suas possibilidades de processamento nos computadores quânticos e de aumento da capacidade de armazenamento dos dados em dispositivos de memória. A partir da análise do q-bit, é possível a percepção das alterações de estruturas mentais e sociais, além de sua interferência direta no processo de memória como meio de preservação de informações sob diversos formatos. Observações das contribuições a Mecânica Quântica para a Ciência da Informação e a confluência teórico epistêmica entre as duas ciências, complementadas por algumas ponderações em torno das questões que ainda necessitam de respostas. Inserção dos termos emaranhamento e superposição de estados identificados como fundamentais para o entendimento do conceito de q-bit. Tais termos são a base para dimensionar as alterações em conceitos, formulações e descrições consagrados na Ciência da Informação. Palavras-chave: Bit quântico
9
LI, HANG. "DESIGN OF A 32 BY 32 BIT READ HEAD DEVICE FOR PAGE-ORIENTED OPTICAL MEMORY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037304111.
10
Ho, Chi Ming. "Neuropharmacological and neurochemical characterization of memory enhancing effects of bis(12)-huperin, a novel dimeric acetylcholinesterase inhibitor /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?BICH%202002%20HO.
Анотація:
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.Includes bibliographical references (leaves 151-175). Also available in electronic version. Access restricted to campus users.
11
Sauer, Christine. "Fundatio und Memoria : Stifter und Klostergründer im Bild 1100 bis 1350 /." Göttingen : Vandenhoeck & Ruprecht, 1993. http://catalogue.bnf.fr/ark:/12148/cb356040571.
Анотація:
Texte remanié de: Diss.--Philosophische Fakultät für Geschichts- und Kunstwissenschaften--München--Ludwig-Maximilians-Universität, 1990. Titre de soutenance : Stifterbild und Stiftungsrecht im deutschen Mittelalter : Studien zu den Darstellungen von Klostergründern und -wohltätern.
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Kareer, Shobhit. "Fabrication of Carbon Nanotube Field Effect Transistor Using Dielectrophoresis and Its Application as Static Random Access Memory Bit Cell." Thesis, Université d'Ottawa / University of Ottawa, 2019. http://hdl.handle.net/10393/39983.
Анотація:
The aim of the thesis is to fabricate Schottky contact carbon nanotube field effect transistor (CNFET) using the dielectrophoresis (DEP) to resolve the alignment issue and show its transistor behaviour. The work presented is a combination of fabrication and simulation of CNFET. Fabrication of the device electrode had been done using the electron beam lithography to achieve a channel length of 150nm and analysis was done on an optical microscope, SEM, AFM and Raman spectroscopy. Second half of the thesis provides a solution to “bottleneck communication” between microprocessor and memory to increase the computation for applications like AI, IoT etc and 3D monolithic memories. As a solution, we propose a novel CNFET based processing in-memory architecture using a novel CNFET dual port single-ended SRAM bit cell. The combination of the CNFET and processing in-memory can be a new phase for memory and computation.
13
Charalambous, M. ""My people seem to be falling to bits" : impotence, memory, and the co-possibility of body and mind in Samuel Beckett's works." Thesis, University of Westminster, 2016. https://westminsterresearch.westminster.ac.uk/item/9y59v/-my-people-seem-to-be-falling-to-bits-impotence-memory-and-the-co-possibility-of-body-and-mind-in-samuel-beckett-s-works.
Анотація:
The present thesis examines the representation of the impotent body and mind in a selection of Samuel Beckett’s dramatic and prose works. Aiming to show that the body-mind relation is represented as one of co-implication and co-constitution, this thesis also takes the representation of memory in Beckett’s work as a key site for examining this relation. The thesis seeks to address the centrality of the body and embodied subjectivity in the experience of memory and indeed in signification and experience more generally. In these terms, Chapter 1 analyzes the representation of the figure of the couple in Beckett’s drama of the 1950s – as a metaphor of the body-mind relation – and, in light of Jacques Derrida’s theory of the supplement and Bernard Stiegler’s theory of technics, it discusses how the relationship between physical body and mind is defined by an essential supplementarity that is revealed even (or especially) in their apparent separation. Furthermore, the impotence that marks both elements in Beckett’s writings, when it is seen to lay bare this intrication, can be viewed, in important respects, as enabling rather than merely privative. Chapter 2 discusses the somatic structure of memory as represented in four of Beckett’s later dramatic works composed in the 1970s and 1980s. Similarly to Chapter 1, the second chapter focuses on the more “extreme” representation of bodily impotence in Beckett and demonstrates that rather than a merely “mental” recollection, memory in the work of Beckett is presented as necessarily experienced through, and shaped by, the body itself. In this light, then, it is shown that despite the impotence that marks the body in Beckett’s work of the 1970s and 1980s, the body is a necessary site of memory and retains or discovers a kind of activity in this impotence. Finally, Chapter 3 shifts its attention to Beckett’s prose works in order to explore how such works, reliant on language rather than the physical performance of actors onstage, sustain questions of embodied subjectivity at their heart. Specifically, the chapter argues that, on closer inspection, Beckett’s “literature of the unword” is not an abstention from meaning and its materialization, but one that paradoxically foregrounds that “something” which remains an essential part of it, that is, an embodied subjectivity.
14
Sendek, David M. "Designing a virtual-memory implementation using the Motorola MC68010 16 bit microprocessor with multi-processor capability interfaced to the VMEbus." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA232554.
Анотація:
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 1990.Thesis Advisor(s): Abbott, Larry W. Second Reader: Terman, Fred W. "June 1990." Description based on title screen as viewed on October 19, 2009. DTIC Identifier(s): Bus Oriented Microprocessors, Multi Processing, MC-68010 Microprocessors, Virtual Memories, Exception Processing, Theses. Author(s) subject terms: MC68010 Microprocessor, VMEbus, Virtual-Memory, Dual-port Memory, Multi-processor. Includes bibliographical references (p. 161). Also available online.
15
Barlas, Marios Dimitrios. "Development and characterization of innovative nonvolatile OxRAM memory cells compatible with advanced nodes." Thesis, Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0229.
Анотація:
La mémoire résistive à la base des oxydes de transition métallique (ReRAM) est une classe de technologies de mémoire non volatile dans lesquelles la commutation entre états de mémoire est rendue possible par la décomposition réversible de l’oxyde au moyen de la création et de la dissolution d’un chemin de percolation (filament). Les principaux avantages de cette technologie résident dans l’évolutivité de la cellule de mémoire, principalement en raison de la dimension inférieure à 10 nm du filament, de sa faible consommation d’énergie (<300 pJ / commutateur) et de la compatibilité des matériaux avec la technologie CMOS avancée. Néanmoins, deux obstacles majeurs ont jusqu'à présent empêché la mise en œuvre de ReRAM dans les réseaux de grande taille: premièrement, la nécessité d'une tension de claquage initiale supérieure à la tension de fonctionnement et, deuxièmement, les composantes de variabilité intrinsèque et extrinsique résultant de l'interaction des matériaux à son environnement ainsi qu’à la nature stochastique fondamentale de la conduction percolative. Ce travail est axé sur la technologie ReRAM à base de HfO2. D'abord, des alliages d'HfO2 sont étudiés. Dans la seconde partie, l’alliage HfSiOx proposé est intégré dans le BEOL d’un procédé de 130 nm et l’impact de l’intégration de la zone de commutation dans la formation, la commutation, l’évolution du taux d’erreur et la conservation des données est étudié. Dans la dernière partie, une intégration basée sur HfO2 dans le MOL ancien d’un processus CMOS FDSOI 300 mm avancé est étudiée, qui étudie les performances et les limitations standard de HfO2 ReRAMTransition Metal Oxide ReRAM is a class of non-volatile memory technologies where the switching between memory states is enabled by the reversible breakdown of the oxide by means of the creation and dissolution of a percolation path (filament). The main advantages of the technology lie in the scalability of the memory cell –mainly owed to the sub 10nm dimension of the filament, its low power consumption (< 300 pJ/ switch) and material compatibility to advanced CMOS. Nevertheless, there are two major roadblocks that have prevented so far the implementation of ReRAM in large arrays: first, the requirement for an initial breakdown happening voltages significantly higher than the operating voltage range and second, the intrinsic and extrinsic variability components arising from material interaction to its environment as well as the fundamental stochastic nature of percolative conduction. This work, is focused on HfO2 based ReRAM technology. In the first part, we investigate different dopants to engineer the conductive properties of HfO2 by combining a first-principles approach and in-depth material characterization techniques. In the second part, the proposed HfSiOx alloy is integrated in the BEOL of a 130nm process and the impact of the integration of the switching zone in forming, switching, error rate evolution and data retention is investigated. In the last part, a HfO2 based integration in the early MOL of an advanced FDSOI 300mm CMOS process is demonstrated investigating standard HfO2 ReRAM performances and limitations
16
Lieven, Jens. "Adel, Herrschaft und Memoria Studien zur Erinnerungskultur der Grafen von Kleve und Geldern im Hochmittelalter (1020 bis 1250)." Bielefeld Verl. für Regionalgeschichte, 2006. http://d-nb.info/988791099/04.
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Erll, Astrid. "Prämediation - Remediation : Repräsentationen des indischen Aufstands in imperialen und post-kolonialen Medienkulturen (von 1857 bis zur Gegenwart)." Trier WVT Wiss. Verl. Trier, 2007. http://www.wvttrier.de/top/Beschreibungen/ID513.html.
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Suntrup-Andresen, Elisabeth. "Hacer memoria. Der Bürgerkrieg in der Literatur der Nachgeborenen : Typologie und Analyse spanischer Gegenwartsromane von den 1980er Jahren bis heute /." München : M-Press, 2008. http://deposit.d-nb.de/cgi-bin/dokserv?id=3069950&prov=M&dokv̲ar=1&doke̲xt=htm.
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Suntrup-Andresen, Elisabeth. "Hacer memoria. Der Bürgerkrieg in der Literatur der Nachgeborenen Typologie und Analyse spanischer Gegenwartsromane von den 1980er Jahren bis heute." München M-Press Meidenbauer, 2007. http://d-nb.info/987537555/04.
20
Chinone, Noriko [Verfasser], and Wolfgang [Akademischer Betreuer] Augustyn. "Memoria und Kunst : Kunststiftungen der Antoniter von 1443 bis 1516 in der Dauphiné, im Piemont und im Elsass / Noriko Chinone ; Betreuer: Wolfgang Augustyn." München : Universitätsbibliothek der Ludwig-Maximilians-Universität, 2018. http://d-nb.info/122878728X/34.
21
Allevato, Anthony James. "From Intuition to Evidence: A Data-Driven Approach to Transforming CS Education." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/28352.
Анотація:
Educators in many disciplines are too often forced to rely on intuition about how students learn and the effectiveness of teaching to guide changes and improvements to their curricula. In computer science, systems that perform automated collection and assessment of programming assignments are seeing increased adoption, and these systems generate a great deal of meaningful intermediate data and statistics during the grading process. Continuous collection of these data and long-term retention of collected data present educators with a new resource to assess both learning (how well students understand a topic or how they behave on assignments) and teaching (how effective a response, intervention, or assessment instrument was in evaluating knowledge or changing behavior), by basing their decisions on evidence rather than intuition. It is only possible to achieve these goals, however, if such data are easily accessible.
I present an infrastructure that has been added to one such automated grading system, Web-CAT, in order to facilitate routine data collection and access while requiring very little added effort by instructors. Using this infrastructure, I present three case studies that serve as representative examples of educational questions that can be explored thoroughly using pre-existing data from required student work. The first case study examines student time management habits and finds that students perform better when they start earlier but that offering extra credit for finishing earlier did not encourage them to do so. The second case study evaluates a tool used to improve student understanding of manual memory management and finds that students made fewer errors when using the tool. The third case study evaluates the reference tests used to grade student code on a selected assignment and confirms that the tests are a suitable instrument for assessing student ability. In each case study, I use a data-driven, evidence-based approach spanning multiple semesters and students, allowing me to answer each question in greater detail than was possible using previous methods and giving me significantly increased confidence in my conclusions.Ph. D.
22
Matthes, Patrick. "Magnetic and Magneto-Transport Properties of Hard Magnetic Thin Film Systems." Doctoral thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-192683.
Анотація:
The present thesis is about the investigation of ferromagnetic thin film systems with respect to exchange coupling, magnetization reversal behavior and effects appearing in magnetic heterostructures, namely the exchange bias and the giant magnetoresistance effect. For this purpose, DC magnetron sputtered thin films and multilayers with perpendicular magnetic anisotropy were prepared on single crystalline and rigid as well as flexible amorphous substrates. The first part concentrates on magnetic data storage applications based on the combination of the concept of bit patterned media and three dimensional magnetic memory, consisting of at least two exchange decoupled ferromagnetic storage layers. Here, [Co/Pt] multilayers, revealing different magnetic anisotropies, have been applied as storage layers and as spacer material Pt and Ru was employed. By the characterization of the magnetization reversal behavior the exchange coupling in dependence of the spacer layer thickness was studied. Furthermore, with regard to the concept of bit patterned media, the layers were also grown on self-assembled silica particles, leading to an exchange decoupled single-domain magnetic dot array, which was studied by magnetic force microscope imaging and angular dependent magneto-optic Kerr effect magnetometry to evaluate the reversal mechanism and its dependence on the array dimensions, mainly the diameter of the silica particles and layer thicknesses. To complete the study, micromagnetic simulations were performed to access smaller dimensions and to investigate the dependence of intralayer as well as interlayer coupling on the magnetization reversal of the dot array with multiple storage layers. The second part focuses on the investigation of the giant magnetoresistance effect in systems with perpendicular magnetic anisotropy, where L10 -chemically ordered FePt alloys and [Co/Pt] as well as [Co/Pd] multilayers were utilized. In case of FePt, where high temperatures during the deposition are necessary to induce the chemical ordering, diffusion and alloying of the spacer material often prevent a sufficient exchange decoupling of the ferromagnetic layers. However, with Ru as spacer material a giant magnetoresistance effect could be achieved. Large improvements of the magnetoresistive behavior of such trilayer structures are presented for [Co/Pt] and [Co/Pd] multilayers, which can be deposited at room temperature not limiting the choice of spacer as well as substrate material. Furthermore, in systems consisting of one ferromagnet with perpendicular magnetic anisotropy and one ferromagnet with in-plane magnetic easy axis, a linear and almost hysteresis-free field dependence of the electrical resistance was observed and the behavior for various thickness series has been intensively studied. Finally, the corrosion resistance in dependence of the capping layer material as well as the magnetoresistance of a strained flexible pseudo-spin-valve structure is presented. In addition, in chapter 2.5.2 an experimental study of an improved crystal growth of FePt at comparable low temperatures by molecular beam epitaxy and further promoted by a surfactant mediated growth using Sb is shown. Auger electron spectroscopy as well as Rutherford backscattering spectrometry were carried out to confirm the surface segregation of Sb and magnetic characterization revealed an increase of magnetic anisotropy in comparison to reference layers without SbDie vorliegende Dissertation beschäftigt sich mit der Untersuchung ferromagnetischer Dünnschichtsysteme im Hinblick auf die Austauchkopplung, das Ummagnetisierungsverhalten und Effekte wie z.B. den Exchange Bias Effekt oder den Riesenmagnetwiderstandseffekt (GMR), welche in derartigen Heterostrukturen auftreten können. Die Probenpräparation erfolgte mittels DC Magnetronsputtern, wobei auf einkristallinen aber auch flexiblen sowie starren amorphen Substraten abgeschieden wurde. Im ersten Teil der Arbeit werden Untersuchungen mit dem Hintergrund einer Anwendung als magnetischer Datenträger vorgestellt. Konkret werden hier die Konzepte Bit Patterned Media (BPM) und 3D Speicher miteinander kombiniert. Letzteres Konzept basiert auf der Verwendung wenigstens zweier austauschentkoppelter ferromagnetischer Schichten, für welche [Co/Pt] Multilagen mit unterschiedlicher magnetischer Anisotropie verwendet wurden. Als Zwischenschichtmaterial diente Pt und Ru. Durch die Charakterisierung des Ummagnetisierungsverhaltens wurde die Austauschkopplung in Abhängigkeit der Zwischenschichtdicke untersucht. Darüber hinaus wurden jene Schichtstapel zur Realisierung des BPM-Konzeptes auf selbstangeordnete SiO2 Partikel mit unterschiedlichen Durchmessern aufgebracht, durch welche sich lateral austauschentkoppelte, eindomänige magnetische Nanostrukturen erzeugen lassen. Zur Untersuchung des Ummagnetisierungsverhaltens und der jeweiligen Größenabhängigkeiten (maßgeblich Durchmesser und Schichtdicke) wurden diese mittels Magnetkraftmikroskopie sowie winkelabhängiger magnetooptischer Kerr Effekt Magnetometrie untersucht. Zur weiteren Vertiefung des Verständnisses noch kleinerer Strukturgrößen erfolgten mikromagnetische Simulationen, bei denen die magnetischen Wechselwirkungen lateral (benachbarte 3D Elemente) als auch vertikal (Wechselwirkungen ferromagnetischer Schichten innerhalb eines 3D Elementes) im Interesse standen, sowie deren Auswirkungen auf das Ummagnetisierungsverhalten des gesamten Feldes. Der Fokus des zweiten Teils liegt auf der Untersuchung des Riesenmagnetwiderstandseffektes in Systemen mit senkrechter Sensitivität. Dafür sind ferromagnetische Schichten mit senkrechter magnetischer Anisotropie nötig, wobei hier die chemisch geordnete L10-Phase der FePt Legierung und [Co/Pt] sowie [Co/Pd] Multilagen Anwendung fanden. Für eine chemische Ordnung der FePt Legierung sind hohe Temperaturen während der Schichtabscheidung notwendig, welche eine hinreichende Austauschentkopplung beider ferromagnetischer Schichten meist nicht gewährleisten. Grund dafür sind einsetzende Diffusionsprozesse als auch Legierungsbildungen mit dem Zwischenschichtmaterial. In der vorliegenden Arbeit konnte der GMR Effekt daher ausschließlich mit einer Ru Zwischenschicht in FePt basierten Trilagensystemen nachgewiesen und charakterisiert werden. Enorme Verbesserungen der magnetoresistiven Eigenschaften werden im Anschluss für [Co/Pt] und vor allem [Co/Pd] Multilagen vorgestellt. Diese Schichtsysteme mit senkrechter magnetischer Anisotropie können bei Raumtemperatur präpariert werden und stellen daher keine weiteren Anforderungen an das Zwischenschichtmaterial sowie die verwendeten Substrate. Hier wurden neben Systemen mit ausschließlich senkrechter magnetischer Anisotropie auch Systeme mit gekreuzten magnetischen Anisotropien intensiv untersucht, da diese durch einen linearen und weitgehend hysteresefreien R(H) Verlauf imHinblick auf Sensoranwendungen enorme Vorteile bieten. Letztendlich wurde die Korrosionsbeständigkeit in Abhängigkeit des Deckschichtmaterials als auch die mechanische Belastbarkeit von auf flexiblen Substraten abgeschiedenen GMR-Schichtstapeln untersucht. Zusätzlich wird in Kapitel 2.5.2 eine experimentelle Studie zum Surfactant-gesteuerten Wachstum der FePt Legierung mittels Molekularstrahlepitaxie vorgestellt. Als Surfactant dient Sb, wodurch die Kristallinität bei geringer Depositionstemperatur deutlich verbessert werden konnte. Die Oberflächensegregation von Sb wurde mittels Auger Elektronenspektroskopie und Rutherford Rückstreuspektrometrie verifiziert und die Charakterisierung magnetischer Eigenschaften belegt einen Anstieg der magnetischen Anisotropieenergie im Vergleich zu Referenzproben ohne Sb
23
Vargas, Paredero David Eduardo. "Transmit and Receive Signal Processing for MIMO Terrestrial Broadcast Systems." Doctoral thesis, Universitat Politècnica de València, 2016. http://hdl.handle.net/10251/66081.
Анотація:
[EN] Multiple-Input Multiple-Output (MIMO) technology in Digital Terrestrial Television (DTT) networks has the potential to increase the spectral efficiency and improve network coverage to cope with the competition of limited spectrum use (e.g., assignment of digital dividend and spectrum demands of mobile broadband), the appearance of new high data rate services (e.g., ultra-high definition TV - UHDTV), and the ubiquity of the content (e.g., fixed, portable, and mobile). It is widely recognised that MIMO can provide multiple benefits such as additional receive power due to array gain, higher resilience against signal outages due to spatial diversity, and higher data rates due to the spatial multiplexing gain of the MIMO channel. These benefits can be achieved without additional transmit power nor additional bandwidth, but normally come at the expense of a higher system complexity at the transmitter and receiver ends. The final system performance gains due to the use of MIMO directly depend on physical characteristics of the propagation environment such as spatial correlation, antenna orientation, and/or power imbalances experienced at the transmit aerials. Additionally, due to complexity constraints and finite-precision arithmetic at the receivers, it is crucial for the overall system performance to carefully design specific signal processing algorithms.
This dissertation focuses on transmit and received signal processing for DTT systems using MIMO-BICM (Bit-Interleaved Coded Modulation) without feedback channel to the transmitter from the receiver terminals. At the transmitter side, this thesis presents investigations on MIMO precoding in DTT systems to overcome system degradations due to different channel conditions. At the receiver side, the focus is given on design and evaluation of practical MIMO-BICM receivers based on quantized information and its impact in both the in-chip memory size and system performance. These investigations are carried within the standardization process of DVB-NGH (Digital Video Broadcasting - Next Generation Handheld) the handheld evolution of DVB-T2 (Terrestrial - Second Generation), and ATSC 3.0 (Advanced Television Systems Committee - Third Generation), which incorporate MIMO-BICM as key technology to overcome the Shannon limit of single antenna communications. Nonetheless, this dissertation employs a generic approach in the design, analysis and evaluations, hence, the results and ideas can be applied to other wireless broadcast communication systems using MIMO-BICM.[ES] La tecnología de múltiples entradas y múltiples salidas (MIMO) en redes de Televisión Digital Terrestre (TDT) tiene el potencial de incrementar la eficiencia espectral y mejorar la cobertura de red para afrontar las demandas de uso del escaso espectro electromagnético (e.g., designación del dividendo digital y la demanda de espectro por parte de las redes de comunicaciones móviles), la aparición de nuevos contenidos de alta tasa de datos (e.g., ultra-high definition TV - UHDTV) y la ubicuidad del contenido (e.g., fijo, portable y móvil). Es ampliamente reconocido que MIMO puede proporcionar múltiples beneficios como: potencia recibida adicional gracias a las ganancias de array, mayor robustez contra desvanecimientos de la señal gracias a la diversidad espacial y mayores tasas de transmisión gracias a la ganancia por multiplexado del canal MIMO. Estos beneficios se pueden conseguir sin incrementar la potencia transmitida ni el ancho de banda, pero normalmente se obtienen a expensas de una mayor complejidad del sistema tanto en el transmisor como en el receptor. Las ganancias de rendimiento finales debido al uso de MIMO dependen directamente de las características físicas del entorno de propagación como: la correlación entre los canales espaciales, la orientación de las antenas y/o los desbalances de potencia sufridos en las antenas transmisoras. Adicionalmente, debido a restricciones en la complejidad y aritmética de precisión finita en los receptores, es fundamental para el rendimiento global del sistema un diseño cuidadoso de algoritmos específicos de procesado de señal. Esta tesis doctoral se centra en el procesado de señal, tanto en el transmisor como en el receptor, para sistemas TDT que implementan MIMO-BICM (Bit-Interleaved Coded Modulation) sin canal de retorno hacia el transmisor desde los receptores. En el transmisor esta tesis presenta investigaciones en precoding MIMO en sistemas TDT para superar las degradaciones del sistema debidas a diferentes condiciones del canal. En el receptor se presta especial atención al diseño y evaluación de receptores prácticos MIMO-BICM basados en información cuantificada y a su impacto tanto en la memoria del chip como en el rendimiento del sistema. Estas investigaciones se llevan a cabo en el contexto de estandarización de DVB-NGH (Digital Video Broadcasting - Next Generation Handheld), la evolución portátil de DVB-T2 (Second Generation Terrestrial), y ATSC 3.0 (Advanced Television Systems Commitee - Third Generation) que incorporan MIMO-BICM como clave tecnológica para superar el límite de Shannon para comunicaciones con una única antena. No obstante, esta tesis doctoral emplea un método genérico tanto para el diseño, análisis y evaluación, por lo que los resultados e ideas pueden ser aplicados a otros sistemas de comunicación inalámbricos que empleen MIMO-BICM.
[CAT] La tecnologia de múltiples entrades i múltiples eixides (MIMO) en xarxes de Televisió Digital Terrestre (TDT) té el potencial d'incrementar l'eficiència espectral i millorar la cobertura de xarxa per a afrontar les demandes d'ús de l'escàs espectre electromagnètic (e.g., designació del dividend digital i la demanda d'espectre per part de les xarxes de comunicacions mòbils), l'aparició de nous continguts d'alta taxa de dades (e.g., ultra-high deffinition TV - UHDTV) i la ubiqüitat del contingut (e.g., fix, portàtil i mòbil). És àmpliament reconegut que MIMO pot proporcionar múltiples beneficis com: potència rebuda addicional gràcies als guanys de array, major robustesa contra esvaïments del senyal gràcies a la diversitat espacial i majors taxes de transmissió gràcies al guany per multiplexat del canal MIMO. Aquests beneficis es poden aconseguir sense incrementar la potència transmesa ni l'ample de banda, però normalment s'obtenen a costa d'una major complexitat del sistema tant en el transmissor com en el receptor. Els guanys de rendiment finals a causa de l'ús de MIMO depenen directament de les característiques físiques de l'entorn de propagació com: la correlació entre els canals espacials, l'orientació de les antenes, i/o els desequilibris de potència patits en les antenes transmissores. Addicionalment, a causa de restriccions en la complexitat i aritmètica de precisió finita en els receptors, és fonamental per al rendiment global del sistema un disseny acurat d'algorismes específics de processament de senyal. Aquesta tesi doctoral se centra en el processament de senyal tant en el transmissor com en el receptor per a sistemes TDT que implementen MIMO-BICM (Bit-Interleaved Coded Modulation) sense canal de tornada cap al transmissor des dels receptors. En el transmissor aquesta tesi presenta recerques en precoding MIMO en sistemes TDT per a superar les degradacions del sistema degudes a diferents condicions del canal. En el receptor es presta especial atenció al disseny i avaluació de receptors pràctics MIMO-BICM basats en informació quantificada i al seu impacte tant en la memòria del xip com en el rendiment del sistema. Aquestes recerques es duen a terme en el context d'estandardització de DVB-NGH (Digital Video Broadcasting - Next Generation Handheld), l'evolució portàtil de DVB-T2 (Second Generation Terrestrial), i ATSC 3.0 (Advanced Television Systems Commitee - Third Generation) que incorporen MIMO-BICM com a clau tecnològica per a superar el límit de Shannon per a comunicacions amb una única antena. No obstant açò, aquesta tesi doctoral empra un mètode genèric tant per al disseny, anàlisi i avaluació, per la qual cosa els resultats i idees poden ser aplicats a altres sistemes de comunicació sense fils que empren MIMO-BICM.
Vargas Paredero, DE. (2016). Transmit and Receive Signal Processing for MIMO Terrestrial Broadcast Systems [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/66081
TESIS
Premiado
24
Matthes, Patrick. "Magnetic and Magneto-Transport Properties of Hard Magnetic Thin Film Systems." Doctoral thesis, Universitätsverlag der Technischen Universität Chemnitz, 2015. https://monarch.qucosa.de/id/qucosa%3A20376.
Анотація:
The present thesis is about the investigation of ferromagnetic thin film systems with respect to exchange coupling, magnetization reversal behavior and effects appearing in magnetic heterostructures, namely the exchange bias and the giant magnetoresistance effect. For this purpose, DC magnetron sputtered thin films and multilayers with perpendicular magnetic anisotropy were prepared on single crystalline and rigid as well as flexible amorphous substrates.
The first part concentrates on magnetic data storage applications based on the combination of the concept of bit patterned media and three dimensional magnetic memory, consisting of at least two exchange decoupled ferromagnetic storage layers. Here, [Co/Pt] multilayers, revealing different magnetic anisotropies, have been applied as storage layers and as spacer material Pt and Ru was employed. By the characterization of the magnetization reversal behavior the exchange coupling in dependence of the spacer layer thickness was studied. Furthermore, with regard to the concept of bit patterned media, the layers were also grown on self-assembled silica particles, leading to an exchange decoupled single-domain magnetic dot array, which was studied by magnetic force microscope imaging and angular dependent magneto-optic Kerr effect magnetometry to evaluate the reversal mechanism and its dependence on the array dimensions, mainly the diameter of the silica particles and layer thicknesses. To complete the study, micromagnetic simulations were performed to access smaller dimensions and to investigate the dependence of intralayer as well as interlayer coupling on the magnetization reversal of the dot array with multiple storage layers.
The second part focuses on the investigation of the giant magnetoresistance effect in systems with perpendicular magnetic anisotropy, where L10 -chemically ordered FePt alloys and [Co/Pt] as well as [Co/Pd] multilayers were utilized. In case of FePt, where high temperatures during the deposition are necessary to induce the chemical ordering, diffusion and alloying of the spacer material often prevent a sufficient exchange decoupling of the ferromagnetic layers. However, with Ru as spacer material a giant magnetoresistance effect could be achieved. Large improvements of the magnetoresistive behavior of such trilayer structures are presented for [Co/Pt] and [Co/Pd] multilayers, which can be deposited at room temperature not limiting the choice of spacer as well as substrate material. Furthermore, in systems consisting of one ferromagnet with perpendicular magnetic anisotropy and one ferromagnet with in-plane magnetic easy axis, a linear and almost hysteresis-free field dependence of the electrical resistance was observed and the behavior for various thickness series has been intensively studied. Finally, the corrosion resistance in dependence of the capping layer material as well as the magnetoresistance of a strained flexible pseudo-spin-valve structure is presented.
In addition, in chapter 2.5.2 an experimental study of an improved crystal growth of FePt at comparable low temperatures by molecular beam epitaxy and further promoted by a surfactant mediated growth using Sb is shown. Auger electron spectroscopy as well as Rutherford backscattering spectrometry were carried out to confirm the surface segregation of Sb and magnetic characterization revealed an increase of magnetic anisotropy in comparison to reference layers without Sb.Die vorliegende Dissertation beschäftigt sich mit der Untersuchung ferromagnetischer Dünnschichtsysteme im Hinblick auf die Austauchkopplung, das Ummagnetisierungsverhalten und Effekte wie z.B. den Exchange Bias Effekt oder den Riesenmagnetwiderstandseffekt (GMR), welche in derartigen Heterostrukturen auftreten können. Die Probenpräparation erfolgte mittels DC Magnetronsputtern, wobei auf einkristallinen aber auch flexiblen sowie starren amorphen Substraten abgeschieden wurde. Im ersten Teil der Arbeit werden Untersuchungen mit dem Hintergrund einer Anwendung als magnetischer Datenträger vorgestellt. Konkret werden hier die Konzepte Bit Patterned Media (BPM) und 3D Speicher miteinander kombiniert. Letzteres Konzept basiert auf der Verwendung wenigstens zweier austauschentkoppelter ferromagnetischer Schichten, für welche [Co/Pt] Multilagen mit unterschiedlicher magnetischer Anisotropie verwendet wurden. Als Zwischenschichtmaterial diente Pt und Ru. Durch die Charakterisierung des Ummagnetisierungsverhaltens wurde die Austauschkopplung in Abhängigkeit der Zwischenschichtdicke untersucht. Darüber hinaus wurden jene Schichtstapel zur Realisierung des BPM-Konzeptes auf selbstangeordnete SiO2 Partikel mit unterschiedlichen Durchmessern aufgebracht, durch welche sich lateral austauschentkoppelte, eindomänige magnetische Nanostrukturen erzeugen lassen. Zur Untersuchung des Ummagnetisierungsverhaltens und der jeweiligen Größenabhängigkeiten (maßgeblich Durchmesser und Schichtdicke) wurden diese mittels Magnetkraftmikroskopie sowie winkelabhängiger magnetooptischer Kerr Effekt Magnetometrie untersucht. Zur weiteren Vertiefung des Verständnisses noch kleinerer Strukturgrößen erfolgten mikromagnetische Simulationen, bei denen die magnetischen Wechselwirkungen lateral (benachbarte 3D Elemente) als auch vertikal (Wechselwirkungen ferromagnetischer Schichten innerhalb eines 3D Elementes) im Interesse standen, sowie deren Auswirkungen auf das Ummagnetisierungsverhalten des gesamten Feldes. Der Fokus des zweiten Teils liegt auf der Untersuchung des Riesenmagnetwiderstandseffektes in Systemen mit senkrechter Sensitivität. Dafür sind ferromagnetische Schichten mit senkrechter magnetischer Anisotropie nötig, wobei hier die chemisch geordnete L10-Phase der FePt Legierung und [Co/Pt] sowie [Co/Pd] Multilagen Anwendung fanden. Für eine chemische Ordnung der FePt Legierung sind hohe Temperaturen während der Schichtabscheidung notwendig, welche eine hinreichende Austauschentkopplung beider ferromagnetischer Schichten meist nicht gewährleisten. Grund dafür sind einsetzende Diffusionsprozesse als auch Legierungsbildungen mit dem Zwischenschichtmaterial. In der vorliegenden Arbeit konnte der GMR Effekt daher ausschließlich mit einer Ru Zwischenschicht in FePt basierten Trilagensystemen nachgewiesen und charakterisiert werden. Enorme Verbesserungen der magnetoresistiven Eigenschaften werden im Anschluss für [Co/Pt] und vor allem [Co/Pd] Multilagen vorgestellt. Diese Schichtsysteme mit senkrechter magnetischer Anisotropie können bei Raumtemperatur präpariert werden und stellen daher keine weiteren Anforderungen an das Zwischenschichtmaterial sowie die verwendeten Substrate. Hier wurden neben Systemen mit ausschließlich senkrechter magnetischer Anisotropie auch Systeme mit gekreuzten magnetischen Anisotropien intensiv untersucht, da diese durch einen linearen und weitgehend hysteresefreien R(H) Verlauf imHinblick auf Sensoranwendungen enorme Vorteile bieten. Letztendlich wurde die Korrosionsbeständigkeit in Abhängigkeit des Deckschichtmaterials als auch die mechanische Belastbarkeit von auf flexiblen Substraten abgeschiedenen GMR-Schichtstapeln untersucht. Zusätzlich wird in Kapitel 2.5.2 eine experimentelle Studie zum Surfactant-gesteuerten Wachstum der FePt Legierung mittels Molekularstrahlepitaxie vorgestellt. Als Surfactant dient Sb, wodurch die Kristallinität bei geringer Depositionstemperatur deutlich verbessert werden konnte. Die Oberflächensegregation von Sb wurde mittels Auger Elektronenspektroskopie und Rutherford Rückstreuspektrometrie verifiziert und die Charakterisierung magnetischer Eigenschaften belegt einen Anstieg der magnetischen Anisotropieenergie im Vergleich zu Referenzproben ohne Sb.
25
Mo, Chin-tsung, and 牟慶聰. "A self-diagnostic BIST memory design." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/12306003479185957293.
Анотація:
碩士國立交通大學
電子研究所
81
In this thesis, a self-diagnostic BIST RAM structure for the embedded RAM which achieves the self-diagnostic capability with only a minimal overhead is proposed. The BIST structure degrades a little on the speed performance of the RAM in normal operation. Two sets of test patterns which can detect most of the models of failures are adopted to speed up the self-testing and diagnosis. With self-diagnosis capability, this BIST RAM design can be incorporated with the self-repaired redundant design to increase the yield of the embedded RAM.
26
Yeh, Chun-Wen, and 葉俊文. "Processor-Programmable Memory BIST Framework for System-on-Chip." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/57805191702038533797.
Анотація:
碩士國立清華大學
電機工程學系
89
Memory is now widely used in digital systems. The popular core-based System-on-Chip (SoC) environment always contains some kind and different size of memory cores. The testing for these embedded memory becomes more important and essential. In this thesis, we will present a processor-programmable memory built-in self-test (BIST) framework for SoC environment. We promise to build up a friendly and complete test framework to perform memory testing and verify our idea. In our SoC test environment, it includes one microprocessor, the programmable BIST circuit we proposed, self-defined bus, arbiter, I/O, and memory. The test framework can automatically execute most popular March test algorithms through brief description of March algorithm and register definition for our BIST circuit. It simulates March algorithm in a simple SoC environment after programming BIST circuit via on-chip microprocessor. Finally, it will show the test results and if any error occurs when testing, it can report the erroneous responses and faulty addresses, too. Compared with processor-based memory BIST schemes that use an assembly-language program to perform testing and comparison of the memory outputs, the test time of our proposed BIST circuit is greatly reduced. Compared with conventional dedicated BIST circuit, the area overhead can be reduced and flexibility is higher. The proposed framework can perform various March test algorithms and verify the functionality of our BIST circuit.
27
O'Donnell, William Hugh. "A programmable MBIST with address and NPSF pattern generators." Thesis, 2013. http://hdl.handle.net/2152/24050.
Анотація:
The movement to smart mobile connected devices which consolidate functions of traditionally separate devices is driving innovation in System-on-chips (SoCs). One of the innovations helping to meet the current needs of SoCs is the integration of larger memory with the processor, and with this, comes the challenge of testing all the memory cells. The programmable memory BIST offers a flexible approach to designers and testers because it allows the memory test algorithms to be updated when new memory fault models are discovered. But this flexibility comes as a trade-off to area as the BIST circuitry needs to be integrated next to the memory array. This report proposes enhancements to an existing design that will improve flexibility by enhancing the address generation schemes while simultaneously eliminating the need for an auxiliary memory in cases where a Type-1 NPSF background will be used. A comparison of the base design to the proposed design shows the address and data generation improvements can be achieved with only 1.8% increase in area with an 8KB memory.text
28
Tseng, Nan-Hsin, and 曾南欣. "Universal BIST for Heterogeneous Embedded Synchronous Memory cores in SOC." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/yed7t2.
Анотація:
碩士國立成功大學
電機工程學系碩博士班
90
Due to the drastic growing up and heterogeneity of embedded memory cores in SOCs, the memory testing issue has become a major problem in the SOC testing. For low cost and testability consideration, BIST is a widely accepted methodology for testing embedded memories within SOCs. In this thesis, we propose a universal BIST design for the heterogeneous embedded memory cores in an SOC. The memory cores considered include Sync-SRAM, SDRAM, DDR SDRAM and Sync-Flash. Because the memory cells can be tested in a regular address order, the March algorithms are popular to test the embedded memory cores of the SOC and stand-alone memories. In our design, we first propose a Universal Test Instruction Generator. We analyze the properties of March algorithms and use an efficient procedure to reduce the memory storage for these characteristics. The proposed approach integrates 42 existing march algorithms into an embedded test instruction generator. This generator is capable of executing any March algorithm with small area overhead. To deal with word-oriented memory cores, we also use a “background” signal to select different data backgrounds for memory cells. Besides, to test manifold memory cores in an SOC, different test command sequences are necessary. A mixed-type test vector generator and a command generator are proposed to generate the command sequences. According to this proposed design, the user can test heterogeneous memory cores in an SOC using a single BIST controller and hence can significantly reduce the BIST hardware overhead.
29
Ko, Yen-Chun, and 柯妍君. "3D IC Memory BIST Design and Test Scheduling under Power Constraints." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/71021599394150571984.
Анотація:
碩士中原大學
電子工程研究所
105
With the increasing number of embedded memory cores in modern electronic system designs, the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective approach for memory testing. However, memory BIST for three-dimensional integrated circuits (3D ICs) has not been well studied. Different from 2D SOCs, the testing of 3D ICs consists of both pre-bond testing and post-bond testing. Therefore, extra memory BIST controllers may be required for each layer to reduce the total test application time. In this thesis, we propose a two-stage approach: the first stage performs memory grouping under distance constraints and the second stage performs test scheduling under power constraints. Compared to the previous work, our approach can improve both BIST area cost and total test time simultaneously.
30
Lu, Wei Hao, and 呂偉豪. "A Leakage-Current Sensor Enhanced Memory BIST for Defect Level Reduction." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/z86357.
Анотація:
碩士國立清華大學
電機工程學系
105
Semiconductor memory is considered an essential component in almost all electronic systems. Increasing the yield and reliability of semiconductor memory becomes a more and more important issue. It is well known that in advanced process technologies, more and more defects in an IC cannot be modeled and tested by conventional logic-level faults or voltage measurements at the primary outputs. Delay (timing) testing and current measurement, e.g., are two important approaches, which help cover such defects that may otherwise escape conventional tests. Delay or at-speed test is relatively mature, but a complete test that covers all potential timing defects can be slow and impractical for large memories, so we address the issue using a current measurement circuit (current sensor). Memory built-in self-test (BIST) is popular and mature for embedded memories, especially for static functional faults. For timing related dynamic defects, however, complicated test algorithms and clock schemes may be required. Even if they can be executed at-speed, the process still can be too slow and impractical for large embedded memories. We try to address the issue by integrating a current sensor with the existing BIST design. We reuse the current sensor circuit developed by Prof. Ying-Chieh Ho of NDHU, who provides the current sensor circuit and layout. Based on that, we propose a leakage-current sensor enhanced memory BIST for reducing defect level of embedded RAM, where the original memory BIST was generated by BRAINS (BIST for RAM in seconds). The leakage-current sensor mirrors the leakage-current from the circuit under test, and then quantizes the result into a digital form that is to be evaluated by the BIST circuit. We use a commercial 65nm CMOS technology (with standard cell library) to implement the memory BIST design, and use a commercial SRAM compiler to generate an 8KB (2048x32 bits) single-port SRAM. As an experiment, we integrate the memory BIST, SRAM, and the leakage-current sensor into a single test chip, and finish the design at the physical level. Based on detailed post-layout simulation, we conclude that the leakage-current sensor enhanced memory BIST works as we expected. However, the extra loading of the current sensor to the SRAM results in a lower measurement current than expected, but this factor can be taken care of in the calibration process (to determine the reference current) before mass production test. The reference current will then be entered into the BIST module in the beginning of the test session for go/no-go comparison with the measured current. In summary, the proposed leakage-current sensor enhanced memory BIST can do the original functional test, and furthermore it can sense the leakage-current of the SRAM. The minimum value of the current detected by our design is 30 uA. The total area of our design is 905x905 um2.
31
Yeh, Chang-Han, and 葉昌翰. "Co-Optimization of Memory BIST Grouping and Test Scheduling under Power Constraints." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/76d799.
Анотація:
碩士中原大學
電子工程研究所
104
Built-in self-test (BIST) is a well-known design technique for the embedded memory verification and fixing problem. As the chip design becomes more complex, the test time also becomes longer, which directly affects the cost of the testing. In addition to the test time, the built-in self-test circuit area, built-in self-test controller and memory routing wire length should also be included in the cost considerations. In this thesis, we propose a mixed integer linear programming approach to optimize the total test time under power constraints by taking into account the number of built-in self-test controller as well as the distances between BIST controller and memories. Experimental results show that our proposed method can achieve the minimum total test time and improve test efficiency by reducing the costs.
32
Kim, Hyun Jin doctor of electrical and computer engineering. "BIST methodology for low-cost parametric timing measurement of high-speed source synchronous interfaces." 2012. http://hdl.handle.net/2152/19455.
Анотація:
With the scaling of technology nodes, the speed performance
of microprocessors has rapidly improved but the scaling of off-chip
input/output (I/O) bandwidth is limited by physical pin resources
and interconnect technologies. In order to reduce the performance
gaps, new interface techniques have emerged and the marketplace has
moved towards higher levels of integration with system on a chip
(SoC) implementations. The advent of new techniques, however, has
led to new challenges on the semiconductor and automated test
equipment (ATE) industries. The relatively slow growing ATE
technology comparing to I/O speeds especially intensifies
manufacturing test issues. Testing high speed I/O timing parameters
requires expensive high performance test equipment with high
accuracy and resolution. The requirements increase integrated
circuit (IC) manufacturing costs and thus test issues have become
critical.
This thesis focuses on on-chip test methods to improve test accuracy
and reduce test costs for high speed double data rate (DDR) memory
I/Os using source synchronous clocking. For testing the I/O timing
parameters, a phase interpolator based on-chip timing sampler using
a cycle-by-cycle control method was developed. This circuit
generates data and clock patterns and controls the time delay
between data and clock to detect the timing mismatch which indicates
timing degradations. The on-chip timing sampler was implemented as a
built-in self test (BIST) circuit for low-cost parametric timing
measurements. The BIST scheme was fabricated with a 0.18-um CMOS
process technology. Using the static and dynamic modes, measurement
results are obtained for the I/O timing parameters such as the setup
and hold times, input voltage-level variations tolerances, duty
distortion tolerances and data skews. Moreover, a delay mismatch
measurement method was developed to improve measurement accuracy
using a simple control circuit. This delay mismatch detector
measures timing mismatches between data and clock paths and then the
timing mismatches are converted to timing specifications. This
scheme is also implemented along with analog to digital converter
(ADC) to collect digital test results supporting low-cost
system-level tests. Thus, the low-frequency test results show that
our on-chip measurement techniques provide an attractive low-cost
solution and is effectively applied for testing high speed source
synchronous systems.text
33
Kuan-Wei, Wu. "Study on the 2nd Bit Effect of Scaled Two Bits Per Cell Storage SONOS Type Flash Memory." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0005-2607200616231300.
34
Wu, Kuan-Wei, and 吳冠緯. "Study on the 2nd Bit Effect of Scaled Two Bits Per Cell Storage SONOS Type Flash Memory." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/48001771590507069061.
Анотація:
碩士國立中興大學
電機工程學系所
94
This thesis focus on the discussions about 2nd bit effect of two bits per cell storage SONOS type flash memory. In our experimental designs, the primary topics for discussion are the channel length effect and BD (source/drain) implantation dosage effect. In this study, the two bits per cell storage SONOS cell is made of an n-channel MOSFET with an oxide-nitride-oxide gate structure. Unlike conventional SONOS cell, this cell has a relatively thicker bottom oxide to avoid charge direct tunneling and is operated with channel hot electron to program and band-to-band hot hole to erase, respectively. Thus, after the program operation, we use the charge profiling methodology to extract the electron distribution trapped in the nitride and take advantage of TCAD tools to simulate process conditions and analyze the electrical characteristics. Using these simulated results, we try to understand how the channel length and source/drain implantation dosage affect 2nd bit effect as shown in our experimental data. The degrading factors of 2nd bit effect are the short channel effect and different junction shapes inducing different potential distribution, respectively.
35
Seok, Geewhun. "Testability considerations for implementing an embedded memory subsystem." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4507.
Анотація:
There are a number of testability considerations for VLSI design,
but test coverage, test time, accuracy of test patterns and
correctness of design information for DFD (Design for debug) are
the most important ones in design with embedded memories. The goal
of DFT (Design-for-Test) is to achieve zero defects. When it comes
to the memory subsystem in SOCs (system on chips), many flavors of
memory BIST (built-in self test) are able to get high test
coverage in a memory, but often, no proper attention is given to
the memory interface logic (shadow logic). Functional testing and
BIST are the most prevalent tests for this logic, but functional
testing is impractical for complicated SOC designs. As a result,
industry has widely used at-speed scan testing to detect delay
induced defects. Compared with functional testing, scan-based
testing for delay faults reduces overall pattern generation
complexity and cost by enhancing both controllability and
observability of flip-flops. However, without proper modeling of
memory, Xs are generated from memories. Also, when the design has
chip compression logic, the number of ATPG patterns is increased
significantly due to Xs from memories. In this dissertation, a
register based testing method and X prevention logic are presented
to tackle these problems.
An important design stage for scan based testing with memory
subsystems is the step to create a gate level model and verify
with this model. The flow needs to provide a robust ATPG netlist
model. Most industry standard CAD tools used to analyze fault
coverage and generate test vectors require gate level models.
However, custom embedded memories are typically designed using a
transistor-level flow, there is a need for an abstraction step to
generate the gate models, which must be equivalent to the actual
design (transistor level). The contribution of the research is a
framework to verify that the gate level representation of custom
designs is equivalent to the transistor-level design.
Compared to basic stuck-at fault testing, the number of patterns
for at-speed testing is much larger than for basic stuck-at fault
testing. So reducing test and data volume are important. In this
desertion, a new scan reordering method is introduced to reduce
test data with an optimal routing solution. With in depth
understanding of embedded memories and flows developed during the
study of custom memory DFT, a custom embedded memory Bit Mapping
method using a symbolic simulator is presented in the last chapter
to achieve high yield for memories.text
36
Wu, Hsiang-Wei, and 吳祥維. "A Shift-Based Segment of BISR Architecture for Embedded Memory." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/10960962034354391657.
Анотація:
碩士逢甲大學
電子工程所
92
While system-on-chip (SoC) designs have the advantages of higher performance, lower power consumption, and smaller area when compared with system-on-board designs, test development is now identified as a major bottleneck. By using embedded memory unavoidably, and how to do efficient test and improve the yield of embedded memory will be the important subject for engineers who develop system on a chip. A novel shift-based built-in-self-repair (BISR) architecture is developed in this thesis. The entire process is completed by following steps: First, the embedded memory fault can be detected by built-in-self-test (BIST) approach, then by using built-in self-diagnostic (BISD) technique to diagnose embedded memory itself and finally, the embedded memory will repair the failure memory cells itself by using BISR architecture proposed in this thesis. Based on BIST and BISD of [1], a novel BISR approach, segmented shifting word line, is created. Simulation results show that the repair rate of our approach is much better than previous memory repair algorithms.
37
Shepherd, Simon J., and Jorge C. Mex-Pereira. "Cryptanalysis of a summation generator with 2 bits of memory." 2002. http://hdl.handle.net/10454/3744.
Анотація:
NoThe conventional summation generator (SG) has been broken in the past using a number of different methods. Recently, a modified SG was proposed by Lee and Moon to increase the resistance of such generators against these attacks. However, this paper shows that even the modified generator is still vulnerable to correlation attacks.
38
Chang, Yu-Cheng, and 張祐誠. "Improving QEMU Memory Access in 64-bit Operating Systems." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21796022245773047898.
Анотація:
碩士國立中正大學
資訊工程研究所
101
QEMU is a fast and popular emulator for on embedded systems. Not only have ability for Application Simulations, but also support System Simulations. Unfortunately, 10 times slowdown was observed in System Simulation speed tests, as Simulation being focused on correctness. Nowadays, embedded systems step forward to multi-core application, while CPU frequencies get higher, speeding up the emulator and emulating differentiate instruction with more reasonable time is a noticeable issue. This paper described a method to improve Soft-MMU and Soft-TLB. This paper is targeted on x86-64 bit platform, and emulating arm-32 bit platform system. These two configurations are the most widely used when developing Android applications.
39
Kolditz, Till. "Resiliency Mechanisms for In-Memory Column Stores." 2018. https://tud.qucosa.de/id/qucosa%3A33197.
Анотація:
The key objective of database systems is to reliably manage data, while high query throughput and low query latency are core requirements. To date, database research activities mostly concentrated on the second part. However, due to the constant shrinking of transistor feature sizes, integrated circuits become more and more unreliable and transient hardware errors in the form of multi-bit flips become more and more prominent. In a more recent study (2013), in a large high-performance cluster with around 8500 nodes, a failure rate of 40 FIT per DRAM device was measured. For their system, this means that every 10 hours there occurs a single- or multi-bit flip, which is unacceptably high for enterprise and HPC scenarios. Causes can be cosmic rays, heat, or electrical crosstalk, with the latter being exploited actively through the RowHammer attack. It was shown that memory cells are more prone to bit flips than logic gates and several surveys found multi-bit flip events in main memory modules of today's data centers. Due to the shift towards in-memory data management systems, where all business related data and query intermediate results are kept solely in fast main memory, such systems are in great danger to deliver corrupt results to their users. Hardware techniques can not be scaled to compensate the exponentially increasing error rates. In other domains, there is an increasing interest in software-based solutions to this problem, but these proposed methods come along with huge runtime and/or storage overheads. These are unacceptable for in-memory data management systems.
In this thesis, we investigate how to integrate bit flip detection mechanisms into in-memory data management systems. To achieve this goal, we first build an understanding of bit flip detection techniques and select two error codes, AN codes and XOR checksums, suitable to the requirements of in-memory data management systems. The most important requirement is effectiveness of the codes to detect bit flips. We meet this goal through AN codes, which exhibit better and adaptable error detection capabilities than those found in today's hardware. The second most important goal is efficiency in terms of coding latency. We meet this by introducing a fundamental performance improvements to AN codes, and by vectorizing both chosen codes' operations. We integrate bit flip detection mechanisms into the lowest storage layer and the query processing layer in such a way that the remaining data management system and the user can stay oblivious of any error detection. This includes both base columns and pointer-heavy index structures such as the ubiquitous B-Tree. Additionally, our approach allows adaptable, on-the-fly bit flip detection during query processing, with only very little impact on query latency. AN coding allows to recode intermediate results with virtually no performance penalty. We support our claims by providing exhaustive runtime and throughput measurements throughout the whole thesis and with an end-to-end evaluation using the Star Schema Benchmark. To the best of our knowledge, we are the first to present such holistic and fast bit flip detection in a large software infrastructure such as in-memory data management systems. Finally, most of the source code fragments used to obtain the results in this thesis are open source and freely available.:1 INTRODUCTION
1.1 Contributions of this Thesis
1.2 Outline
2 PROBLEM DESCRIPTION AND RELATED WORK
2.1 Reliable Data Management on Reliable Hardware
2.2 The Shift Towards Unreliable Hardware
2.3 Hardware-Based Mitigation of Bit Flips
2.4 Data Management System Requirements
2.5 Software-Based Techniques For Handling Bit Flips
2.5.1 Operating System-Level Techniques
2.5.2 Compiler-Level Techniques
2.5.3 Application-Level Techniques
2.6 Summary and Conclusions
3 ANALYSIS OF CODING TECHNIQUES
3.1 Selection of Error Codes
3.1.1 Hamming Coding
3.1.2 XOR Checksums
3.1.3 AN Coding
3.1.4 Summary and Conclusions
3.2 Probabilities of Silent Data Corruption
3.2.1 Probabilities of Hamming Codes
3.2.2 Probabilities of XOR Checksums
3.2.3 Probabilities of AN Codes
3.2.4 Concrete Error Models
3.2.5 Summary and Conclusions
3.3 Throughput Considerations
3.3.1 Test Systems Descriptions
3.3.2 Vectorizing Hamming Coding
3.3.3 Vectorizing XOR Checksums
3.3.4 Vectorizing AN Coding
3.3.5 Summary and Conclusions
3.4 Comparison of Error Codes
3.4.1 Effectiveness
3.4.2 Efficiency
3.4.3 Runtime Adaptability
3.5 Performance Optimizations for AN Coding
3.5.1 The Modular Multiplicative Inverse
3.5.2 Faster Softening
3.5.3 Faster Error Detection
3.5.4 Comparison to Original AN Coding
3.5.5 The Multiplicative Inverse Anomaly
3.6 Summary
4 BIT FLIP DETECTING STORAGE
4.1 Column Store Architecture
4.1.1 Logical Data Types
4.1.2 Storage Model
4.1.3 Data Representation
4.1.4 Data Layout
4.1.5 Tree Index Structures
4.1.6 Summary
4.2 Hardened Data Storage
4.2.1 Hardened Physical Data Types
4.2.2 Hardened Lightweight Compression
4.2.3 Hardened Data Layout
4.2.4 UDI Operations
4.2.5 Summary and Conclusions
4.3 Hardened Tree Index Structures
4.3.1 B-Tree Verification Techniques
4.3.2 Justification For Further Techniques
4.3.3 The Error Detecting B-Tree
4.4 Summary
5 BIT FLIP DETECTING QUERY PROCESSING
5.1 Column Store Query Processing
5.2 Bit Flip Detection Opportunities
5.2.1 Early Onetime Detection
5.2.2 Late Onetime Detection
5.2.3 Continuous Detection
5.2.4 Miscellaneous Processing Aspects
5.2.5 Summary and Conclusions
5.3 Hardened Intermediate Results
5.3.1 Materialization of Hardened Intermediates
5.3.2 Hardened Bitmaps
5.4 Summary
6 END-TO-END EVALUATION
6.1 Prototype Implementation
6.1.1 AHEAD Architecture
6.1.2 Diversity of Physical Operators
6.1.3 One Concrete Operator Realization
6.1.4 Summary and Conclusions
6.2 Performance of Individual Operators
6.2.1 Selection on One Predicate
6.2.2 Selection on Two Predicates
6.2.3 Join Operators
6.2.4 Grouping and Aggregation
6.2.5 Delta Operator
6.2.6 Summary and Conclusions
6.3 Star Schema Benchmark Queries
6.3.1 Query Runtimes
6.3.2 Improvements Through Vectorization
6.3.3 Storage Overhead
6.3.4 Summary and Conclusions
6.4 Error Detecting B-Tree
6.4.1 Single Key Lookup
6.4.2 Key Value-Pair Insertion
6.5 Summary
7 SUMMARY AND CONCLUSIONS
7.1 Future Work
A APPENDIX
A.1 List of Golden As
A.2 More on Hamming Coding
A.2.1 Code examples
A.2.2 Vectorization
BIBLIOGRAPHY
LIST OF FIGURES
LIST OF TABLES
LIST OF LISTINGS
LIST OF ACRONYMS
LIST OF SYMBOLS
LIST OF DEFINITIONS
40
Gupta, Vasudha. "Variability-Aware Design of Static Random Access Memory Bit-Cell." Thesis, 2008. http://hdl.handle.net/10012/3812.
Анотація:
The increasing integration of functional blocks in today's integrated circuit designs necessitates a large embedded memory for data manipulation and storage. The most often used embedded memory is the Static Random Access Memory (SRAM), with a six transistor memory bit-cell. Currently, memories occupy more than 50% of the chip area and this percentage is only expected to increase in future. Therefore, for the silicon vendors, it is critical that the memory units yield well, to enable an overall high yield of the chip. The increasing memory density is accompanied by aggressive scaling of the transistor dimensions in the SRAM. Together, these two developments make SRAMs increasingly susceptible to process-parameter variations. As a result, in the current nanometer regime, statistical methods for the design of the SRAM array are pivotal to achieve satisfactory levels of silicon predictability.
In this work, a method for the statistical design of the SRAM bit-cell is proposed. Not only does it provide a high yield, but also meets the specifications for the design constraints of stability, successful write, performance, leakage and area. The method consists of an optimization framework, which derives the optimal design parameters; i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in the transistor's geometry and intrinsic threshold voltage fluctuations. The method is employed to obtain optimal designs in the 65nm, 45nm and 32nm technologies for different set of specifications. The optimality of the resultant designs is verified. The resultant optimal bit-cell designs in the 65nm, 45nm and 32nm technologies are analyzed to study the SRAM area and yield trade-offs associated with technology scaling. In order to achieve 50% scaling of the bit-cell area, at every technology node, two ways are proposed. The resultant designs are further investigated to understand, which mode of failure in the bit-cell becomes more dominant with technology scaling. In addition, the impact of voltage scaling on the bit-cell designs is also studied.
41
Lee, Kung-Hong, and 李昆鴻. "A Novel 2-Bit Per Cell Trench-Gate Flash Memory." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/89296609749500161313.
Анотація:
碩士國立清華大學
電子工程研究所
89
A 2-bit per cell flash memory based on a novel trenched gate structure is proposed. Its advantages include high density, large read current, easy fabrication steps, and avoiding complicated peripheral circuit. Using 2D and 3D device simulation tools, the effects of cell structure, and operation conditions on memory performance are discussed. The feasibility of this novel cell is demonstrated through simulated results of proposed fabrication steps. This work has shown that the novel 2-bit trenched gate flash structure is suitable for future giga-bit flash memory application.
42
Lee, He-lin, and 李和臨. "A Nonvolatile Two-Bits SONOS Memory with Vertical Oxide-Nitride-Oxide Stack." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/upayuw.
Анотація:
碩士國立中山大學
電機工程學系研究所
95
Flash memory is one sort of non-volatile memory, focus on the dates holding and capacity. Conventional non-volatile memory applies poly-crystalline for floating gate material, because the poly-crystalline (like poly-silicon) itself is the semiconductor material, will cause leakage problem, recently, Oxide-nitride-oxide multi-layer structure is under development for the place of conventional floating gate. Because it is the insulator material, can suppress leakage current, and it contains a deeper trapping energy level, and has a partial trapped carriers phenomenon to give a multi-bits memory solution. My effort is to propose a pair of ONO three layers stack, which is located close to the beneath of D/S region and a column like. Such structure can overcome miniaturization limitation of channel length, and a somewhat depth oxide can promise good isolation and separation between the trapping layer and other area, and a reliable distance of the two trapped unit can prevent interference issue. My proposal can suppose a higher devices density and a feasible and flexible solution to develop memory devices, a cost down to be more competitive, certainly bring much favor for the future improvement.
43
Chang, Yu-Che, and 張又哲. "Study of a Novel Vertical Non-volatile Multi-Bit SONOS Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/28098558437662952220.
Анотація:
碩士國立中山大學
電機工程學系研究所
99
In this thesis, a simple vertical embedded gate (VEG) MOSFET process is proposed and demonstrated by using simulation tools of ISE TCAD and Silvaco TCAD. In fundamental electrical characteristics, we employed junctionless technology and two extra sidewall spacer gates to fabricate the Junctionless Pseudo Tri-Gate Vertical (JPTGV) MOS. According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60 mV/dec and Ion/Ioff ~ 1010 are achieved at short gate length (Lg) 8 nm. In additional, our proposed VEG structure can also be applied for non-volatile memory. Using VEG structure to fabricate the SONOS devices have some features, it not only has three source/drain (S/D) terminals and two channels which can be operated independently, but also has two silicon nitride trap layers to provide the possible operation of multi-bit. We can apply different voltage in these three S/D terminals to achieve two bits or even four bits operation, thus the device has multi-bit characteristic is realized in this thesis.
44
Huang, Yi-Ren, and 黃奕仁. "Low-Frequency Noise in Two-Bit Poly-Si TANOS Flash Memory." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/xuaqw8.
Анотація:
碩士國立臺北科技大學
電腦與通訊研究所
102
In recent years, Poly-Si flash memory is extensively utilized in various portable electronic products. Poly-Si flash memory can be applied to system-on-panel (SOP) and 3D circuit applications because of its characteristics of low cost and low power consumption. In this thesis, the NVM utilizes a two-bit TaN-SiO2-Si3N4-SiO2-Si (TANOS)-type thin-film transistor (TFT), which has shown NVM characteristics and ultrahigh storage density. In poly-Si TANOS flash memory devices with a long channel, 2-bit operation is difficult to achieved by channel hot electron injection (CHEI) programing and band-to-band tunneling-induced hot-hole injection (BTBT-HHI) erasing owing to the grain boundaries. Accordingly, modulated Fowler-Nordheim (MFN) tunneling, which requires no charge acceleration, was performed in poly-Si TANOS flash memory for spatial programming and erasing. In this thesis, we would like to study the LFN in dual-gate (DG) TANOS with multiple nanowire (multi-NW) channel structure under modulate Fowler–Nordheim tunneling program/erase (P/E) operation. In addition, grain boundary trap density (QT) were examined to assist in the analysis of LFN for poly-Si TANOS NVM. In conclusion, through this thesis, we would like to provide DG TANOS-TFT design with strong reference to optimize memory by reducing the impact of LFN, and thus achieve the idealization of SOP.
45
Chang, Hung-Yu, and 張宏宇. "The Method of Reducing Flash Memory Bit-Line Leakage under 0.13um Process." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/30986203673714503818.
Анотація:
碩士國立交通大學
電機學院碩士在職專班電子與光電組
99
Flash memory which is the most popular non-volatile memory has a lot of advantages --- high density, fast read-write, long time data-retention and multi-times erase. Because of low-cost and easy use, Flash memory becomes the dominate semiconductor product. It can be used in many electric products. People use low-density parts to keep firmware program, middle parts in network equipment and cellular phone, high-density parts in digital camera and solid-state disc, etc. That’s why Research and Development of flash memory have become very important. Following with the progress of semiconductor industry, flash cell sensing current reduce from 100uA to about 30uA in 0.13um process. In the near future, lower sensing current can be expected. It means that any unexpected leakage current may cause sensing wrong. This thesis bring up some methods to improve the bit-line leakage issue. The traditional method to improve bit-line leakage is force high voltage on whole bit-line to use cell drain coupling to reduce cell leakage. Another new method is force high voltage on both word-line and bit-line to program single word or byte to reduce bit-line leakage. There are advantage and drawback in both method, we try to combine the two methods and realize it in a real 0.13um flash product.
46
Zhang, Yin Home, and 張穎弘. "Fabrication and Characterization of Multi-Bit Nonvolatile Memory Cell with Ge Nanocrystals." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/uhcpfe.
Анотація:
碩士國立中央大學
電機工程研究所
97
Current requirements of nonvolatile memory (NVM) for the scaling down device are high density cells, low-power consumption, high-speed operation and good reliability. The nonvolatile memories with nanocrystals are one of promising candidates to substitute for the conventional floating-gate memory, because the nanocrystals discrete charge storage nodes have effectively improved the data retention under endurance test for the scaling down device. In this thesis, the multi-bit nonvolatile memory cell with Ge nanocrystals as the charge trapping nodes has been fabricated and demonstrated. Firstly, the Ge nanocrystals gate stack with rather simple fabrication process has been studied to optimize process conditions and performance (e.g. large memory window and high density Ge nanocrystals with uniform distribution, etc.). Then, the optimum Ge nanocrystals gate stack was used to fabricate the multi-bit NVM cell. The application of three-dimensional cell structure led the cell to the advantage of multi-bit capacity. The fabrication processes of this NVM cell were compatible with current IC manufacturing process. The multi-bit NVM cell studied commercialization in the feature.
47
Kuo, Hsu-Hang, and 郭旭航. "Study on the Single-Grain-Boundary Multi-Bits TFT-SONOS Memory with 3D structures." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/21209264034116826825.
Анотація:
碩士國立交通大學
電子研究所
98
Low-temperature polycrystalling silicon (LTPS) thin film transistors (TFTs) have been widely used as the switching elements in active matrix displays due to their high field-effect mobility. In addition to high performance of operating elements as well as memory elements in the system on panel (SOP), TFT-SONOS memory is worthy to be investigated for the three dimensional applications owing to their features of being easily stacked. With the device dimension scaled down, the two-bits margin would be decreased due to the second bit effect increasing. Therefore, it was difficult to use the two bits mechanism (channel hot electron injection) with the symmetric SONOS structures; in the meantime, the 4 bits/cell target would hardly to achieve. In this thesis, we introduced the so-called elevated channel method to control the grain growth and the location of grain boundary, which could avoid many drawbacks of the conventional excimer laser crystallization, such as random grain boundaries, narrow process window, and etc. And there was a protrusion at the grain boundary with electric field enhanced effect. Consequently, we want to use the elevated channel method with excimer laser crystallization, and combine with an offset top gate mask design to fabricate asymmetric TFT-SONOS devices to increase the two-bits margin of SONOS memory. Furthermore, for the higher memory density demand in the future, we fabricated our device with 3D structures by using the layer by layer stacking technology to increase the memory capacity per unit area. In the first part, single grain boundary (SGB) bottom gate (BG), top gate (TG) and double gate (DG) TFT SONOS memory fabricated by excimer laser crystallization were investigated. As the excimer laser energy was 500 mJ/cm2 and the channel length was 1 um. The field-effect mobility and subthreshold swing of TFT-SONOS devices with bottom gate structure are 271 cm2/V-s and 0.481 V/decade, respectively. The field-effect mobility and subthreshold swing of TFT-SONOS devices with top gate structure are 320 cm2/V-s and 0.438 V/decade, respectively. In addition, to improve the gate controlling ability, we employ the double gate structure. The field-effect mobility and subthreshold swing of TFT-SONOS devices with Double gate structure are 455 cm2/V-s and 0.386 V/decade. In the second part, second bit effect was investigated by using both reverse read the SONOS with forward programming and reverse programming, respectively. The devices having single grain boundary with symmetric location under bottom gate, top gate and double gate structures fabricated by excimer laser crystallization studies with two-bits margin of 0.52 V, 0.22 V, and 0.46 V, respectively. Due to top gate has a protrusion in the channel middle, so the devices having single grain boundary with asymmetric location under offset top gate fabricated by excimer laser crystallization, the two-bits margin increased from 0.22 V to 0.69 V and 1.09 V with 0.1 um and 0.2 um top gate shift design, respectively. By using the large two-bits margin, the 2 bits (4 states) could be distiguished by once reverse read. And then to the endurance of SGB- bottom-gate, top-gate, double-gate, and offset-top-gate structures, the double gate structure has the worst endurance due to the more deep trapped electrons. In the last part, to achieve the high capacity demand the 3D structures with SGB-BG TFT-SONOS devices were implemented by layer by layer stacking technology. The two-bits margin of the top layer and the bottom layer devices were 0.61 V and 0.53 V, respectively. And the TFT-SONOS devices with 3D structure have good independence between top layer and bottom layer. Therefore, the 4 bits (16 states) were distinguished by twice read both top and bottom layer. To sum up, with the features such as simple process, high device performance, and large two-bits margin, the multi bits TFT-SONOS devices with 3D structures memory shows great potential in the 3D-IC applications.
48
Kuo, Jian-Hung, and 郭建鴻. "Investigation of the Mechanism and Reliability in a Two-Bit SONOS Flash Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00711881673803377573.
Анотація:
碩士國立交通大學
電子工程系所
96
For the design of advanced flash memories with better data retention characteristics, SONOS (Silicon Oxide Nitride Oxide Silicon) will become the main stream of nonvolatile memory products because of its simplicity in structure and scalable by comparing with conventional floating gate cells. The flash memory today, due to the vigorous development of the portable information system, the requirements for low voltage operation, low power consumption, and high speed are becoming increasingly important. By using the conventional programming scheme of channel hot electron injection, the interaction of the generated electron and hole pairs could cause the reliability issue for the tunnel oxide. This thesis will be focused on a novel programming method for SONOS applications, in which its physical mechanism and reliability issues will be demonstrated. For the scaling of SONOS memory, two-bit-per-cell operation has been one of the merits for SONOS devices. The unique feature of two-bit-per-cell storage is owing to the localized charge injection and the non-conducting property of charge storage material. First, we developed a low voltage operation scheme, FBEI (Forward Bias induced Electron Injection). Comparing to those reported schemes, this FBEI scheme has features of low voltage and sufficient large operation window. We found that the FBEI and CHEI have a similar characteristic to store charge locally verified from our experiment. Moreover, the stored charge for FBEI is closer to the drain than CHEI from the profiling of the stored charge density distribution. In addition, a better data retention property also made FBEI to become a new candidate for 2-bit operation. The characteristics of endurance and data retention test have also been compared.
49
Chen, Guan-Nan, and 陳冠男. "A Less Memory and Less Bit Requirement Architecture for the Discrete Wavelet Transform." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/16612136388731215671.
Анотація:
碩士中興大學
資訊科學系所
95
Discrete Wavelete Transform(DWT) is an efficient technology of analyzing signal and is the kernel technology of JPEG2000 as well. In this thesis, we propose a new methodology of rearranging Flipping-based DWT to get a low-cost and high-performance 2D DWT architecture. The proposed architecture consists of three main components which includes the column processor, the transposing buffers and the row processor. The column processor contains four multipliers, eight adders, sixteen registers and 4N temporal memory. The transposing buffer is used to replace original memory. Similarly, the row processor contains four multipliers, eight adders and twenty-four registers. There exist less register requirement to replace temporal memory because row processor applies row-wise scanning method. In this thesis, we also discuss the relation between data bit width of proposed architecture and PSNR of input picture. Here, we can maintain the qualified PSNR with less width of data bit while comparing with others.
50
Chen, Huan-Xun, and 陳煥勳. "The Research of Three-Dimensional Multi-bit Vertical Resistive-Switching Random Access Memory." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/29489252733244845020.
Анотація:
碩士國立中央大學
化學工程與材料工程學系
101
The essential structure of resistive-switching random access memory (RRAM) could be fabricated on capacitor-like metal/insulator/semiconductor (MIS) or metal/insulator/metal (MIM) stack. The simple structure is promising for development of high density nonvolatile memory (NVM). This research focused on increasing the storage density of RRAM by fabricating vertical structure which including double-layered structure to enhance the improvement of bit-per-area more efficiently. There are two main sections in this thesis. The HfO2-based double-layered vertical RRAM (VRRAM) will be demonstrated in the first section with different dimension and thickness of HfO2 switch layer. In the second section, we demonstrated an amorphous-silicon-based VRRAM with different thickness of a-Si. HfO2 and a-Si are both compatible with CMOS fabrication process and which are also possessed of superior step coverage to fulfill the vertical structure. Independent access between different bottom electrodes could be achieved in double-layered VRRAM which accomplished multi-bit operation. The characteristic of the two adjacent cells in the same vertical stack are identical due to excellent program/read disturbance immunity. The HfO2-based VRRAM could achieve lower set voltage (Vset) and better endurance with thinner HfO2 switch layer. The endurance and retention of amorphous-silicon-based VRRAM are both satisfactory with appropriate thickness of a-Si.