Готові списки джерел за темами / Digital-to-Analog Convertor (DAC)

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Добірка наукової літератури з теми "Digital-to-Analog Convertor (DAC)"

Автор: Grafiati

Опубліковано: 3 червня 2025

Оновлено: 31 липня 2025

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Статті в журналах з теми "Digital-to-Analog Convertor (DAC)"

An, Sheng-Biao, Li-Xin Zhao, Shi-Cong Yang, Tao An, and Rui-Xia Yang. "Design of Low Power and High Precision Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) Based on Piecewise Capacitance and Calibration Technique." Journal of Nanoelectronics and Optoelectronics 15, no. 4 (2020): 478–86. http://dx.doi.org/10.1166/jno.2020.2782.

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This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%. The test chip fabricated in 180 nm Complementary Metal Oxide Semiconductor (CMOS) occupied an active area of 0.12 mm 2 . At 10 MS/s, a signal-to-noise and distortion ratio (SNDR) of 57.70 dB and a spurious-free dynamic range (SFDR) of 55.63 dB are measured with 1.68 Vpp differential-mode input signal. The total power consumption is 6

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Albaba, Mouhamad Samer Ehsan, Ahmad Al-Abdo, and Yasser Khadra. "Calculation the precision of the conversion of bio-signals (heart sounds) in analog to digital and digital to analog conversion processes in ATmega 8 microcontroller processors using computer simulation." Association of Arab Universities Journal of Engineering Sciences 26, no. 4 (2019): 105–12. http://dx.doi.org/10.33261/jaaru.2019.26.4.013.

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Анотація:

The research aims to calculate the precision transfer from the analogue to digital convertor (ADC) and the digital to analogue convertor (DAC) of the ATmega microcontroller series that are widely used in various circuits and their application of weak signals such as boi-signals, especially heart sounds signals.We chose the ATmega8 microcontroller and performed the measurements and results on the first heart sound (S1) after enforcement the simulations of an electronic stethoscope using the famous program proteus8 for electronic systems. We performed the analogue to digital conversion (ADC) for

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Vidya, Sagar Potharaju. "FPGA IMPLEMENTATION OF DIRECT DIGITAL SYNTHESIZERUSING VHDL." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 140–50. https://doi.org/10.5281/zenodo.1067984.

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Signal generators are heavy and large in size and are limited to particular set of analog wave forms,creation of arbitrary wave forms are not possible. The available Digital signal generators nowadays are incapable of creating all type of waveforms and more ever they are not reconfigurable. In this paper I am proposing an efficient method called Direct Digital Synthesis (DDS) to realize all the hardware parts of signal generator called Direct Digital Synthesizer in FPGA using VHSIC Hardware Description Language (VHDL). DDS has many advantages over its analog counterpart and improved phase nois

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Hasannezhad, Mojtaba, Abumoslem Jannesari, and Mojtaba Lotfizad. "Design of a High-Frequency Very Low-Power Direct Digital Frequency Synthesizer." Journal of Circuits, Systems and Computers 25, no. 08 (2016): 1650085. http://dx.doi.org/10.1142/s0218126616500857.

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This paper presented a low-power Direct Digital Frequency Synthesizer (DDFS) using non-uniform sine-weighted digital-to-analog convertor (DAC). To avoid the need for a sharp filter to generate signals near and beyond the Nyquist frequency, parallel DACs, which cause to speed relaxation in a single DAC as well, and return-to-zero (RZ) technique were used. To reduce the area and power in parallel DACs, non-uniform sine-weighted DAC design method was proposed. This technique causes to reduce power consumption in DACs up to 48.47%, and nearly the same amount of reduction in the area. Meanwhile, by

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Nahar, Ali Kerem, Ansam Subhi Jaddar, Hussain K. Khleaf, and Mohmmed Jawad Mortada Mobarek. "Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance." International Journal of Advances in Applied Sciences 10, no. 1 (2021): 79. http://dx.doi.org/10.11591/ijaas.v10.i1.pp79-87.

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Анотація:

In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response

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Ali, Kerem Nahar, Subhi Jaddar Ansam, K. Khleaf Hussain, and Jawad Mortada Mobarek Mohmmed. "Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance." International Journal of Advances in Applied Sciences (IJAAS) 10, no. 1 (2021): 79–87. https://doi.org/10.11591/ijaas.v10.i1.pp79-87.

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Анотація:

In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounti

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Bekal, Anush, Shabi Tabassum, and Manish Goswami. "Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750077. http://dx.doi.org/10.1142/s0218126617500773.

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Анотація:

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of t

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Yao, Y., J. Zhang, Y. Liu, et al. "Development of a multifunctional real-time data processing system for interferometers on EAST." Journal of Instrumentation 18, no. 11 (2023): C11013. http://dx.doi.org/10.1088/1748-0221/18/11/c11013.

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Abstract In the latest campaign of EAST experiments, two new interferometers were installed, a dispersion interferometer (DI) based on a Carbon Dioxide laser and a solid source interferometer (SSI) based on microwave multiplier sources. To make them available for the Plasma Control System (PCS) system, each of them needs to be provided with a real-time processing system to extract the detector output signal and afterward obtain the electron density information through signal processing. To obtain interferometer data quickly and reliably, a unified hardware template was applied to both interfer

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Zhou, Peigen, Pinpin Yan, Jixin Chen, Zhe Chen, and Wei Hong. "A 77 GHz Power Amplifier with 19.1 dBm Peak Output Power in 130 nm SiGe Process." Micromachines 14, no. 12 (2023): 2238. http://dx.doi.org/10.3390/mi14122238.

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This article reports a two-stage differential structure power amplifier based on a 130 nm SiGe process operating at 77 GHz. By introducing a tunable capacitor for amplitude and phase balance at the center tap of the secondary coil of the traditional Marchand balun, the balun achieves amplitude imbalance less than 0.5 dB and phase imbalance less than 1 degree within the operating frequency range of 70–85 GHz, which enables the power amplifier to exhibit comparable output power over a wide operating frequency band. The power amplifier, based on a designed 3-bit digital analog convertor (DAC)-con

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Melikyan, V. Sh, V. D. Hovhannisyan, M. T. Grigoryan, A. A. Avetisyan, and H. T. Grigoryan. "Real Number Modeling Flow of Digital to Analog Converter." Proceedings of Universities. Electronics 26, no. 2 (2021): 144–53. http://dx.doi.org/10.24151/1561-5405-2021-26-2-144-153.

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Анотація:

This work introduces a flow of digital to analog (DAC) implementation in digital environment of SystemVerilog. Unlike the classical Verilog models, this digital to analog converter behavioral model is analog. Such type of model creation in general is called real number modeling. The DAC model is verified by the HSPICE and SystemVerilog Co-simulations which show its applicability in different register transfer level verification environments. The digital environment with real number modeled DAC runs around 8 times faster than the same environment with SPICE model. At the same time, the output s

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Дисертації з теми "Digital-to-Analog Convertor (DAC)"

Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.

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Анотація:

This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold l

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Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Анотація:

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture conside

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Perry, Jonathan. "Digital to Analog Converter Design using Single Electron Transistors." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/33871.

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Анотація:

CMOS Technology has advanced for decades under the rule of Moore's law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 10 to 15 years. In order to assure further progress in the field, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be trans- ported (tunnel) across a thin insulating surface. A conducting island sepa- rated by a

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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe.

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Majid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.

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Direct Digital Frequency Synthesis (DDFS) is a method of producing an analog waveform bygenerating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sourc

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Moody, Tyler J. "Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.

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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power effici

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Eklund, Henrik. "Linearization of Resistive Digital-to-Analog Converter for RF-Applications Using Compensator and Digital Predistortion." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177574.

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High-speed digital-to-analog converters are critical components in many radiofrequency (RF) applications. The resistive DAC (RDAC) architecture is suitable for high-speed implementation in extremely scaled digital circuit nodes. An RDAC core can be implemented as a resistance network and a digital block, consisting of inverters as drivers to the resistive network. One disadvantage of the architecture is the input code-dependent supply current. Combined with a non-zero supply network impedance, the code-dependent current will introduce non-linearity in the output voltage. One way to circumvent

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PELOSO, RICCARDO. "Signal processing techniques to improve interpolation and modulation in audio Digital to Analog Converters." Doctoral thesis, Politecnico di Torino, 2021. http://hdl.handle.net/11583/2898036.

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Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.

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A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400

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Книги з теми "Digital-to-Analog Convertor (DAC)"

Tang, Yongjian. Dynamic-Mismatch Mapping for Digitally-Assisted DACs. Springer New York, 2013.

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Lin, Haiqing. Multi-bit delta-sigma switched-capacitor DACs employing element-mismatch-shaping. 1998.

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Lin, Haiqing. Multi-bit delta-sigma switched-capacitor DACs employing element-mismatch-shaping. 1998.

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Hudson, William Forrest. Experimental verification of a mismatch-shaping DAC. 1997.

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Dynamicmismatch Mapping For Digitallyassisted Dacs. Springer, 2012.

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Engelbrecht, Linda M. A DAC and comparator for a 100MHz decision feedback equalization loop. 1996.

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Shui, Tao. Lowpass and bandpass current-mode delta-sigma DACs employing mismatch-shaping. 1998.

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Zhang, Bo. Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs. 1996.

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Zhang, Bo. Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs. 1996.

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Raspberry Pi - New Tech: Spotify, Gaming Console Utilizing RetroPie, WhatsApp to Send and Receive Messages, Software TensorFlow, Interface PCF8591 ADC/DAC Analog Digital Converter. Independently Published, 2019.

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Частини книг з теми "Digital-to-Analog Convertor (DAC)"

Schmidt, Christian. "Time Interleaving DAC (TI-DAC)." In Interleaving Concepts for Digital-to-Analog Converters. Springer Fachmedien Wiesbaden, 2019. http://dx.doi.org/10.1007/978-3-658-27264-7_3.

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Schmidt, Christian. "Analog Multiplexing DAC (AMUX-DAC)." In Interleaving Concepts for Digital-to-Analog Converters. Springer Fachmedien Wiesbaden, 2019. http://dx.doi.org/10.1007/978-3-658-27264-7_4.

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Schmidt, Christian. "Frequency Interleaving DAC (FI-DAC)." In Interleaving Concepts for Digital-to-Analog Converters. Springer Fachmedien Wiesbaden, 2019. http://dx.doi.org/10.1007/978-3-658-27264-7_5.

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Asadi, Farzin. "Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)." In Essentials of Arduino™ Boards Programming. Apress, 2023. http://dx.doi.org/10.1007/978-1-4842-9600-4_3.

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Radulov, Georgi, Patrick Quinn, Hans Hegt, and Arthur van Roermund. "Two Self-Calibrating DAC Designs." In Smart and Flexible Digital-to-Analog Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0347-6_16.

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Schmidt, Christian. "DAC: Fundamentals and Interleaving Concepts." In Interleaving Concepts for Digital-to-Analog Converters. Springer Fachmedien Wiesbaden, 2019. http://dx.doi.org/10.1007/978-3-658-27264-7_2.

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Tang, Yongjian, Hans Hegt, and Arthur van Roermund. "Digital-to-Analog Converters." In Dynamic-Mismatch Mapping for Digitally-Assisted DACs. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-1250-2_2.

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Radulov, Georgi, Patrick Quinn, Hans Hegt, and Arthur van Roermund. "Error Modeling for DAC Correction, a Broad View." In Smart and Flexible Digital-to-Analog Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0347-6_5.

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Radulov, Georgi, Patrick Quinn, Hans Hegt, and Arthur van Roermund. "A Functional-Segmentation DAC Design Using Harmonic Distortion Suppression Method." In Smart and Flexible Digital-to-Analog Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0347-6_17.

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Radulov, Georgi, Patrick Quinn, Hans Hegt, and Arthur van Roermund. "A 14 Bit Quad Core Flexible 180 nm DAC Platform." In Smart and Flexible Digital-to-Analog Converters. Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-0347-6_18.

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Тези доповідей конференцій з теми "Digital-to-Analog Convertor (DAC)"

Safanejadian, Arman, Leslie A. Rusch, Wei Shi, and Ming Zeng. "Enhanced Digital-to-Analog Converter Model Capturing Frequency Dependent ENoB." In Signal Processing in Photonic Communications. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/sppcom.2024.spth2g.2.

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Анотація:

We propose a digital-to-analog converter (DAC) model that accurately captures frequency-dependent effective number of bits (ENoB). Our model overcomes previous limitations (including aliasing and distortion) and reflects the DAC true frequency response.

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Pan, Z., Junyi Wang, and Yi Weng. "Investigation of Digital-to-Analog Converter (DAC) in Digital Nyquist-WDM Transmission Systems." In Optoelectronic Devices and Integration. OSA, 2015. http://dx.doi.org/10.1364/oedi.2015.ot2c.1.

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Vohra, Japesh, and Vinayak Hande. "Ultra low-energy active charge restoration DAC for SAR Analog-to-Digital Converter." In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018. http://dx.doi.org/10.1109/mwscas.2018.8623977.

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Vancura, Pavel, Miroslav Havranek, Tomas Benka, Zdenko Janoska, Jiri Jakovenko, and Vaclav Vrba. "A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation." In Topical Workshop on Electronics for Particle Physics. Sissa Medialab, 2019. http://dx.doi.org/10.22323/1.343.0094.

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Yoon, Sang-Hee, and Young-Ho Cho. "High-Accuracy Microflow Controllers Using Fluidic Digital-to-Analog Converters." In ASME 2003 International Mechanical Engineering Congress and Exposition. ASMEDC, 2003. http://dx.doi.org/10.1115/imece2003-41233.

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This paper presents 4-digit digital microflow controllers where fluidic digital-to-analog converters (DACs) achieve an improved linearity with finer flow-rate levels for a given number of digital valves. The fluidic DAC, composed of microchannels with binary-weighted flow resistors, controls flow-rate levels not based on the magnitude of flow resistances, but based on the ratio of the flow resistance. We deign the flow resistance of microchannel using a serial or a parallel connection of an identical fluidic resistor, thus making the controllable flow-rates insensitive to the micromachining er

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Chang-Ming Lai, Yi-Chung Chen, and Po-Chiun Huang. "Time-domain analog-to-digital converters with domino delay lines." In 2013 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2013. http://dx.doi.org/10.1109/vldi-dat.2013.6533841.

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I-Hsin Wang and Shen-Iuan Liu. "An integrating analog-to-digital data converter with variable resolution." In 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2010. http://dx.doi.org/10.1109/vdat.2010.5496721.

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Mahdavi, Sina, Rezvan Ebrahimi, Ainaz Daneshdoust, and Arefeh Ebrahimi. "A 12bit 800MS/s and 1.37mW Digital to Analog Converter (DAC) based on novel R-C technique." In 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI). IEEE, 2017. http://dx.doi.org/10.1109/icpcsi.2017.8392025.

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Runge, Marcel, та Friedel Gerfers. "A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters". У 2017 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2017. http://dx.doi.org/10.1109/iscas.2017.8050485.

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Chandrasekhar Bh, Maruthi, and Sudeb Dasgupta. "A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications." In 2009 10th International Symposium on Quality of Electronic Design (ISQED). IEEE, 2009. http://dx.doi.org/10.1109/isqed.2009.4810336.

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