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Готові списки джерел за темами / Digital-to-Analog Convertor (DAC) / Дисертації

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Дисертації з теми "Digital-to-Analog Convertor (DAC)"

Автор: Grafiati

Опубліковано: 3 червня 2025

Оновлено: 31 липня 2025

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1

Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.

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<p>This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.</p><p>The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold l

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2

Andersson, Ola. "Modeling and Implementation of Current-Steering Digital-to-Analog Converters." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5062.

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Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture conside

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3

Perry, Jonathan. "Digital to Analog Converter Design using Single Electron Transistors." Thesis, Virginia Tech, 2005. http://hdl.handle.net/10919/33871.

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CMOS Technology has advanced for decades under the rule of Moore's law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 10 to 15 years. In order to assure further progress in the field, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be trans- ported (tunnel) across a thin insulating surface. A conducting island sepa- rated by a

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4

Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe.

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5

Majid, Abdul, and Abdul Waheed Malik. "Design and Implementation of a Direct Digital Frequency Synthesizer using Sum of Weighted Bit Products." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-19986.

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<p>Direct Digital Frequency Synthesi<em>s </em>(DDFS) is a method of producing an analog waveform by</p><p>generating a time-varying signal in digital form, succeeded by digital-to-analog reconstruction.</p><p>At behavioral level the bit products with specified weights are used to generate the sine wave. In representation of a sine wave both positive and negative weights are generated. Since negative weights are not desired in design, the negative weights are transformed to positive weights. To reduce the number of current sources and control signals, bit product signals of those current sourc

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6

Moody, Tyler J. "Design of a 10-bit 1.2 GS/s Digital-to-Analog Converter in 90 nm CMOS." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440063577.

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7

Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power effici

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8

Eklund, Henrik. "Linearization of Resistive Digital-to-Analog Converter for RF-Applications Using Compensator and Digital Predistortion." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177574.

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High-speed digital-to-analog converters are critical components in many radiofrequency (RF) applications. The resistive DAC (RDAC) architecture is suitable for high-speed implementation in extremely scaled digital circuit nodes. An RDAC core can be implemented as a resistance network and a digital block, consisting of inverters as drivers to the resistive network. One disadvantage of the architecture is the input code-dependent supply current. Combined with a non-zero supply network impedance, the code-dependent current will introduce non-linearity in the output voltage. One way to circumvent

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9

PELOSO, RICCARDO. "Signal processing techniques to improve interpolation and modulation in audio Digital to Analog Converters." Doctoral thesis, Politecnico di Torino, 2021. http://hdl.handle.net/11583/2898036.

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10

Ebrahimi, Mehr Golnaz. "Design of a Rom-Less Direct Digital Frequency Synthesizer in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91680.

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A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400

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11

Ravikumar, Nivethithaa. "An Area Efficient 10-bit Time Mode Digital- to- Analog Converter with Current Settling Error Compensation Technique." University of Akron / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=akron1437756110.

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12

Balasubramanian, Sidharth. "STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.

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13

Patel, Vipul J. "A Poly-phased, Time-interleaved Radio Frequency Digital-to-analog Converter (Poly-TI-RF-DAC)." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1516146989134088.

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14

ABEDINKHAN, ESLAMI MAZYAR. "High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications." Doctoral thesis, Università degli studi di Pavia, 2022. http://hdl.handle.net/11571/1451124.

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Анотація:

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main g

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15

Puidokas, Vytenis. "Design and Research on Sigma-Delta Digital-to-Analog Converters for Audio Power Amplifiers." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2011. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20111220_133108-90590.

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The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis.<br>Disertacijoje nagrinėjami Sigma-Delta skaitmeniniai-analoginiai (skaičiaus-analogo, SA) keitikliai garso galios stiprintuvams. Pagrindinis tyrimų objekt

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16

Dornelas, Helga Uchoa. "Low power SAR analog-to-digital converter for internet-of-things RF receivers." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/186015.

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The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of high relevance in this area. The exponential increase of devices with wireless capabilities as well as the number of users, alongside with the decreasing costs for implementation of broadband communications, created a suitable environment for IoT applications. An IoT device is typically composed by a wireless transceiver, a battery and/or energy harvesting unit, a power management unit, sensors and conditioning unit, a microproc

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17

Warecki, Sylwester. "Behavioral simulation of digital to analog converters simulation of segmented current steering DAC with utilization of perfect sampling technique." Diss., The University of Arizona, 2003. http://hdl.handle.net/10150/280331.

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Rapid progress in telecommunication and introduction of wireless phones has revolutionized the way, in which the analog signal is treated. High Radio Frequency (RF) pollution caused by increased number of subscribers imposes new requirements on the quality of transmitted RF signal. These requirements are met by introduction of Digital Direct Synthesis (DDS) of Intermediate Frequency (IF). The DDS eliminates the analog IF mixing stage, which is responsible interference with modulated signal. The high accuracy of DDS modulation is possible only with high quality digital-to-analog conversion. The

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18

Azizi, Farouk. "Microfluidic Chemical Signal Generation." Cleveland, Ohio : Case Western Reserve University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=case1244664596.

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Thesis(Ph.D.)--Case Western Reserve University, 2009<br>Title from PDF (viewed on 2009-11-23) Department of Electrical Engineering Includes abstract Includes bibliographical references and appendices Available online via the OhioLINK ETD Center

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19

Kerzerho, Vincent. ""Analogue Network of Converters": a DfT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SoC." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2008. http://tel.archives-ouvertes.fr/tel-00364546.

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Une nouvelle méthode de test pour les convertisseurs ADC et DAC embarqués dans un système complexe a été développée en prenant en compte les nouvelles contraintes affectant le test. Ces contraintes, dues aux tendances de design de systèmes, sont un nombre réduit de point d'accès aux entrées/sorties des blocs analogiques du système et une augmentation galopante du nombre et des performances des convertisseurs intégrés. La méthode proposée consiste à connecter les convertisseurs DAC et ADC dans le domaine analogique pour n'avoir besoin que d'instruments de test numériques pour générer et capture

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20

Earick, Weston R. "DESIGN OF A HIGH-POWER, HIGH-EFFICIENCY, LOW-DISTORTION DIRECT FROM DIGITAL AMPLIFIER." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1155008919.

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21

Chhetri, Dhurv, and Venkata Narasimha Manyam. "A Continuous-Time ADC and DSP for Smart Dust." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80586.

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Recently, smart dust or wireless sensor networks are gaining more attention.These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operati

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22

Ciprys, Michal. "Systém pro sběr dat s Raspberry Pi." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400631.

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This work deals with the collection of data from analog sensors, their storage and display using the Raspberry Pi microcomputer. In more detail it deals with selecting the appropriate analog-to-digital converter, selecting the appropriate storage and database server, web server and application to display the measured data.

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23

Gaddam, Ravi Shankar. "A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation." University of Akron / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=akron1349294825.

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24

Thomsson, Pontus, and Aghamiri Cyrus Seyed. "Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-177548.

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Анотація:

Wireless communication technologies continue to evolve to meet the demand for increased data throughput. To achieve higher data throughput one approach is to increase the bandwidth. One problem related to very large bandwidths is the implementation of digital-to-analog converters with sampling rates roughly in the 5 to 20 GHz range. Traditionally, current-steering data converters have been the go-to choice but their linearity suffers at higher frequencies. An alternative to the current-steering digital-to-analog converter is the voltage-mode digital-to-analog converter, which is an attractive

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25

Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.

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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (S

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26

Kočík, Karol. "Modul osciloskopu s bezdrátovým přenosem dat." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221279.

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The aim of the thesis is the design and realization of the oscilloscope module with wireless data transfer. One part of the thesis is a short overview of the different types of AD converters. The main part is focused on the hardware configuration that allows modification of the wireless module of the oscilloscope, and the possibility of using in the industrial zone. The design takes into account reducing of consumption and EMC compatibility.

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27

Křížek, Miroslav. "Měřicí modul s A/D převodníkem se současným vzorkováním." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217840.

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In this work is designed programme unit for acquisition analog acoustic signlas from sensors. There is used accurate A/D converter ADS1287 by the company Texas Iinstrument with resolution of 24 bits to digitizing these signals. There is used 32-bit microprocessor AT91SAM7S64 by the company Atmel to control this A/D converter and sending digitized data to PC. This microprocessor has implemented USB interface. By force of developmental programme units whit microprocessor and A/D converter is produced programme for microprocessor in developmental setting IAR Embedded Workbench IDE 5.0 and simple

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28

Sattouf, Mousa. "Systém snímání dat a ovládání vodní elektrárny prostřednictvím internetové techniky." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-233685.

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Vodní energie se nyní stala nejlepším zdrojem elektrické energie na zemi. Vyrábí se pomocí energie poskytované pohybem nebo pádem vody. Historie dokazuje, že náklady na tuto elektrickou energii zůstávají konstantní v průběhu celého roku. Vzhledem k mnoha výhodám, většina zemí nyní využívá vodní energie jako hlavní zdroj pro výrobu elektrické energie.Nejdůležitější výhodou je, že vodní energie je zelená energie, což znamená, že žádné vzdušné nebo vodní znečišťující látky nejsou vyráběny, také žádné skleníkové plyny jako oxid uhličitý nejsou vyráběny, což činí tento zdroj energie šetrný k životn

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29

Wang, Xuesheng. "A fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs." Thesis, 2003. http://hdl.handle.net/1957/30720.

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This thesis proposes a novel fully digital technique for the estimation and correction of the DAC error in multi-bit delta sigma ADCs. The structure of the DAC error is indicated through a simple model for unit-element based DACs. The impact of the DAC error on the performance of ADC is then analyzed. Various techniques dealing with the DAC error are described and their drawbacks are pointed out. Based on the nature of the DAC error and the surrounding signals, a fully digital method to estimate the error from the ADC output and remove it is proposed. Simulation results are shown to support th

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30

Kuo, Ming-Hung. "Low-power high-linearity digital-to-analog converters." Thesis, 2012. http://hdl.handle.net/1957/28313.

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In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been proven to provide low power and high speed operation. Typically, capacitor matching is the best among all integrated circuit components but the mismatch among nominally equal value capacitors will introduce nonlinear distortion. By using dynamic element matchi

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31

Lin, Haiqing. "Multi-bit delta-sigma switched-capacitor DACs employing element-mismatch-shaping." Thesis, 1998. http://hdl.handle.net/1957/33995.

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Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters (ADCs and DACs). Most delta-sigma modulators in production today employ single-bit quantization because a 1-bit DAC is inherently linear, whereas a multi-bit DAC is not. Were it not for this drawback, the use of multi-bit quantization would improve a delta-sigma modulator's performance by increasing the modulator's resolution or increasing the modulators's bandwidth, while at the same time whitening the quantization noise and improving modulator stability.

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32

Χρίστου, Χρίστος, та Τιμόθεος Τιμοθέου. "Μελέτη και σχεδίαση γραμμικού digital to analog converter". Thesis, 2010. http://nemertes.lis.upatras.gr/jspui/handle/10889/3111.

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Анотація:

Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά ενός νέου μετατροπέα ψηφιακού σήματος σε αναλογικό (Digital to Analog Converter DAC). Η δομή του DAC βασίζεται στη γνωστή δομή του συμβατικού R2R Ladder και θα μπορούσε να θεωρηθεί σαν μία δισδιάστατη ανάπτυξη του Ladder. Αυτό σημαίνει ότι η νέα μορφή του DAC χρησιμοποιεί σαφώς περισσότερες αντιστάσεις από τον συμβατικό Ladder, όμως δίνεται η δυνατότητα της ρύθμισης του ρεύματος εξόδου του κάθε κλάδου. Αυτό έχει ως συνέπεια τη δραματική βελτίωση της γραμμικότητας του DAC. Επιπλέον στην Εργασία αυτή μελετήθηκαν με χρήση τη

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33

Hudson, William Forrest 1971. "Experimental verification of a mismatch-shaping DAC." Thesis, 1997. http://hdl.handle.net/1957/33999.

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Анотація:

Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This is a feature which multibit converters cannot realize due to the unavoidable phenomenon of element mismatch. Because of this problem, multibit converters have been largely unexplored, and the

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34

Kittredge, Jeffrey Prax. "High voltage, high resolution, digital-to-analog converter for driving deformable mirrors." Thesis, 2015. https://hdl.handle.net/2144/15209.

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Digital-to-analog converters with a range over 50 volts are required for driving micro-electro mechanical system deformable mirrors used in adaptive optics. An existing tested and deployed DM driver has 1024 channels and resolution of 15mV per Least Significant Bit. DMs used in the search for exoplanets require 3mV per LSB resolution. A technique is presented to employ a secondary high resolution and low voltage DAC which has for it's ground the output of the high voltage DAC. The entire system then has the range of high voltage DAC yet the resolution of the low voltage DAC. A method for provi

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35

Engelbrecht, Linda M. "A DAC and comparator for a 100MHz decision feedback equalization loop." Thesis, 1996. http://hdl.handle.net/1957/34236.

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Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at sp

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36

Chen, Hongbo. "Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522.

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Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling

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37

Shui, Tao 1969. "Lowpass and bandpass current-mode delta-sigma DACs employing mismatch-shaping." Thesis, 1998. http://hdl.handle.net/1957/33910.

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Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. A recent development in the realm of delta-sigma-based ADC and DAC systems is the use of multilevel (as opposed to binary) quantization. This development owes its existence to th

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38

Behera, Prachee Shree. "A MOSCAP pipeline pseudo passive DAC." Thesis, 2005. http://hdl.handle.net/1957/465.

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Graduation date: 2006<br>The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.

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39

Padyana, Aravind 1983. "Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters." Thesis, 2010. http://hdl.handle.net/1969.1/148453.

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Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC)

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40

Huang, Hsin, and 黃昕. "Low-Power DAC and Successive Approximation Analog to Digital Converter for Biomedical Application." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/81107529896968436330.

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碩士<br>長庚大學<br>電子工程學研究所<br>96<br>In this thesis we discuss the design of the analog to digital converter (ADC) for biomedical signal applications. ADC servers as an important role to translate biomedical signals from analog to digital for back-end microprocessor to analyze and process. The required ADC suitable for this purpose must have low power and high resolution , which has a good tradeoff between power,area and speed. Analog circuits are the key point of the ADC design. Among them, DAC is of much importance . In this thesis we use both fixed reference voltage, and Complementary Signal

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41

Zhang, Bo. "Delta-sigma modulators employing continuous-time circuits and mismatch-shaped DACs." Thesis, 1996. http://hdl.handle.net/1957/34675.

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Анотація:

Delta-sigma modulators are currently a very popular technique for making high-resolution analog-to-digital and digital-to-analog converters. These oversampled data converters have several advantages over conventional Nyquist-rate converters, including an insensitivity to many analog component imperfections, a simpler antialiasing filter and reduced accuracy requirements in the sample and hold. Though the initial uses of delta-sigma modulators were in the audio field, the development of bandpass modulators opened up the application range to radar systems, digital communication systems and instr

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42

Φωτόπουλος, Αρχιμήδης. "Μετατροπείς ψηφιακού σήματος σε αναλογικό". Thesis, 2011. http://nemertes.lis.upatras.gr/jspui/handle/10889/4601.

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Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά, ενός καινοτόμου Μετατροπέα Ψηφιακού Σήματος σε Αναλογικό (Digital to Analog Converter - DAC) που αναπτύχθηκε στο Εργαστήριο Ηλεκτρονικών Εφαρμογών του Πανεπιστημίου Πατρών. Η δομή του συγκεκριμένου DAC βασίζεται στην τοπολογία του γνωστού R-2R Ladder και παρ’ όλο που υλοποιείται με αντιστάσεις μικρής σχετικά ακρίβειας, επιτυγχάνει τελικά πολύ υψηλές επιδόσεις σε γραμμικότητα, κατανάλωση αλλά και επιφάνεια υλοποίησης. Στα πλαίσια της παρούσας Διπλωματικής Εργασίας χρησιμοποιήθηκε το ‘κατά κοινή ομολογία’ καλύτερο λογισμ

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Guerber, Jon. "Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters." Thesis, 2012. http://hdl.handle.net/1957/36019.

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In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binar

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Lin, Chun-Yao, and 林俊耀. "A 10Bit 1Msample/sec Successive Approximation Analog-to-Digital Converter with Wide-Swing Current-Mode R-2R DAC." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/50067408005489965689.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>91<br>Abstract A 10-bit 1MSample/sec successive approximation A/D converter is described in this thesis. First, by a comparator designed with high input impedance is used for the load of the modified wide-swing R-2R D/A converter. The modified wide-swing R-2R D/A converter possesses a high impedance load thus the op-amp is used in the D/A converter can be neglected. Therefore, the usable swing range and the convertible speed are improved and the power consumption is reduced. Secondary, the modified wide-swing R-2R D/A converter that contains modified switch-cir

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Ribeiro, Diogo Carlos Alcobia. "Instrumentation for measurement and characterization of mixed-signal devices." Doctoral thesis, 2018. http://hdl.handle.net/10773/24802.

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This PhD thesis work is about the development of radio frequency oriented measurement and characterization approaches for mixed-signal devices. Mixed-signal devices are an important building block for newer, higher data-rate and smart radios. However, intuitive and simple characterization approaches have not yet been developed. The most basic mixed-signal device is an ADC or a DAC. The ADCs and DACs will be considered in this work, as well as, more complex mixed-signal devices and even entire (integrated) radio front-ends. A microwave network analysis approach, in an S-parameters like fashion,

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Ferreira, Bruno Miguel Rosa. "A CCO-based Sigma-Delta ADC." Master's thesis, 2018. http://hdl.handle.net/10362/65512.

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Analog-to-digital converter (ADC) is one of the most important blocks in nowadays systems. Most of the data processing is done in the digital domain however, the physical world is analog. ADCs make the bridge between analog and digital domain. The constant and unstoppable evolution of the technology makes the dimensions of the transistors smaller and smaller, and the classical solutions of Sigma-Delta converters (ΣΔ) are becoming more challenging to design because they normally require high active gain blocks difficult to achieve in modern technologies. In recent years, the use of voltage-co

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