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Статті в журналах з теми "Flip-flop (electronics)"

Автор: Grafiati

Опубліковано: 23 червня 2022

Оновлено: 19 липня 2025

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1

K., Srilatha, Pujitha B., and V. Sirisha M. "Implementation of D Flip Flop using CMOS Technology." International Journal of Trend in Scientific Research and Development 4, no. 3 (2020): 624–26. https://doi.org/10.5281/zenodo.3892465.

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Анотація:

In this paper, D flip flop has been designed and layout simulated using 32nm technology. This schematic of d flip flop has been designed using and its equivalent layout is created using Micro wind tools. The performance has been Analysed and compared in terms of area and power and delay. These proposed circuits are investigated in terms of area and power consumption and delay. K. Srilatha | B. Pujitha | M. V. Sirisha "Implementation of D Flip-Flop using CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volum

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2

Gomathi, R., S. Gopalakrishnan, S. Ravi Chand, S. Selvakumaran, J. Jeffin Gracewell, and Kalivaraprasad B. "Design and Speed Analysis of Low Power Single and Double Edge Triggered Flip Flop with Pulse Signal Feed-Through Scheme." International Journal of Electrical and Electronics Research 10, no. 4 (2022): 1107–14. http://dx.doi.org/10.37391/ijeer.100456.

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Flip flop is a fundamental electrical design component. Most electrical designs incorporate memory and their corresponding designs. The consumer electronics or end users need mobility and extended battery backup to enhance design performance. The focus on any parameter in the system is to maximize the performance of the design. Here the task is to reduce the energy use of flip flop. Due to the increased frequency clock delivered to the networks within the design, the edge or level triggered by a flip flop will contribute to power consumption. Due to the short circuit power consumption between

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3

Surbhi, Vishwakarma, and Vinod Kapse Dr. "Design of Dual Pulsating Latch Flip Flop DPLFF using Novel Pulse Generator." International Journal of Trend in Scientific Research and Development 2, no. 2 (2018): 1713–18. https://doi.org/10.31142/ijtsrd12743.

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In this paper various flip flop structures have been studied. In all designs to reduce power consumption, the Pulse Generator circuitry should be in build along with the flip flop itself. If a pulse generator is included along with DPSCRFF structure, power consumption can be reduced. In this work a new design of flip flop, Double Pulse Latch Flip flop DPLFF is proposed. DPLFF eliminates unnecessary glitches, which consume more power. DPLFF consume less power for same delay as compared with other existing techniques, which is performing one of the fastest known flip flops. In serial operation a

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4

Mathis, Wolfgang. "100 years multivibrator-history, circuits and mathematical analysis." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, no. 3 (2020): 725–37. http://dx.doi.org/10.1108/compel-10-2019-0411.

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Purpose This work is intended to historically commemorate the one hundredth anniversary of the invention of a new type of electronic circuit, referred to in 1919 by Abraham and Bloch as a multivibrator and by Eccles and Jordan as a trigger relay (later known as a flip-flop). Design/methodology/approach The author also considers the circuit-technical side of this new type of circuit, considering the technological change as well as the mathematical concepts developed in the context of the analysis of the circuit. Findings The multivibrator resulted in a “circuit shape” which became one of the mo

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5

Lin, Dave Y. W., and Charles H. P. Wen. "A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (2021): 1–12. http://dx.doi.org/10.1145/3462171.

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As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF wi

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6

Ragavendran, U., and M. Ramachandran. "Low Power and Low Complexity Flip-Flop Design using MIFGMOS." International Journal of Engineering & Technology 7, no. 3.1 (2018): 183. http://dx.doi.org/10.14419/ijet.v7i3.1.17233.

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Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.

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7

Guo, Wei Jia, Shu Bao Wang, Gui Jing Mei, and Xiu Mei Zhang. "Swift Self-Starting Design of Sequential Logic Circuit Based on Karnaugh Map." Applied Mechanics and Materials 220-223 (November 2012): 1008–11. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.1008.

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To make the circuit self-start swiftly in the environment with much disturbance, according to the principle of being propitious to simplify state equation and output equation, assigned a next state for each bound term on Karnaugh map, and the next state must be a state of the valid cycle, at last tested the method by simulation. In the simulation, imitated the disturbance by the set pin or reset pin of flip-flop. The simulation based on electronics workbench 5.0C shows the effectiveness and feasibility of the method.

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8

Swathi, Prabhu, H. R. Unnathi, B. R. Chethan, R. Tejaswini, and A. O. Vaishnavi. "Review on multi bit flip-flop enhanced shift register: A low power solution for UART." i-manager’s Journal on Electrical Engineering 17, no. 2 (2023): 35. http://dx.doi.org/10.26634/jee.17.2.20432.

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This paper details the Verilog HDL- based design of UART modules. Developing UART with a shift register utilizing multibit flip-flops proves to be pragmatic strategy for contemporary VLSI circuits. This work supports not only asynchronous and serial communication but also aligns with essential objectives of minimizing power consumption and reducing overall circuit area. Such integration enhances data transmission efficiency while meeting crucial design considerations in modern electronics

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9

Rompis, Lianly. "A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER." Jurnal Ilmiah Realtech 14, no. 1 (2018): 64–68. http://dx.doi.org/10.52159/realtech.v14i1.118.

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Анотація:

Mostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, using shift register and encoder, which is easier to applied and the sequence of this counter can be managed rand

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10

Rahman, Aminur, Ian Jordan, and Denis Blackmore. "Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops." Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 474, no. 2209 (2018): 20170111. http://dx.doi.org/10.1098/rspa.2017.0111.

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It has been observed through experiments and SPICE simulations that logical circuits based upon Chua’s circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some dis

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11

Prema, S., N. Karthikeyan, and S. Karthik. "Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications." Journal of Medical Imaging and Health Informatics 11, no. 12 (2021): 3215–22. http://dx.doi.org/10.1166/jmihi.2021.3919.

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To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be u

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12

Hassan, Ahmad, Jean-Paul Noël, Yvon Savaria, and Mohamad Sawan. "Circuit Techniques in GaN Technology for High-Temperature Environments." Electronics 11, no. 1 (2021): 42. http://dx.doi.org/10.3390/electronics11010042.

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As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilli

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13

Buzzi, Alessandro, Matteo Castellani, Reed A. Foster, Owen Medeiros, Marco Colangelo, and Karl K. Berggren. "A nanocryotron memory and logic family." Applied Physics Letters 122, no. 14 (2023): 142601. http://dx.doi.org/10.1063/5.0144686.

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The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show [Formula: see text] bit error rates with above [Formula: see text

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14

Wang, An Jing, and Yu Zhuo Fu. "Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact." Applied Mechanics and Materials 716-717 (December 2014): 1239–43. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1239.

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Анотація:

Recently, Multi-bit flip-flop usage has shown its advantage in dynamic power saving in nowadays commercial electronic design. This paper present a more comprehensive comparison of chip-level synthesis result by using single-bit flip-flop and multi-bit flip-flop standard cell and except for analyzing the power and area benefit from replacement under the maximum speed, this paper give a compromise solution to solve that using multi-bit flip-flop cannot run as the fastest as single-bit with even large area. The trade-off between a multi-bit flip-flop cell driving strength and its area when design

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15

Avikshit., B., and Ramesh K.B. "Design and Implementation of an Power Efficient Clock Pulsed D-Flip Flop Using Transmission Gate." Journal of VLSI Design and its Advancement 7, no. 3 (2024): 1–7. https://doi.org/10.5281/zenodo.12642709.

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<em>In the realm of recent digital applications demanding highly efficient and swift devices with minimal delay and power consumption, this study introduces a low-power clock-pulsed data flip-flop (D flip-flop) featuring a transmission gate. The key innovation lies in the implementation of clock gating to enhance power efficiency. By utilizing an AND gate to interrupt the clock input based on a control signal named Enable, unnecessary transistor switching is curtailed, consequently lowering dynamic power consumption. This clock gating strategy ensures that the clock is deactivated during perio

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16

CHANG, ROBERT C., L. C. HSU, and M. C. SUN. "A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH." Journal of Circuits, Systems and Computers 11, no. 01 (2002): 51–55. http://dx.doi.org/10.1142/s0218126602000239.

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A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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17

Komshina, A., S. Telibaev, and B. S. Mikhlin. "ASSEMBLING THE RS FLIP-FLOP ON CHIPS CONTAINING ELEMENTS OF "OR-NOT", "AND-NOT"." Informatics in school, no. 7 (November 17, 2018): 17–25. http://dx.doi.org/10.32517/2221-1993-2018-17-7-17-25.

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The article provides general information about flip-flops, their types, about an asynchronous RS flip-flop. A detailed description of the practical work on assembling the RS flip-flop in two variants is given, based on a chip containing four "2OR-NOT" elements, and based on a chip containing four "2AND-NOT" elements. The details from the electronic set "Micronik" ("Amperka") and the details provided by the site "Let's create together" are used in assembling.

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18

Gabrielli, Alessandro, Fabrizio Alfonsi, Alberto Annovi, Alessandra Camplani, and Alessandro Cerri. "Hardware Implementation Study of Particle Tracking Algorithm on FPGAs." Electronics 10, no. 20 (2021): 2546. http://dx.doi.org/10.3390/electronics10202546.

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In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are eve

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19

Liu, J. M., and Y. C. Chen. "Optical flip-flop." Electronics Letters 21, no. 6 (1985): 236. http://dx.doi.org/10.1049/el:19850169.

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20

Badugu, Divya Madhuri, Sunithamani S., Javid Basha Shaik, and Ramesh Kumar Vobulapuram. "Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology." Circuit World 47, no. 1 (2020): 51–59. http://dx.doi.org/10.1108/cw-10-2019-0141.

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Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of th

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21

Majeed, Ali, Esam Alkaldy, Mohd Zainal, and Danial Nor. "Novel Memory Structures in QCA Nano Technology." 3D SCEEER Conference sceeer, no. 3d (2020): 119–24. http://dx.doi.org/10.37917/ijeee.sceeer.3rd.17.

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Quantum-dot Cellular Automata (QCA) is a new emerging technology for designing electronic circuits in nanoscale. QCA technology comes to overcome the CMOS limitation and to be a good alternative as it can work in ultra-high-speed. QCA brought researchers attention due to many features such as low power consumption, small feature size in addition to high frequency. Designing circuits in QCA technology with minimum costs such as cells count and the area is very important. This paper presents novel structures of D-latch and D-Flip Flop with the lower area and cell count. The proposed Flip-Flop ha

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22

Yin, Chenyu, Yulun Zhou, Hongxia Liu, and Qi Xiang. "SEU Hardened D Flip-Flop Design with Low Area Overhead." Micromachines 14, no. 10 (2023): 1836. http://dx.doi.org/10.3390/mi14101836.

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D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the value stored in the flip-flop. On this basis, a new structure D flip-flop is proposed in this paper. This flip-flop uses an asymmetric scheme in which the master–slave latch adopts different hardening structures. By sacrificing circuit speed in exchange for stronger SEU fortification capability, the SEU threshold of this structure is improved b

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23

Khan, Muhammad Imran. "Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems." ACM Transactions on Design Automation of Electronic Systems 28, no. 4 (2023): 1–17. http://dx.doi.org/10.1145/3590770.

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This paper presents estimation and analysis of the higher order harmonics, power features, and real performance of flip-flop and master-slave latch topologies. This research article outlines the impact of transistor model quality and input signal selection on the estimate of higher order harmonic contents of switching waveform emitted by the digital integrated circuits. Highly integrated systems require accurate estimation of higher order harmonics to control noise. This work presents simulations of 12 kinds of flip-flop and latch topologies on different process technologies i.e., 28 nm, 45 nm

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24

Duraivel, A. N., B. Paulchamy, and K. Mahendrakan. "Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 602–11. http://dx.doi.org/10.1166/jno.2021.2984.

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Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but

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25

Lala, P. K., and A. Walker. "A Fine Grain Configurable Logic Block for Self-checking FPGAs." VLSI Design 12, no. 4 (2001): 527–36. http://dx.doi.org/10.1155/2001/83474.

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This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical.

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26

Pal, Amrindra, Santosh Kumar, and Sandeep Sharma. "Design of Optical SR Latch and Flip-Flop Using Electro-Optic Effect Inside Lithium–Niobate-Based Mach–Zehnder Interferometers." Journal of Optical Communications 40, no. 2 (2019): 119–34. http://dx.doi.org/10.1515/joc-2017-0053.

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Abstract Set-Reset (SR) latch or flip-flop is bistabile circuit. The circuit maintains a binary state indefinitely until directed by an input signal (clock signal) to switch state. Sequential logic circuits for specific application can be implemented by using SR flip-flop and external gates. In this article, SR latch and SR flip-flop is proposed using electro-optic effect inside lithium–niobate-based Mach–Zehnder interferometers (MZIs). The MZI structures have the powerful capability of switching an optical input signal to a desired output port. The article constitutes a mathematical descripti

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27

G. S., Jayadeva, Nikhil Murali, Meghana S., Raksha K. Kumar, and Nithin Anil Nair. "Design and Implementation of a High-Speed D Flip Flop using CMOS Inverter Logic." WSEAS TRANSACTIONS ON ELECTRONICS 13 (December 19, 2022): 125–29. http://dx.doi.org/10.37394/232017.2022.13.16.

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This paper proposes an improvised D- flip flop configuration based on tristate inverter logic, which reduces the power dissipation, decrease the transition time from the input to output as well as reduced time to reach rail to rail voltage. The flip flop uses transmission gate instead of pass transistor to achieve this requirement. The design is simulated using 90nm CMOS technology and data is propagated at 50% duty cycle. The circuit is simulated using Cadence tools to assess the performance with respect to delay and power. These D-flip flops have numerous applications such as buffers, regist

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28

Nafees, Naira, Suhaib Ahmed, Vipan Kakkar, Ali Newaz Bahar, Khan A. Wahid, and Akira Otsuki. "QCA-Based PIPO and SIPO Shift Registers Using Cost-Optimized and Energy-Efficient D Flip Flop." Electronics 11, no. 19 (2022): 3237. http://dx.doi.org/10.3390/electronics11193237.

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With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D f

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29

Wang, Shixin, Lixin Wang, Yue Wang, Min Guo, and Yuanzhe Li. "A Novel Radiation-Hardened CCDM-TSPC Compared with Seven Well-Known RHBD Flip-Flops in 180 nm CMOS Process." Electronics 11, no. 19 (2022): 3098. http://dx.doi.org/10.3390/electronics11193098.

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Numerous radiation-hardened-by-design (RHBD) flip-flops have been developed to increase the dependability of digital chips for space applications over the past two decades. In this paper, the radiation immunity and performance of seven well-known RHBD flip-flops are discussed. A novel cross-connected dual modular redundant true single-phase clock (TSPC) D flip-flop (CCDM-TSPC) is proposed. The presented CCDM-TSPC replaces the typical master-slave D flip-flop (MS-DFF) with the fundamental TSPC structure to shorten the circuit’s propagation time. All sensitive points in the circuit are radiation

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30

Stephan, G., B. Aissaoui, and A. Kellou. "A flip-flop interferometer." IEEE Journal of Quantum Electronics 23, no. 4 (1987): 458–60. http://dx.doi.org/10.1109/jqe.1987.1073366.

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31

Zhuang, N., and H. Wu. "Novel ternary JKL flip-flop." Electronics Letters 26, no. 15 (1990): 1145. http://dx.doi.org/10.1049/el:19900741.

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32

Li, X., S. Jia, X. Liang, and Y. Wang. "Self-blocking flip-flop design." Electronics Letters 48, no. 2 (2012): 82. http://dx.doi.org/10.1049/el.2011.2888.

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33

Park, Jaeyoung, and Young Yim. "Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop." Micromachines 10, no. 6 (2019): 411. http://dx.doi.org/10.3390/mi10060411.

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An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead;

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Sanadhya, Minakshi, and Devendra Kumar Sharma. "D flip-flop design by adiabatic technique for low power applications." Indonesian Journal of Electrical Engineering and Computer Science 29, no. 1 (2022): 141. http://dx.doi.org/10.11591/ijeecs.v29.i1.pp141-146.

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Indigital circuits, energy reduction is the most important parameter in the design of handy and battery-operated devices. Flip- flop is an important component in any digital system. By improving the performance of flip-flop, complete system performance is better. This paper addresses the design of D flip-flop using direct current diode-based positive feedback adiabatic logic (DC-DB PFAL) at various frequencies at 45nm technology node. Further, the layout for the proposed design is also presented. The performance analysis is carried out for delay, power dissipation, power delay product and tran

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Lin, Jin-Fa, Zheng-Jie Hong, Jun-Ting Wu, Xin-You Tung, Cheng-Hsueh Yang, and Yu-Cheng Yen. "Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design." Sensors 22, no. 15 (2022): 5696. http://dx.doi.org/10.3390/s22155696.

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A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activit

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Arunabala, Dr C., A. Lohithakshi, D. Jyothsna, CH Pranathi, and A. Navaneetha. "Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods." International Journal of Innovative Technology and Exploring Engineering 11, no. 5 (2022): 32–36. http://dx.doi.org/10.35940/ijitee.e9850.0411522.

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This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift regi

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Xu, Daiguo, Shiliu Xu, and Yuxin Wang. "Improved self‐blocking flip‐flop design." Electronics Letters 52, no. 14 (2016): 1207–9. http://dx.doi.org/10.1049/el.2016.0836.

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Kanjamala, A. P., and A. F. J. Levi. "Wavelength selective electro-optic flip-flop." Electronics Letters 34, no. 3 (1998): 299. http://dx.doi.org/10.1049/el:19980224.

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Sanadhya, Minakshi, Devendra Kumar Sharma, and Alfilh Raed Hameed Chyad. "Adiabatic technique based low power synchronous counter design." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (2023): 3770. http://dx.doi.org/10.11591/ijece.v13i4.pp3770-3777.

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<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit syn

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Monga, Kanika, Nitin Chaturvedi, and S. Gurunarayanan. "Energy-efficient data retention in D flip-flops using STT-MTJ." Circuit World 46, no. 4 (2020): 229–41. http://dx.doi.org/10.1108/cw-09-2018-0073.

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Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin tran

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Koshak, Essam, Afzel Noore, and Rita Lovassy. "Intelligent reconfigurable universal fuzzy flip-flop." IEICE Electronics Express 7, no. 15 (2010): 1119–24. http://dx.doi.org/10.1587/elex.7.1119.

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Saf’yannikov, N. M., and P. N. Bondarenko. "Flip-flop device with state actuation." Russian Microelectronics 38, no. 3 (2009): 219–22. http://dx.doi.org/10.1134/s1063739709030093.

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HU, YINGBO, and RUNDE ZHOU. "LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 01 (2009): 121–31. http://dx.doi.org/10.1142/s0218126609004971.

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In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops

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Ashis Kumar Mandal. "All-optical Frequency Divider using TOAD based D-Flip-Flop." January 2021 7, no. 01 (2021): 152–57. http://dx.doi.org/10.46501/ijmtst070133.

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From the last few decades the optical communication has been established as much easier process than electrical communication. Many optical proposed circuits have already been suggested in many fields in support of this. The optical communication circuits demand frequency dividers capable of operating well above 10 GHz. Here, an all-optical frequency divider using terahertz optical asymmetric demultiplexer (TOAD) based D-flip-flop is proposed in the optical domain in a configuration exactly like the standard electronic setup. It presents a high-speed flip-flop-based frequency divider incorpora

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MONTEIRO, JOSÉ, SRINIVAS DEVADAS, and ABHIJIT GHOSH. "RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER." International Journal of High Speed Electronics and Systems 07, no. 02 (1996): 323–40. http://dx.doi.org/10.1142/s0129156496000141.

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Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted swi

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Breznik, Andrej, Tomaž Zakrajšek, and Boris Turk. "MRI findings in serous atrophy of bone marrow in spinal imaging." MEDICAL IMAGING AND RADIOTHERAPY JOURNAL 39, no. 1 (2022): 18–21. http://dx.doi.org/10.47724/mirtj.2022.i02.a003.

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Introduction: Serous atrophy of bone marrow (SABM) is a rare, and potentially reversible, cause of diffuse look, irregular bone marrow and subcutaneous adipose tissue appearances on magnetic-resonance imaging (MRI). SABM has also been named gelatinous bone marrow transformation (GTMB) or ‘starvation marrow’. Purpose: The aim of the article is to represent a case report of ‘flip-flop’ phenomenon in SABM and GTBM pathology. Material and methods: This case report highlights an unexpected image appearance of an occurrence ‘flip-flop’ effect which is characteristic in the condition of serous atroph

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Bhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.

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Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation

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Zhao, Xianghong, Longhua Ma, Hongye Su, Jieyu Zhao, and Weiming Cai. "High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 528–33. http://dx.doi.org/10.1166/jno.2021.2976.

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In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed,

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Jin-Woo Han, Jae-Hyuk Ahn, and Yang-Kyu Choi. "FinFACT—Fin Flip-Flop Actuated Channel Transistor." IEEE Electron Device Letters 31, no. 7 (2010): 764–66. http://dx.doi.org/10.1109/led.2010.2048093.

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Jian Zhou, Jin Liu, and Dian Zhou. "Reduced setup time static D flip-flop." Electronics Letters 37, no. 5 (2001): 279. http://dx.doi.org/10.1049/el:20010197.

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