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Дисертації з теми "FPGA resources"

Автор: Grafiati

Опубліковано: 30 травня 2022

Оновлено: 19 липня 2025

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1

Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191286.

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Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfig

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2

Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-231445.

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The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concep

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3

Iordache, Ancuta. "Performance-cost trade-offs in heterogeneous clouds." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S045/document.

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Les infrastructures de cloud fournissent une grande variété de ressources de calcul à la demande avec différents compromis coût-performance. Cela donne aux utilisateurs des nombreuses opportunités pour exécuter leurs applications ayant des besoins complexes en ressources, à partir d’un grand nombre de serveurs avec des interconnexions à faible latence jusqu’à des dispositifs spécialisés comme des GPUs et des FPGAs. Les besoins des utilisateurs concernant l’exécution de leurs applications peuvent varier entre une exécution la plus rapide possible, la plus chère ou un compromis entre les deux. C

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4

Hassan, Mohamed Nabil. "Low resource scalable elliptic curve cryptography on FPGA." Thesis, University of Sheffield, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.522417.

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5

Lam, Andrew H. "An analytical model of logic resource utilization for FPGA architecture development." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/19753.

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Designers constantly strive to improve Field-Programmable Gate Array (FPGA) performance through innovative architecture design. To evaluate performance, an understanding of the eﬀects of modifying logic blocks structures and routing fabrics on performance is needed. Current architectures are evaluated via computer-aided design (CAD) simulations that are labourious and computationally-expensive experiments to perform. A more scientiﬁc method, based on understanding the relationships between architectural parameters and performance will enable the rapid evaluation of new architectures, even befo

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6

Hinnerson, Martin. "A Resource Efficient, HighSpeed FPGA Implementation of Lossless Image Compression for 3D Vision." Thesis, Linköpings universitet, Datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-165300.

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High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless comp

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7

Thangella, Praneeth Kumar, and Aravind Reddy Gundla. "Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16547.

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<p>AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.</p>

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8

Tolmie, Donald Francois. "Design of a low-resource 2D graphics engine for FPGAs." Master's thesis, Faculty of Engineering and the Built Environment, 2018. http://hdl.handle.net/11427/30042.

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This study focused on the design and implementation of a low-resource graphics engine, MicroGE, which can be implemented on an FPGA. MicroGE uses a minimal amount of FPGA resources when compared to other graphics engines. After researching existing graphics engines, it was discovered that most make use of a memory space to store frame buffer data. Because of the restrictions that were imposed on the design of MicroGE, it could not incorporate a large enough memory space to store a frame buffer. It was specified that MicroGE should be able to fit on low-resource FPGAs, without any external memo

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9

Yao, Jia Stroud Charles E. "Built-In self-test of global routing resources in Virtex-4 FPGAs." Auburn, Ala., 2009. http://hdl.handle.net/10415/1723.

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10

Simons, Taylor Scott. "High-Speed Image Classification for Resource-Limited Systems Using Binary Values." BYU ScholarsArchive, 2021. https://scholarsarchive.byu.edu/etd/9097.

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Анотація:

Image classification is a memory- and compute-intensive task. It is difficult to implement high-speed image classification algorithms on resource-limited systems like FPGAs and embedded computers. Most image classification algorithms require many fixed- and/or floating-point operations and values. In this work, we explore the use of binary values to reduce the memory and compute requirements of image classification algorithms. Our objective was to implement these algorithms on resource-limited systems while maintaining comparable accuracy and high speeds. By implementing high-speed image class

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11

Fowers, Spencer G. "Limited Resource Feature Detection, Description, and Matching." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3207.

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Анотація:

The aims of this research work are to develop a feature detection, description, and matching system for low-resource applications. This work was motivated by the need for a vision sensor to assist the flight of a quad-rotor UAV. This application presented a real-world challenge of autonomous drift stabilization using vision sensors. The initial solution implemented a basic feature detector and matching system on an FPGA. The research then pursued ways to improve the vision system. Research began with color feature detection, and the Color Difference of Gaussians feature detector was developed.

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12

Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем". Thesis, Національний аерокосмічний університет ім. М. Є. Жуковського "Харківський авіаційний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38557.

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Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р. Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з

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13

Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем". Thesis, Національний технічний університет "Харківський політехнічний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38548.

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Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р. Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з

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14

Mollberg, Alexander. "A Resource-Efficient and High-Performance Implementation of Object Tracking on a Programmable System-on-Chip." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124044.

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Анотація:

The computer vision problem of object tracking is introduced and explained. An approach to interest point based feature detection and tracking using FAST and BRIEF is presented and the selection of algorithms suitable for implementation on a Xilinx Zynq7000 with an XC7Z020 field-programmable gate array (FPGA) is detailed. A modification to the smoothing strategy of BRIEF which significantly reduces memory utilization on the FPGA is presented and benchmarked against a reference strategy. Measures of performance and resource efficiency are presented and utilized in an iterative development proce

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15

Hartman, Garrett Sean. "Real-Time Color TreeBASIS Feature Matching on a Limited-Resource Hardware System." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/4002.

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Анотація:

This research has been conducted in order to create a robust, lightweight feature detecting and matching algorithm that builds upon the foundation set by the TreeBASIS algorithm. The goal is to create a color-based version of the TreeBASIS algorithm that uses less hardware resources than the original, is more accurate in its matching capabilities, can successfully be deployed on a resource-limited FPGA platform, and can process in real time. This thesis first presents the newly designed hardware tri-channel FAST Feature Detector that finds features in color. Next the TreeBASIS algorithm is ana

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16

Al, Rawashdeh Khaled. "Toward a Hardware-assisted Online Intrusion Detection System Based on Deep Learning Algorithms for Resource-Limited Embedded Systems." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535464571843315.

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17

Young, Jeffrey Scott. "Global address spaces for efficient resource provisioning in the data center." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50261.

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Анотація:

The rise of large data sets, or "Big Data'', has coincided with the rise of clusters with large amounts of memory and GPU accelerators that can be used to process rapidly growing data footprints. However, the complexity and performance limitations of sharing memory and accelerators in a cluster limits the options for efficient management and allocation of resources for applications. The global address space model (GAS), and specifically hardware-supported GAS, is proposed as a means to provide a high-performance resource management platform upon which resource sharing between nodes and resourc

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18

Mahmood, Adnan, and Zaheer Ahmed Mohammed. "DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP." Thesis, Jönköping University, JTH, Computer and Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.

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<p>Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed rout

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19

Sun, Hua. "Throughput constrained and area optimized dataflow synthesis for FPGAS." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2276.pdf.

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20

Hireche, Chabha. "Etude et implémentation sur SoC-FPGA d'une méthode probabiliste pour le contrôle de mission de véhicule autonome Embedded context aware diagnosis for a UAV SoC platform, in Microprocessors and Microsystems 51, June 2017 Context/Resource-Aware Mission Planning Based on BNs and Concurrent MDPs for Autonomous UAVs, in MDPI-Sensors Journal, December 2018." Thesis, Brest, 2019. http://www.theses.fr/2019BRES0067.

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Анотація:

Les systèmes autonomes embarquent différents types de capteurs, d’applications et de calculateurs puissants. Ils sont donc utilisés dans différents domaines d’application et réalisent diverses missions simples ou complexes. Ces missions se déroulent souvent dans des environnements non déterministes avec la présence d’évènements aléatoires pouvant perturber le déroulement de la mission. Il est donc nécessaire d’évaluer régulièrement l’état de santé du système et de ses composants matériels et logiciels dans le but de détecter les défaillances à l’aide de réseaux Bayésiens. Par la suite, une déc

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21

Boukhtache, Seyfeddine. "Système de traitement d’images temps réel dédié à la mesure de champs denses de déplacements et de déformations." Thesis, Université Clermont Auvergne‎ (2017-2020), 2020. http://www.theses.fr/2020CLFAC054.

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Анотація:

Cette thèse s’inscrit dans un cadre pluridisciplinaire. Elle traite de la problématique du temps réel et de celle des performances métrologiques en traitement d’images numériques. Elle s'intéresse plus particulièrement à la photomécanique. Il s'agit d'une discipline récente visant à développer et à utiliser au mieux des systèmes de mesure de champs entiers de petits déplacements et de petites déformations en surface de solides soumis à des sollicitations thermomécaniques. La technique utilisée dans cette thèse est la corrélation des images numériques (CIN), qui se trouve être l'une des plus em

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22

Isaacson, Spencer W. "Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip." BYU ScholarsArchive, 2007. https://scholarsarchive.byu.edu/etd/971.

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Анотація:

Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel

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23

Hung, Yu-Shan, and 洪羽珊. "performance driven FPGA partitioning with complex resources." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/96617730412697036494.

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碩士<br>中原大學<br>資訊工程研究所<br>89<br>To shorten time to market , the architecture , FPGA, is used widely. Because the circuit is larger and more complex, it is necessary to partition a large circuit to several sub-circuits. Although a FPGA is programmable, the chief shortcoming of FPGA is poor performance, so that many real time systems can not implemented by FPGAs, especially when we deal with the problem of FPGA partitioning, the performance problem is more serious. We will partition the circuit to several different FPGAs and the delay of the wires cross two FPGAs is larger. We hope to decrease th

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24

Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, 2015. https://tud.qucosa.de/id/qucosa%3A29126.

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Анотація:

Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfig

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25

Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, 2017. https://tud.qucosa.de/id/qucosa%3A30681.

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Анотація:

The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concep

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26

黃峻然. "A Rearrangeable Hierarchical Interconnection Structure for FPGA Routing Resource." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29154315050553224929.

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碩士<br>國立臺灣海洋大學<br>資訊工程學系<br>98<br>Field Programmable Gate Arrays (FPGA’s) are now widely used for the implementation of digital circuits and many commercial products. Since the programmable switches usually have high resistance and capacitance and occupy a large area, the number of programmable switches used in an FPGA affects its speed performance, die size, and routability. In this thesis, we propose a rearrangeable hierarchical switching network (HSN) for the implementation of an FPGA. The main component of this HSN consists of polygonal switch blocks and crossbars. With the same size and t

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27

Chen, Yen-Yu, and 陳彥宇. "FPGA Realization of a MIMO-OFDM System with Optimized Hardware Resource Utilization." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/04667297508207657216.

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碩士<br>國立交通大學<br>電信工程系所<br>94<br>In recent years, orthogonal frequency division multiplexing (OFDM) becomes a key technology in the development of new wireless communication systems, enabling high data rate transmission, and is suitable for frequency selective channels caused by multipath propagation. On the other hand, multiple-input multiple-output (MIMO) technique has a great potential of delivering either a dramatic increase of throughput or improvement of link quality. Combined with the MIMO technique, OFDM systems become more suited to next generation wireless communications. In this thes

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28

Masrani, Divyang K. "Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low." 2006. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=442188&T=F.

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29

Hou, Guan-Hao, and 侯冠豪. "An FPGA-based 200-ps Resolution 16-channel Formatter with Low Resource Usage." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t9fe25.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>106<br>Automatic Test Equipment (ATE) is used to test the performance and features of the Inte-grated Circuit, and avoiding the defective ICs from entering to the market. Formatter in the ATE is the vital core module to load the symbol data by user’s defi-nition, and then generate the testing waveform for the circuit which should be measured. In this paper, it proposes a new way to generate the new symbol and time/format set table, and implements the muti-channel formatter on Xilinx Spatan-6 FPGA board. Using the especially designed for the programmable dela

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30

Wei, Ya-Ti, and 魏雅笛. "Using Decision Trees to Improve Resource Utilization on FPGA-based Network Intrusion Detection System." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/89652649266820124688.

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碩士<br>國立中央大學<br>資訊管理研究所<br>97<br>As network services become more and more important in our society, the demand for network security systems is increasing. Network intrusion detection systems (NIDS) provide an effective and secure solution to the network attacks and are widely used in enterprises. Many NIDSs, such as Snort, are based on software, so their processing speeds are much slower than wire-speed. FPGA technology has properties which are high speed string matching and reprogrammable, but the resources in FPGA are limited while the database of signatures has become very large and

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31

Chang, Yi-Fan, and 張奕凡. "Resource-Aware Asynchronous Circuit Synthesis on FPGA and a Case Study of Secure AES Design." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/xfhz93.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>107<br>Asynchronous circuits have distinct advantages over their synchronous counterparts, e.g., in their security against side-channel attacks, resilience against process variation, robustness against environmental fluctuation, low electromagnetic interference, and ease of design composition, among other benefits. Among various asynchronous delay models, quasi-delay insensitive (QDI) circuits with dual-rail encoding are promising due to its relaxed timing assumption and timing robustness. Furthermore, dual-rail precharge logic (DRPL) has been considered to be a pra

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32

Tseng, Su-Fen, and 曾淑芬. "Cost Minimization of Partitioned Circuits with Complex Resource Constraints in FPGAs." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/06409114514119696010.

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Анотація:

碩士<br>中原大學<br>資訊工程學系<br>87<br>In FPGAs with complex resources, each circuit element can be implemented by variant resources and each resource can implement one ore more circuit elements. Usually it is difficult to randomly generate a feasible initial solution. In this thesis, we have solved this by maximum-matching method. A new cost minimization partitioning problem with complex resource constraints in FPGAs is formulated and solved. We first write the complex resources constraints in ILP model and use the ILP solver, LINGO, to find the types and numbers of FPGA chips needed to min

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Bridger, Andrew B. "Increasing the spectral efficiency of contunous phase modulation applied to digital microwave radio : a resource efficient FPGA receiver implementation : [a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Electronics and Computer Systems Engineering at Massey University, Palmerston North, New Zealand ] EMBARGED UNTIL 1 JUNE 2012." 2009. http://hdl.handle.net/10179/1366.

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Анотація:

In modern point to point microwave radio systems used to backhaul cellular voice and data traffic, quadrature amplitude modulation (QAM) is the norm. These systems require a highly linear power amplifier which is expensive and has relatively low power efficiency. Recently, continuous phase modulation (CPM) has been deployed in this market. The CPM transmitted waveform has a constant envelope and so a non-linear RF power amplifier can be used. This significantly reduces cost and improves power efficiency. Two important disadvantages of CPM are receiver complexity and inferior spectral efficienc

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Müller, Günter Stefan. "FTIR-ATR spectroscopic and FTIR-FPA microscopic investigations on panel board production processes using Grand fir (Abies grandis (Douglas ex D. Don) Lindl.) and European beech (Fagus sylvatica L.)." Doctoral thesis, 2008. http://hdl.handle.net/11858/00-1735-0000-0006-B10E-4.

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