Дисертації з теми "Germanium on insulator"
Щоб переглянути інші типи публікацій з цієї теми, перейдіть за посиланням: Germanium on insulator.
Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями
Ознайомтеся з топ-33 дисертацій для дослідження на тему "Germanium on insulator".
Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.
Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.
Переглядайте дисертації для різних дисциплін та оформлюйте правильно вашу бібліографію.
1
Hennessy, John 1980. "Germanium on insulator fabrication technology." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28556.
Анотація:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 53-55).
As CMOS devices continue to scale to smaller dimensions, it has become clear that new materials and structures are needed to also continue to improve performance. Germanium on insulator is proposed as it combines both a high mobility material (relative to silicon) and a structure with improved scaling characteristics compared to bulk devices. The goal of this work is to develop of procedure for the transfer of a germanium layer to bulk silicon by means of wafer bonding and hydrogen-induced layer transfer.
by John Hennessy.
S.M.
2
Gay, Diane Lorraine. "Silicon on insulator fabrication using silicon germanium etch stop and polish stop techniques." Thesis, Queen's University Belfast, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.388096.
3
Kah, Masamba. "Comparative study of boron activation in silicon, silicon-on-insulator and silicon-germanium substrates." Thesis, University of Surrey, 2011. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.540711.
4
Ozguven, Nevran. "Interdiffusion studies in silicon-germanium heterostructures and selective oxidation for fabricating Ge-on-insulator /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
5
England, Troy Daniel. "Silicon-germanium BiCMOS and silicon-on-insulator CMOS analog circuits for extreme environment applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51806.
Анотація:
Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.
6
Yuk, Hyung-Sang. "A novel fabrication technique of silicon germanium-on-insulator (SGOI) for SIGe heterostructure CMOS technology." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.416442.
7
Bellini, Marco. "Operation of silicon-germanium heterojunction bipolar transistors on." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28206.
Анотація:
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Cressler, John D.; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephen; Committee Member: Shen, Shyh-Chiang; Committee Member: Zhou, Hao Min.
8
Feng, Jia. "High-performance germanium-on-insulator MOSFETs for three-dimensional integrated circuits based on rapid melt growth /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
9
Hutin, Louis. "Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0159.
Анотація:
Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concomitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel : comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par : la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnelUntil the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS
10
Passanante, Thibault. "Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI." Thesis, Aix-Marseille, 2014. http://www.theses.fr/2014AIXM4020.
Анотація:
Ce travail de thèse est consacré à l’étude expérimentale des mécanismes de démouillage de films solides d’épaisseur nanométrique conduisant à la transformation d’un film mince en une assemblée d’îlots tridimensionnels. L’utilisation de la microscopie à électrons lents (LEEM) nous a permis d’étudier la morphologie et la cinétique in situ et en temps réel du démouillage de films de Si/SiO2 (SOI) et de Ge/SiO2 (GOI) obtenus par collage moléculaire (procédé Smart Cut™). Ces mesures expérimentales ont été complétées par des analyses par diffusion centrale des rayons X en incidence rasante (GISAXS) et des observations ex situ par microscopie à force atomique (AFM). Les mécanismes de démouillage de SOI et GOI sont thermodynamiquement pilotés par la capillarité et cinétiquement contrôlés par la diffusion de surface. L’étude complémentaire du démouillage à partir de fronts cristallographiquement orientés obtenus par lithographie nous a permis d’analyser le rôle central du facettage, de l’anisotropie cristalline et des processus de formation du bourrelet de démouillage. En particulier, le rôle de la nucléation 2D sur la cinétique d’épaississement (couche par couche) du bourrelet a pu être mis en évidence. Les résultats expérimentaux ont pu être confrontés à des modèles analytiques et des simulations de type Monte Carlo cinétique. Nous en avons déduit les valeurs des paramètres physiques pertinents et avons attribué les différences de morphologies entre SOI et GOI à la présence de facettes spécifiquesThis work is devoted to the experimental study of the dewetting mechanisms of ultrathin solid films by which a metastable film transforms into an assembly of tridimensional crystallites. Using low energy Electron Microscopy (LEEM) we analyse, in situ and in real time, the morphology and the kinetics of the dewetting of Si/SiO2 (SOI) and Ge/SiO2 (GOI) systems obtained by molecular bonding (Smart Cut™ process). Further information has been obtained by Grazing Incidence Small Angle X–ray Scattering (GISAXS) and Atomic Force Microscopy (AFM) measurements. We show that the dewetting is driven by surface free energy minimization and mediated by surface diffusion. A complementary study of artificial well-oriented dewetting fronts obtained by lithography enables us to analyze the important role played by facets, the crystal anisotropy and the rim thickening mechanism. We show that the rim thickening proceeds in a layer-by-layer mode and is limited by 2D nucleation. Thanks to analytical models and Kinetics Monte Carlo simulations, numerical values of the pertinent physical parameters involved in the dewetting process are obtained and the morphological differences between SOI and GOI are attributed to the presence of specific facets
11
Wilkinson, Aidan. "Transport phenomena in two-phase systems." Thesis, Loughborough University, 2017. https://dspace.lboro.ac.uk/2134/25574.
Анотація:
The physics of two-phase systems is explored here, particularly magneto-transport and low temperature d.c. conductivity in thin films. The extraordinary magnetoresistance (EMR) effect was analysed in the context of previous experimental and theoretical considerations. The magnetoresistance (MR) may be enhanced by up to two orders of magnitude by changing the geometry. This was investigated using finite element analysis. Thin film samples consisting of a layered structure of Germanium-Tin-Germanium (Ge-Sn-Ge) were created in collaboration with Shandong University in China. Ge layers were kept at a constant thickness across all samples, with variable Sn thickness. Regions of Sn form island-like shapes ten times larger than the average film thickness, as is seen in scanning electron microscope (SEM) images. Raman spectroscopy was conducted on these samples, from which it is concluded that the Ge layers are amorphous in nature. It was seen that there is a relationship between the electrical resistance and the film thickness which is indicative of a metal-insulator transition (MIT). The temperature dependence of resistivity was subsequently investigated. The temperature coefficient of resistivity (TCR) of the samples is seen to become negative as the thickness of the Sn layer is reduced below a certain critical thickness. Depending on their thickness, samples were designated as metallic or insulator, and various models associated with metals and insulators fitted to the data. While it is impossible to be absolutely certain of the validity of each of the models, some are a better fit than others. The same temperature dependence of resistivity was measured with an applied magnetic field. This is compared with the previous EMR investigation, however the MR of the samples is only of the order of a few percent which corresponds to ordinary MR, seen in most metals. The magnetic field measurements suppress a resistivity down-turn at very low temperatures (T < 10K) which suggests the presence of superconductivity. Analysis of dr=dT shows that the onset of superconductivity is lower for samples with a lower Sn thickness. Additionally, the deposition rate of the Sn layer affects the resistivity significantly; a higher deposition rate causes a decrease in resistivity. It is supposed that this is due to a change in the microstructure of the film. Finally, piezo-resistivity was considered by applying mechanical compression to the samples. The added pressure causes a drop in resistivity.
12
Al-Ahmadi, Ahmad Aziz. "COMPLEMENTARY ORTHOGONAL STACKED METAL OXIDE SEMICONDUCTOR: A NOVEL NANOSCALE COMPLEMENTRAY METAL OXIDE SEMICONDUCTOR ARCHTECTURE." Ohio University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1147134449.
13
Silva, Fábio Alex da. "Estudo de diodos PIN multicamadas atuando como célula fotovoltaica /." São João da Boa Vista, 2020. http://hdl.handle.net/11449/192908.
Анотація:
Orientador: Maria Glória Caño de AndradeResumo: Este trabalho é baseado no estudo do comportamento de um diodo PIN de multicamadas utilizado como célula solar. Esse estudo é desenvolvido por meio de simulações em ambiente virtual, validada a partir de dados experimentais, e tem como foco principal o comportamento da geração de corrente pelo dispositivo, tanto na interação entre o dispositivo e uma determinada faixa do espectro luminoso, como na influência que as alterações nas dimensões dessa célula solar podem trazer na tensão gerada. O diodo PIN proposto encontra-se em uma lâmina SOI (Silicon On Insulator) com uma potencial aplicação destinada para a alimentação de circuitos que necessitam de ultrabaixa potência (ULP – Ultra Low Power), tais como sensores de campo para monitoramento e circuitos subcutâneos para monitoramento médico. É construído por uma camada dupla com diferentes semicondutores (silício e germânio) e, através de alterações em sua estrutura (mudança dos materiais e das dimensões), será verificado o comportamento dos principais parâmetros de uma célula solar, tais como fator de forma (FF), corrente fotogerada, tensão de circuito aberto, corrente de curto-circuito, tensão e corrente de trabalho e potência gerada pelo dispositivo. Adicionalmente, é também analisado o comportamento de penetração e absorção do espectro luminoso na célula solar e a existência de alterações nos parâmetros medidos quando há alteração na posição das camadas de semicondutores, com a finalidade de demonstrar que o incremento de uma... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: This work is based on the study of multilayer PIN diode used as a solar cell. This study was developed through simulations in a virtual environment with the main focus of the generation current by the device so much in the interaction between the device and a range of the light spectrum as well as in the influence the changes in the dimensions of the solar cell may bring in the voltage generated. It is composed of a double layer with different semiconductors (silicon and germanium), and though changes in its structure (materials and dimensions change), it will be verified the behavior of main parameters of a solar cell, such as Fill Factor (FF), photogenerated current, open-circuit voltage, short circuit current, work voltage and work current and the generated power will by the device. Additionally, it was also verified the behavior of the penetration and absorption of the light spectrum in the solar cell, and the existence of changes in the measured parameters when there is a change of position in the semiconductor layers, to demonstrate that the increase of a germanium layer may bring to the device concerning entirely silicon device. The results obtained indicate that there was an increase in the photogeneration when the germanium layer is positioned above the silicon layer. This way, this work demonstrates that small changes in the construction and the thickness of the lateral PIN diode used as a solar cell provide an increase in efficiency of more than 136% when comparing... (Complete abstract click electronic access below)
Mestre
14
Lam, Jennifer Eleanor. "The nature of the metal-insulator transition in silicon germanide quantum wells." Thesis, University of Ottawa (Canada), 1997. http://hdl.handle.net/10393/4399.
Анотація:
A study of the temperature dependence of the resistivity of gated SiGe quantum well structures has revealed a metal-insulator transition as a function of carrier density at zero magnetic field. Although early scaling theories (Abrahams et al., 1979) have argued against the existence of a metal-insulator transition at zero temperature in infinite 2D and 1D systems, more recent theoretical results using a random set of two-dimensional point potentials have shown that such a transition is allowed in two dimensions (Az'bel, 1992). Mounting experimental evidence for such a transition in 2D systems with short range scattering has accumulated in both semiconducting and superconducting structures (Kravchenko et al., 1995, and others). Pseudomorphic, CVD-grown p-type Si/Si$\sb{0.87}$Ge$\sb{0.13}$/Si quantum wells of various widths (65-200 A) have been studied. The samples were gated using a Ti-Au Schottky gate to allow for carrier density variation. Measurement of the transport to quantum lifetime ratio indicates that the transport is dominated by short range scattering. In the temperature range from 400 mK - 4.2 K, the temperature dependence shows a transition from a metallic phase in the high density regime to an insulating phase in the low density regime with a transition boundary close to 2.2 $\times$ 10$\sp $ cm$\sp{-2}$. The scaling properties of the observed metal-insulator transition will be discussed, and compared to previous scaling results from silicon MOSFETs. Below 400 mK, the onset of another transition is accompanied by a sharp drop in resistivity with temperature followed by a monotonic decrease in resistivity below 115 mK. The phase diagram was explored using temperature and density dependences of the current-voltage characteristics.
15
Guillet, Thomas. "Tuning the spin-orbit coupling in Ge for spin generation, detection and manipulation." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALY033.
Анотація:
L'un des principaux objectifs de la spintronique est de réaliser le transistor à spin et pour y parvenir, il faut mettre en œuvre avec succès une plateforme où les courants de spin peuvent être facilement injectés, détectés et manipulés à température ambiante. Dans cette optique, ce travail de thèse montre que le germanium est un très bon candidat grâce à ses propriétés optiques et de spin ainsi qu'à sa compatibilité avec les nanotechnologies à base de silicium.Au fil des années, plusieurs schémas d'injection et de détection de spin ont été réalisés dans Ge, mais la manipulation électrique de l'orientation du spin est toujours une pièce manquante. Dans cette thèse, nous nous sommes concentrés sur deux approches afin de manipuler l'interaction spin-orbite (SOI) dans le germanium. Les deux s'appuient sur l'absence de symétrie d'inversion structurale et le couplage spin-orbite aux surfaces et aux interfaces avec le germanium (111). Tout d'abord, nous avons effectué la croissance épitaxiale de l'isolant topologique Bi2Se3 sur Ge (111). Après avoir caractérisé les propriétés structurales et électriques de l'hétérostructure Bi2Se3/ Ge, nous avons développé une méthode originale pour sonder la conversion courant de spin-courant de charge à l'interface entre Bi2Se3 et Ge en tirant profit des propriétés optiques du Ge. Les résultats ont montré que l'hybridation entre les états de surface de Bi2Se3 et du Ge pourrait permettre la manipulation électrique de l'orientation du spin dans un transistor.La seconde approche consiste à exploiter le SOI intrinsèque de Ge (111). J'ai étudié les propriétés électriques d'un film mince de Ge (111) et découvert que le passage du courant dans des états de sous-surface où l'interaction Rashba est forte, induit un effet de magnétorésistance très particulier que nous avons appelé la magnétorésistance Rashba unidirectionnelle. Elle est due à l'interaction entre le champ magnétique appliqué extérieur et le pseudo champ magnétique induit par le courant appliquée dans les états polarisés en spin du Ge (111). La forte intensité et modularité de cet effet nous mène à penser que ces états pourraient être également mis à profit dans la réalisation d'un transistor à spin tout semi-conducteur.Parallèlement, j'ai intégré des jonctions tunnel magnétiques à anisotropie perpendiculaire à base de multicouches (Co/Pt) sur la plateforme de Ge (111). J'ai développé une technique hybride électro-optique originale basée sur une détection électrique du dichroïsme magnétique circulaire du (Co/Pt) pour faire de l’imagerie magnétique. Ces jonctions tunnel magnétiques ont ensuite été utilisées pour effectuer la génération et la détection de spin dans un dispositif de type vanne de spin latérale. L'anisotropie magnétique perpendiculaire permet de générer un courant de spin avec une orientation de spin perpendiculaire au plan de l'échantillon.Enfin, j'ai rassemblé tous ces éléments développés pendant ma thèse dans un dispositif ultime: un prototype de transistor à spin où une accumulation de spin peut être générée et détectée optiquement et/ou électriquement, en utilisant l'orientation optique de spin dans le germanium ou les jonctions tunnel magnétiquesOne of the main goals of spintronics is to achieve the spin transistor operation and for this purpose, one has to successfully implement a platform where spin currents can be easily injected, detected and manipulated at room temperature. In this sense, this thesis work shows that Germanium is a very good candidate thanks to its unique spin and optical properties as well as its compatibility with Silicon-based nanotechnology.Throughout the years, several spin injection and detection schemes were achieved in Ge but the electrical manipulation of the spin orientation is still a missing part. Recently we focused on two approaches in order to tune the spin-orbit interaction (SOI) in a Ge-based platform. Both rely on the structural inversion asymmetry and the spin-orbit coupling at surfaces and interfaces with germanium (111). First, we performed the epitaxial growth of the topological insulator (TI) Bi2Se3 on Ge (111). After characterizing the structural and electrical properties of the Bi2Se3/Ge heterostructure, we developed an original method to probe the spin-to-charge conversion at the interface between Bi2Se3and Ge by taking advantage of the Ge optical properties. The results showed that the hybridization between the Ge and TI surface states could pave the way for implementing an efficient spin manipulation architecture.The latter approach is to exploit the intrinsic SOI of Ge (111). By investigating the electrical properties of a thin Ge(111) film epitaxially grown on Si(111), we found a large unidirectional Rashba magnetoresistance, which we ascribe to the interplay between the externally applied magnetic field and the current-induced pseudo-magnetic field in the spin-splitted subsurface states of Ge (111). The unusual strength and tunability of this UMR effect open the door towards spin manipulation with electric fields in an all-semiconductor technology platform.In a last step, I integrated perpendicularly magnetized (Co/Pt) multilayers-based magnetic tunnel junctions on the Ge (111) platform. I developed an original electro-optical hybrid technique to detect electrically the magnetic circular dichroism in (Co/Pt) and perform magnetic imagingThese MTJs were then used to perform spin injection and detection in a lateral spin valve device. The perpendicular magnetic anisotropy (PMA) allowed to generate spin currents with the spin oriented perpendicular to the sample plane.Finally, I assembled all these building blocks that were studied during my PhD work to build a prototypical spin transistor. The spin accumulation was generated either optically or electrically, using optical spin orientation in germanium or the injection from the magnetic tunnel junction
16
Araújo, Augusto de Lelis. "Investigação dos estados topologicamente protegidos em siliceno e germaneno." Universidade Federal de Uberlândia, 2014. https://repositorio.ufu.br/handle/123456789/15668.
Анотація:
The main objective of this work is to research and obtain surface protected topological states in nano-ribbons created from the leaves of Germanene and Silicene. These sheets belong to the class of Topological Insulators and correspond to monolayers of germanium and silicon atoms in a hexagonal arrangement that is similar to the graphene sheet. For this investigation, we conducted a study of the electronic and structural properties of these sheets, as well as their respective nano-ribbons through first-principles calculations based on density functional theory (DFT). In this methodology we use the generalized gradient approximation (GGA) for estimating the exchange and correlation term, and the PAW method for the effective potential and the expansion of plane waves of the Kohn-Sham. We conducted a computer simulation with the aid of the package VASP (Vienna ab-initio Simulation Package). As a starting point for our research, we used the methodology of solid state physics in order to describe the crystalline structure of the leaves as well as their mutual space. Subsequently we analyze the band structure, from which many of its properties can be visualized. For this task, we initially proceeded to investigate the stability of these systems via total energy calculations, in turn obtaining the network parameters that minimizes the energy of the system. We also obtained the energy cutoff, ECUT used in our calculations, or in other words, determining the number of plane waves needed to expand the electronic wave functions on the DFT formalism. We continued our study, with the creation and analysis of two different configurations of nano-ribbons, one that corresponds to a straightforward cut of the sheet with the armchair termination pattern, and the other based on a reconstruction of those edges, which provide an energetically more stable system. Subsequently we obtained electronic structures, and conducted a study of its variation due to the change of the width of the nano-ribbon and ionic relaxation of its edges. In a way, we modified the above parameters in order to obtain a system that would give us a zero gap, or at least insignificant, as well as a specific configuration for the spin texture, in order to verify the evidence of surface protected topological states in these nano-ribbons.O objetivo principal deste trabalho é a investigação e obtenção dos estados topologicamente protegidos de superfície em nano-fitas criadas a partir das folhas de Germaneno e Siliceno. Estas folhas pertencem a classe dos Isolantes Topológicos e correspondem a monocamadas de átomos de Germânio e Silício, em um arranjo hexagonal que se assemelha a folha do Grafeno. Para esta investigação, realizamos um estudo das propriedades eletrônicas e estruturais destas folhas, bem como de suas respectivas nano-fitas, através de cálculos de primeiros princípios fundamentados na teoria do funcional da densidade (DFT). Nesta metodologia utilizamos a aproximação do gradiente generalizado (GGA) para a estimativa do termo de troca e correlação, e o método PAW para o potencial efetivo e a expansão em ondas planas dos orbitais de Kohn-Sham. Realizamos a simulação computacional com o auxílio do pacote VASP (Vienna ab-initio Simulation Package). Como ponto de partida para nossa pesquisa, utilizamos a metodologia da física do estado sólido com o intuito de descrever a estrutura cristalina das folhas, bem como seu espaço recíproco. Posteriormente analisamos as estruturas de bandas, a partir das quais muitas de suas propriedades podem ser visualizadas. Para esta tarefa, inicialmente procedemos à investigação da estabilidade destes sistemas via cálculos de energia total, obtendo o parâmetro de rede a que minimiza a energia do sistema. Obtivemos também a energia de corte ECUT utilizada em nossos cálculos, ou em outras palavras, a determinação do número de ondas planas necessárias para expandir as funções de onda eletrônicas no formalismo da DFT. Prosseguimos nosso estudo, com a criação e análise de duas distintas configurações de nano-fitas, uma que corresponde a um corte simples e direto da folha com terminação no padrão armchair, e a outra baseada em uma reconstrução destas bordas, que acaba por fornecer um sistema mais estável energeticamente. Posteriormente obtivemos as estruturas eletrônicas, e realizamos um estudo de sua variação em função da alteração da largura da nano-fita e a relaxação iônica de suas bordas. De certa maneira, modificamos os parâmetros acima, de forma a obter um sistema que nos fornecesse um gap nulo, ou pelo menos desprezível, bem como uma determinada configuração para a textura de spin, de modo a verificarmos a evidência de uma proteção topológica nos estados de superfície nestas nano-fitas.
Mestre em Física
17
Tung, Po-I., and 董柏逸. "Nano-Structured Germanium-on-Insulator Technology." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/49084869511491213827.
18
Yu, John Han, and 余宗翰. "Growth and Characterization of Germanium Material on Insulator." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/39213117538667109575.
Анотація:
碩士國立臺灣大學
電子工程學研究所
96
Abstract In order to overcome the nonideal effects in electronics devices caused by the device scaling down, silicon-on-insulator (SOI) material is an ideal substrate for devices fabrication. Silicon (Si) and germanium (Ge) are both group-IV material, and Ge possesses higher electron and hole mobilities as well as better optical properties as compared to Si. To combine the advantages of SOI and Ge materials, the germanium -on-insulator (GOI) approach is one of the best solutions for substrate engineering. Traditional fabrication methods for GOI material, such as wafer bonding, Smart Cut, SIMOX, and Ge condensation, require either long process time or high cost. The liquid phase epitaxy (LPE) technique can solve these issues by utilizing the defect necking mechanism to obtain high-quality GOI. Patterned insulators are used to block the threading dislocation propagation originating from the re-crystallized Ge during the rapid thermal anneal (RTA) process. However, large-area GOI is difficult to be obtained by the LPE process, and the Ge crystal orientation might be twisted during the high temperature annealing process. The LPE method for Ge material fabrication on insulators is investigated in this thesis. Special Ge pattern structures, including the rib structure, growth from two-end seeding window, multi-width structure, defect-block structure, Ge growth-range- survey structure, coplanar symmetric structure and waveguide structure, are designed. The material characterization by the transmission electron microscopy (TEM) and surface morphology analysis by the atomic force microscopy (AFM) will also be discussed.
19
Lin, Chao-Ching, and 林朝清. "Selective Epitaxy of Germanium and Nanoscale Channel Structure Fabrication for Germanium on Insulator." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/08103235869019914104.
Анотація:
碩士國立臺灣大學
電子工程學研究所
99
As the CMOS device scales down, the high mobility devices and optical interconnects become the critical solutions to extend the system performance. Ge is an enabling material for these applications because of its high carrier mobility and strong optical absorption. In the first part of this thesis, the surface morphology and growth rate versus window size and growth temperature of Ge selective epitaxial growth are analyzed by SEM, AFM, TEM, and XRD. The average thickness and facets of grown Ge films are extensively characterized. At low temperature, the form of Ge is almost facet-free and Ge grows without loading effect. At high growth temperature, the facet {311} is observed clearly, and the loading effect appears. In the second part, a novel method to fabricate the nanoscale channel structure for GOI is introduced. In order to remove the nitride channel layer and avoid breaking the TEOS capping layer, H2SiF6 solution is used to enhance the selectivity between nitride and TEOS. Single-crystal Ge grown from the exposed Si seed in the nanoscale channel structure is confirmed by AFM and XRD. These investigations of Ge selective epitaxial growth and nanoscale channel fabrication can enable Ge on insulator materials for electronics and photonics applications.
20
Hsu, Cheng-Chang, and 徐正璋. "Thin Film Germanium-on-Insulator Photodetector and Performance Enhancement." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/00846099726297712709.
Анотація:
碩士國立臺灣大學
電子工程學研究所
95
Smart-Cut is a recently established, advanced technology for fabricating high-quality Germaniun-on-insulator (GOI) systems and has successfully applied to many devices. In this thesis, the thin film germanium layer is transferred successfully to another silicon wafer capped with about 50 nm thermal SiO2 by direct wafer bonding and hydrogen-induced layer transfer and formed the germanium-on-insulator (GOI) structure. The germanium-on-insulator can increase the responsivity and the speed of the MOS photodetector due to the large absorption in the infrared and high mobility of Ge, respectively. In this thesis, we choose the corning 7059 glass displacing Si to be the substrate for the fabrication of GOG photodetector in order to decrease the cost and be used for back incident application. The photogenerated electron-hole pairs may recombine via defects at the Ge/SiO2 interface and consequently etching the surface of germanium layer could decrease the dark current and increase the responsivity under the visible light exposure. In addition, the ohmic contact is exchanged from aluminum to indium-tin-oxide (ITO) to apply on the GOG substrate for back incident application. This germanium-on-ITO glass structure could be used for solar cell technology. Moreover, The smart-cut technology is also applied to germanium thin film transfer to flexible polyimide and integrating with existing microelectronic equipments and process technology of semiconductor factories Finally, the chemical bonds ‘‘Ge–CN bonds’’ are formed by a simple room temperature chemical method ‘‘crown-ether cyanide treatment’’ and they could authentically eliminate interface states at Ge/SiO2 interfaces.
21
Hsu, Cheng-Chang. "Thin Film Germanium-on-Insulator Photodetector and Performance Enhancement." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1707200715511100.
22
Huang, Ying-An, and 黃瀅安. "Thermo-Absorption Optical Modulators Based on Germanium-on-Insulator (GOI) Structure." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/69485735476605036498.
Анотація:
碩士國立臺灣大學
電子工程學研究所
96
The optical communication has advantages in high capacity, low transmission loss, and low interference, therefore it is one of the best communication methods and can significantly enhance the communication speed. The optic modulator is indispensable part in modern high-speed optical communication system. This thesis study is focused on the design, fabrication, and measurement of novel thermo-absorption optical modulators, which utilize lateral self-resistive-heating method to change the device temperature and modulate the light intensity passing through the device. The heating mode utilizes the difference of resistivity between semiconductor materials and metals, thus most of the voltage drop is applied on the semiconductor region to increase the temperature due to its higher resistance. The modulator devices are based on the germanium-on-insulator (GOI) structure. We also establish a process of GOI bonding technology at low temperature that can effectively control the germanium thickness and the surface uniformity. Comparing with other semiconductor materials, germanium has a steep optical absorption curve and therefore the curve can move fast with varying temperature; the use of germanium as the device material is also beneficial to the integration of silicon process technology and electro-optical system. Besides, a bottom metal reflector structure is used to induce cavity effect and to enhance effective light path as well as modulation effect. When the GOI thermo-absorption optical modulator is biased at 0.8V or 1.2V, the increasing temperature causes absorption curve shift. The modulation contrast reaches 8.71dB under the 1563nm wavelength. Therefore this study demonstrated that the thermo-absorption optical modulator is an effective device with low-operation-voltage and high contrast ratio and suitable for optical communication and interconnects.
23
Dong, Bo-Chang, and 董柏昌. "Nanotechnology for Germanium-on-Insulator Structures : Growth, Fabrication, and Material Analysis." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/28503425592013393613.
Анотація:
碩士國立臺灣大學
電子工程學研究所
96
Abstract Germanium (Ge) has become a widely used material in semiconductor fabrication process in recent years. Compared with the dominating semiconductor material－silicon－in today’s industry, germanium has numerous advantages such as higher carrier mobility, higher absorption coefficient, and good lattice match with GaAs. The germanium-on-insulator (GOI) on silicon substrate technology – a novel semiconductor substrate engineering – can further utilize the superior electrical and optical properties of Ge and also suppress its disadvantages such as high leakage and high cost. In this thesis, we study the SiGe thin film growth mechanism, GOI technology, as well as growth rate/composition characterization. Germanium on insulator fabricated by fully-encapsulated rapid thermal annealing is discussed with details of the original idea, fabrication process, and measurement results. Using this technique, nano-crystal germanium film on insulator can be obtained, and the surface characterization and material analysis are also discussed. Finally, we introduce a novel method to fabricate nano-scale-channel, and the fabricated structure is characterized by focused ion beam (FIB) and scanning-electron-microscopy (SEM). This investigation will enable the development of future high performance electrical and optical devices. Key words : Silicon-Germanium (SiGe), Germanium-on-Insulator (GOI), Fully-Encapsulated Rapid Thermal Annealing, Nano-Scale-Channel
24
Lin, Chung-Wei, and 林忠偉. "The Investigation of Polycrystalline Germanium on Insulator Based on SOI and Si Substrates." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/34838492259714620058.
Анотація:
碩士國立臺灣大學
電子工程學研究所
99
Traditional silicon technology is mature and widespread in application nowadays. Therefore, silicon is the main material in semiconductor industry. But by the limit of physics, silicon technology will finally face that it cannot reduce its scale in order to pursue high speed and low cost. Consequently, germanium as group IV as silicon is developed in this thesis. Its advantages are high mobility and larger absorption at communication wavelength than silicon. As a result, it can be combined with traditional silicon technology in order to develop more high-speed devices. In this thesis, we developed poly-germanium on insulator (GOI) by SOI and Si substrates using a low-cost liquid phase epitaxy (LPE) method. Its principle is to anneal Ge above its melting point, and cool it rapidly in order to achieve recrystallization. We have acquired 300-nm-thick and 100-nm-thick poly-GOI respectively by two different methods in this study. Their patterns were 5μm×5μm and 10μm×10μm square arrays. In addition, we have also acquired 300-nm-thick strip GOI. By the method, it is expected to be integrated to Si substrates for new devices, such as photodetectors. Therefore, this investigation is one of the important development trends for semiconductor industry.
25
Tsai, Ming-Tsun, and 蔡明村. "The Polycrystalline Germanium Film on Insulator by Liquid Phase Epitaxy on SOI Platform." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/85384588478234166271.
Анотація:
碩士國立臺灣大學
電子工程學研究所
99
In recent years, the germanium-on-insulator (GOI) technology has been developed to provide a good solution to overcome the physical limits of silicon. Several GOI material fabrication methods has been proposed and demonstrated, such as wafer bonding, zone melting, smart cut, Separation by Implantation Of Oxygen (SIMOX), condensation, epitaxial growth, and rapid melt growth. This thesis introduced a new poly-GOI technology, which could be achieved easily and was compatible with traditional silicon fabrication process. The liquid phase epitaxy (LPE) method was the key technique to the designed fabrication. LPE helped the as-deposited germanium re-crystallizing from amorphous into poly crystalline. The lateral surrounding silicon was the seed for re-crystallization. Several factors were changed and optimized to the better condition that the deposited germanium could successfully re-crystallize to poly-crystalline. The poly-GOI structure was successfully fabricated and the characteristic was good enough for the fabrication of photo detectors which was the goal could be challenged in the future.
26
Lee, Chien-Wei, and 李謙偉. "Fabrication and Characterization of Device of Spin Injection and Detection on Germanium on Insulator." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/61887182267536179768.
Анотація:
碩士國立交通大學
電子工程學系 電子研究所
103
In this thesis, we success in using Smart CutTM to fabricate high quality germanium thin film on insulator(GeOI) substrate. We use proton ion implantation following with direct bonding on the glass substrate. And use thermal annealing to cut the thin film from Ge substrate. Then we used four-terminal structure to fabricate the device of spin injection and detection. Using the four-terminal structure device with ferromagnetic metal-oxide- semiconductor structure to inject spin carriers and using Hanle effect to detect the spin signal. In this thesis, I will mention fabrication process parameters and the method of measurement. In the last part I will discuss the basic characterization of four-terminal device. In the end, we got the carrier mobility in germanium thin film by hall effect. The proposed structure can be simply measured the spin signal, therefore, it can be used to study the characteristics of spin polarized carriers in semiconductors. We success in measuring the Hanle effect signal and obtain higher Spin lifetime at room temperature (160 ps for N-type and 33 ps for P-type).
27
Yang, Yi-Chin, and 楊易瑾. "A Study on High Quality Metal-Insulator-Germanium Capacitor Using Al-based Interfacial Layer." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/18043910764962046049.
Анотація:
碩士國立交通大學
電子工程學系 電子研究所
103
In this thesis, the diffusion coefficients of Ge in AlN and Al2O3 were extracted. Both materials have ability to be diffusion barriers for avoiding Ge atoms diffusion from the substrate into gate dielectric in thermal process effectively. Then, germanium MOS capacitors using plasma oxidation method to form a thin GeOx interfacial layer by oxidizing Ge surface beneath an ALD AlN and Al2O3 layers were fabricated and analyzed electrically. The samples with oxygen plasma treatment exhibits lower interface state density than that of the samples without oxygen plasma treatment. And using AlN as interfacial layer can achieve lower leakage current and smaller hysteresis than that of using Al2O3, because AlN is a more effective barrier to against GeO volatilization and Ge diffusion. However, the interface state density of the AlN/Ge structure is poor. We also investigate the effect of proportion of nitrogen in AlN. The leakage current decreases with the increase of nitrogen concentration in the dielectric. Secondly, an AlN layer was capped on Al2O3 for utilizing the advantages of AlN and Al2O3. It is found that capping AlN on Al2O3 improves the hysteresis and leakage current while degrades the interface state density. We suspect that AlN might mix with Al2O3 to form AlON layer. Decreasing the AlN thickness can decrease the degradation of interface state density, but the hysteresis and leakage current will become worse. Finally, N2 and NH3 plasma treatments were applied on Al2O3 for improving the hysteresis and leakage current. Nevertheless, it is observed that NH3 plasma would reduce the germanium oxide and degrade the interface state density. On the other hand, N2 plasma treatment can improve hysteresis and leakage current without degrading the interface state density. Thus, HfO2/Al2O3/GeOx/Ge MIS structure with N2 plasma treatment is recommended to be the best condition to fabricate gate stack with ultra-thin EOT, small hysteresis, and low leakage current density. The capacitor with EOT about 0.53 nm has been achieved while keeping low leakage current (<4×〖10〗^(-2) A/cm^2), small hysteresis (~120 mV), and Dit as low as 3.13×〖10〗^12 (cm^(-2) eV^(-1)) at E- Ev = 0.2 eV after 450˚C PDA. Therefore, this thesis has achieved a gate stack with smaller hysteresis, and lower leakage current in comparison with previous studies with the same EOT. This achievement is expected to further improve the performance of Ge MOSFETs.
28
Heng, C. L., Wee Kiong Choi, Wai Kin Chim, L. W. Teo, Vincent Ho, W. W. Tjiu, and Dimitri A. Antoniadis. "Charge Storage Effect in a Trilayer Structure Comprising Germanium Nanocrystals." 2002. http://hdl.handle.net/1721.1/3969.
Анотація:
A metal-insulator-semiconductor (MIS) device with a trilayer insulator structure consisting of sputtered SiO₂ (~50nm)/evaporated pure germanium (Ge) layer (2.4nm)/rapid thermal oxide (~5nm) was fabricated on a p-type Si substrate. The MIS device was rapid thermal annealed at 1000°C. Capacitance-voltage (C-V) measurements showed that, after rapid thermal annealing at 1000°C for 300s in Ar, the trilayer device exhibited charge storage property. The charge storage effect was not observed in a device with a bilayer structure without the Ge middle layer. With increasing rapid thermal annealing time from 0 to 400s, the width of the C-V hysteresis of the trilayer device increased significantly from 1.5V to ~11V, indicating that the charge storage capability was enhanced with increasing annealing time. High-resolution transmission electron microscopy results confirmed that with increasing annealing time, the 2.4nm amorphous middle Ge layer crystallized gradually. More Ge nanocrystals were formed and the crystallinity of the Ge layer improved as the annealing time was increased. When the measurement temperature was increased from –50°C to 150°C, the width of the hysteresis of the MIS device reduced from ~10V to ~6V. This means that the charge storage capability of the trilayer structure decreases with increasing measurement temperature. This is due to the fact that the leakage current in the trilayer structure increases with increasing measurement temperature.Singapore-MIT Alliance (SMA)
29
Teo, L. W., Van Tai Ho, M. S. Tay, Y. Lei, Wee Kiong Choi, Wai Kin Chim, Dimitri A. Antoniadis, and Eugene A. Fitzgerald. "Charge Storage Mechanism and Size Control of Germanium Nanocrystals in a Tri-layer Insulator Structure of a MIS Memory Device." 2003. http://hdl.handle.net/1721.1/3712.
Анотація:
A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.Singapore-MIT Alliance (SMA)
30
Hsieh, Hsin-Yuan, and 謝欣原. "Modeling and Investigation of Short-Channel Effects for Ultra-Thin-Body Germanium-On-Insulator MOSFETs Considering Quantum Confinement." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/5pqgtc.
Анотація:
碩士國立交通大學
電子研究所
99
Germanium as a channel material has been proposed to enable mobility scaling. However, its high permittivity makes it very susceptible to short-channel effects (SCEs). To improve the electrostatic integrity, ultra-thin-body (UTB) germanium-on-insulator (GeOI) MOSFET with thin buried oxide has been proposed as a promising device architecture to continue CMOS scaling. In this thesis, we theoretically investigate the impact of quantum-mechanical effects on the threshold-voltage ( ) roll-off in UTB GeOI MOSFETs. To obtain , we have analytically solved the Schrödinger equation and derived a quantum-confinement model based on a parabolic form of channel potential. This parabolic channel potential is simplified from the series solution of Poisson’s equation and has the correct dependence of channel length. Therefore, our quantum-confinement model can be used to examine the SCEs for UTB GeOI devices. Our study indicates that for extremely-scaled UTB GeOI devices, roll-off can be suppressed by quantum confinement.
31
Teo, L. W., Van Tai Ho, M. S. Tay, Wee Kiong Choi, Wai Kin Chim, Dimitri A. Antoniadis, and Eugene A. Fitzgerald. "Dependence of nanocrystal formation and charge storage/retention performance of a tri-layer memory structure on germanium concentration and tunnel oxide thickness." 2003. http://hdl.handle.net/1721.1/3799.
Анотація:
The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer.Singapore-MIT Alliance (SMA)
32
Shamin, Saquib. "Electrical Transport in Si:P and Ge:P δ-doped Systems". Thesis, 2015. http://etd.iisc.ernet.in/2005/3915.
Анотація:
Doped semiconductor systems have for decades provided an excellent platform to study novel concepts in solid state physics such as quantum hall effect, metal-to-insulator transition (MIT), weak localization and many body interaction effects. Doped Si, in particular and doped Ge has been studied extensively to study MIT as a function of dopant concentration or uniaxial stress. Spin transport phenomena have also been probed in bulk doped Si. All the previous studies involved bulk doped semiconductors where the dopants are spread through the bulk of the material. However spatial confinement of dopants in one or more dimensions may lead to a range of exotic quantum phenomena such as an absence of Anderson localization in one and two dimensions, hole-mediated (Nagaoka) ferromagnetism and new modes of quantum transport, when the Fermi energy lies at or close to centre of the band. Since many of these phenomena are inherent to lower dimensions, it has been hard to observe these experimentally in bulk doped crystals of Si and Ge. Recent advances in the monolayer doping techniques with atoms that closely pack on a surface, has made it possible to design a new class of 2D electron systems (2DES) in elemental semiconductors, such as Si and Ge, where the dopant (P) atoms are confined within a few atomic planes. The uniqueness of these systems lies not merely in the planar doping profile in bulk semiconductors that allow versatile designs of nanodevices, such as 1D wires, tunnel gaps and quantum dots, but also that it is now possible to study the interplay of wavefunction overlap and commensurability effects in 2D with unprecedented control. From an application perspective as well these systems are technologically important as they are aimed at being the building blocks of a solid state quantum computer. This thesis deals with investigating the electrical transport properties, both average (resistance) and dynamic (noise) of doped semiconductor systems in 2D delta layers, 1D wires and 0D quantum dots.
We find that the 2D δ-layers shows suppressed low frequency noise and the Hooge parameter of delta doped Si is about five to six orders of magnitude lower when compared to bulk doped Si in metallic regime. At low temperatures, the noise arises in these systems due to universal conductance fluctuations. For 1D wires as well we find that the Hooge parameter is one of the lowest among various 1D systems including carbon
nanotubes. We identify that charge traps in the Si/SiO2 are responsible for causing noise in δ-doped systems. Then we study the noise and transport in 2D delta layers as a function of doping density (and hence carrier density and interaction). Weak localization corrections to the conductivity and the universal conductance fluctuations were both found to decrease rapidly with decreasing doping in the Si:P and Ge:P delta layers, suggesting a spontaneous breaking of time reversal symmetry driven by strong Coulomb interactions. At low doping density we observe metal-like dependence of resistance on temperature at low temperatures, raising the possibility of a metallic ground state in 2D at 0 K in doped semiconductors. Finally we probe the low density devices (with broken time reversal symmetry) using superconducting Al as ohmic contacts. Anomalous increase in resistance below the superconducting transition temperature of Al and magnetoresistance with a sharp peak at 0 T is observed. Additionally we find that when the Al is superconducting, there exists a non-local resistance in low doped devices.
33
Zhang, Yan. "Hole mobility in strained germanium and vanadium-III p-channel inversion layers with self-consistent valence subband structure and high-k insulators." 2010. https://scholarworks.umass.edu/dissertations/AAI3427580.
Анотація:
We present a comprehensive investigation of the low-field hole mobility in strained Ge and III-V (GaAs, GaSb, InSb and In1− xGaxAs) p-channel inversion layers with both SiO2 and high-κ insulators. The valence (sub)band structure of Ge and III-V channels, relaxed and under strain (tensile and compressive) is calculated using an efficient self-consistent method based on the six-band k · p perturbation theory. The hole mobility is then computed using the Kubo-Greenwood formalism accounting for non-polar hole-phonon scattering (acoustic and optical), surface roughness scattering, polar phonon scattering (III-Vs only), alloy scattering (alloys only) and remote phonon scattering, accounting for multi-subband dielectric screening. As expected, we find that Ge and III-V semiconductors exhibit a mobility significantly larger than the “universal” Si mobility. This is true for MOS systems with either SiO2 or high-κ insulators, although the latter ones are found to degrade the hole mobility compared to SiO2 due to scattering with interfacial optical phonons. In addition, III-Vs are more sensitive to the interfacial optical phonons than Ge due to the existence of the substrate polar phonons. Strain—especially biaxial tensile stress for Ge and biaxial compressive stress for III-Vs (except for GaAs)—is found to have a significant beneficial effect with both SiO2 and HfO2. Among strained p-channels, we find a large enhancement (up to a factor of 10 with respect to Si) of the mobility in the case of uniaxial compressive stress added on a Ge p-channel similarly to the well-known case of Si. InSb exhibits the largest mobility enhancement. In0.7Ga 0.3As also exhibits an increased hole mobility compared to Si, although the enhancement is not as large. Finally, our theoretical results are favorably compared with available experimental data for a relaxed Ge p-channel with a HfO2 insulator.