Готові списки джерел за темами / Heterogeneous Architecture Design

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Автор: Grafiati
Опубліковано: 22 червня 2023

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  4. Частини книг
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Статті в журналах з теми "Heterogeneous Architecture Design":

1

LIU, SHAOSHAN, WON W. RO, CHEN LIU, ALFREDO CRISTOBAL-SALAS, CHRISTOPHE CÉRIN, JIAN-JUN HAN, and JEAN-LUC GAUDIOT. "INTRODUCING THE EXTREMELY HETEROGENEOUS ARCHITECTURE." Journal of Interconnection Networks 13, no. 03n04 (September 2012): 1250010. http://dx.doi.org/10.1142/s0219265912500107.

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The computer industry is moving towards two extremes: extremely high-performance high-throughput cloud computing, and low-power mobile computing. Cloud computing, while providing high performance, is very costly. Google and Microsoft Bing spend billions of dollars each year to maintain their server farms, mainly due to the high power bills. On the other hand, mobile computing is under a very tight energy budget, but yet the end users demand ever increasing performance on these devices. This trend indicates that conventional architectures are not able to deliver high-performance and low power consumption at the same time, and we need a new architecture model to address the needs of both extremes. In this paper, we thus introduce our Extremely Heterogeneous Architecture (EHA) project: EHA is a novel architecture that incorporates both general-purpose and specialized cores on the same chip. The general-purpose cores take care of generic control and computation. On the other hand, the specialized cores, including GPU, hard accelerators (ASIC accelerators), and soft accelerators (FPGAs), are designed for accelerating frequently used or heavy weight applications. When acceleration is not needed, the specialized cores are turned off to reduce power consumption. We demonstrate that EHA is able to improve performance through acceleration, and at the same time reduce power consumption. Since EHA is a heterogeneous architecture, it is suitable for accelerating heterogeneous workloads on the same chip. For example, data centers and clouds provide many services, including media streaming, searching, indexing, scientific computations. The ultimate goal of the EHA project is two-fold: first, to design a chip that is able to run different cloud services on it, and through this design, we would be able to greatly reduce the cost, both recurring and non-recurring, of data centers\clouds; second, to design a light-weight EHA that runs on mobile devices, providing end users with improved experience even under tight battery budget constraints.
2

Ahsan, AMM, Ruinan Xie, and Bashir Khoda. "Heterogeneous topology design and voxel-based bio-printing." Rapid Prototyping Journal 24, no. 7 (October 8, 2018): 1142–54. http://dx.doi.org/10.1108/rpj-05-2017-0076.

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Purpose The purpose of this paper is to present a topology-based tissue scaffold design methodology to accurately represent the heterogeneous internal architecture of tissues/organs. Design/methodology/approach An image analysis technique is used that digitizes the topology information contained in medical images of tissues/organs. A weighted topology reconstruction algorithm is implemented to represent the heterogeneity with parametric functions. The parametric functions are then used to map the spatial material distribution following voxelization. The generated chronological information yields hierarchical tool-path points which are directly transferred to the three-dimensional (3D) bio-printer through a proposed generic platform called Application Program Interface (API). This seamless data corridor between design (virtual) and fabrication (physical) ensures the manufacturability of personalized heterogeneous porous scaffold structure without any CAD/STL file. Findings The proposed methodology is implemented to verify the effectiveness of the approach and the designed example structures are bio-fabricated with a deposition-based bio-additive manufacturing system. The designed and fabricated heterogeneous structures are evaluated which shows conforming porosity distribution compared to uniform method. Originality/value In bio-fabrication process, the generated bio-models with boundary representation (B-rep) or surface tessellation (mesh) do not capture the internal architectural information. This paper provides a design methodology for scaffold structure mimicking the native tissue/organ architecture and direct fabricating the structure without reconstructing the CAD model. Therefore, designing and direct bio-printing the heterogeneous topology of tissue scaffolds from medical images minimize the disparity between the internal architecture of target tissue and its scaffold.
3

Sek Meng Chai, T. M. Taha, D. S. Wills, and J. D. Meindl. "Heterogeneous architecture models for interconnect-motivated system design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 6 (December 2000): 660–70. http://dx.doi.org/10.1109/92.902260.

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4

Yang, Chungang, Jiandong Li, and Alagan Anpalagan. "Energy Efficiency Architecture Design for Heterogeneous Cellular Networks." Wireless Communications and Mobile Computing 16, no. 12 (September 15, 2015): 1588–602. http://dx.doi.org/10.1002/wcm.2635.

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5

Kovalyov, S. P. "Design of Heterogeneous Cyber-Physical Systems Employing Category Theory." Mekhatronika, Avtomatizatsiya, Upravlenie 23, no. 2 (February 6, 2022): 59–67. http://dx.doi.org/10.17587/mau.23.59-67.

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Heterogeneous cyber-physical control systems based on digital twins are in demand by Industry 4.0. In accordance with the contemporary systems engineering methodology, such systems are designed at the level of digital models. The paper proposes approaches to formalization and subsequent automation of solving direct and inverse problems of their design. To unify descriptions of heterogeneous components, we follow a viewpoint-based approach to architecture design recommended by the international standard ISO/IEC/IEEE 42010. Following recent trends, we employ category theory as a mathematical framework for the formal description and solution of design problems. Indeed, category theory is a branch of higher algebra specifically aimed at a unified representation of objects of different nature and relationships between them. The design space of a heterogeneous cyber-physical system is constructed as a subcategory of the multicomma category, the objects of which describe possible system architectures with a fixed structural hierarchy represented from a certain viewpoint as diagrams, and morphisms denote actions associated with the parts selection and replacement during the system design. Direct design problems consist in evaluating the properties of the system as a whole by its architecture and are solved using a universal category-theoretic construction of the colimit of the diagram. The solution of inverse problems that require finding variants of the system architecture, which are (sub-, Pareto-) optimal according to the consumer quality criteria, consists in reconstructing diagrams by their colimit edges. For such reconstruction, optimization algorithms of gradient descent type are reasonable to employ, which navigate along the system design space morphisms calculating the path by means of computer algebra. Typical techniques of assembling cyber-physical systems, such as modular composition and aspect weaving, are described in the language of category theory and illustrated. As an example, we outline the design of energy-efficient robotic production lines represented from the behavior viewpoint as discrete-event simulation models.
6

AGYEMAN, MICHAEL O., ALI AHMADINIA, and ALIREZA SHAHRABI. "HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350016. http://dx.doi.org/10.1142/s0218126613500163.

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.
7

Pasha, Muhammad Adeel, Umer Farooq, and Bilal Siddiqui. "A framework for high-level simulation and optimization of fine-grained reconfigurable architectures." SIMULATION 95, no. 8 (September 10, 2018): 737–51. http://dx.doi.org/10.1177/0037549718796272.

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Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.
8

Son, Hyun-Seung, Woo-Yeol Kim, and R. Young-Chul Kim. "MDA(Model Driven Architecture) based Design for Multitasking of Heterogeneous Embedded System." KIPS Transactions:PartD 15D, no. 3 (June 30, 2008): 355–60. http://dx.doi.org/10.3745/kipstd.2008.15-d.3.355.

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9

He, Tao, Hua Zhong Li, Tang Ren Dan, De Fen Zhang, Jun Qiang Liu, and Guo Rong Qin. "Design and Analysis of Test Model under Heterogeneous and Internet-Ware." Applied Mechanics and Materials 687-691 (November 2014): 2635–39. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2635.

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Studying a method based on UML model software architecture performance prediction: this method chosen software architecture design in UML, use case diagram, activity diagram and component diagram, and pull stereotypes and tagged values in it, and enlarge them to be UML SPT model, and then turn UML SPT model into queuing network model through conversion algorithm, this algorithm can deal with UML model activity diagram which included branch node and confluent nodes. Finally, using frequency domain analysis theory to get queuing network model, to know performance parameters and performance bottlenecks and also introduce the design plan of UML software architecture performance automation tools, and give a example of performance prediction software architecture.
10

Fang, Wei. "Design of Heterogeneous Data Exchange Technology for Teaching Resources Based on ICMPv6." International Journal of Emerging Technologies in Learning (iJET) 13, no. 11 (November 9, 2018): 78. http://dx.doi.org/10.3991/ijet.v13i11.9600.

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To promote the innovation of teaching resources and heterogeneous data exchange platform technologies and theories, heterogeneous data exchange platforms based on ICMPv6 teaching resources were studied. First, based on ICMPv6, the middle-tier architecture of the heterogeneous data exchange platform for teaching resources was studied. Second, the application layer architecture in the heterogeneous data exchange platform system of educational resources was studied. The middle layer and application layer were designed and implemented. Finally, the system was applied to the education platform to reflect its performance. The results showed that the ICMPv6 system could solve data exchange and data sharing systems between schools and homes. Contributions were made in solving interactive education between home and school. To sum up, it is feasible to use ICMPv6 on heterogeneous educational resources exchange platform.
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Статті в журналах Дисертації

Дисертації з теми "Heterogeneous Architecture Design":

1

Pessolano, Francesco. "Heterogeneous clustered processors : organization and design." Thesis, London South Bank University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.325819.

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2

Cong, Minh Thanh. "Hardware accelerated simulation and automatic design of heterogeneous architecture." Electronic Thesis or Diss., Université de Rennes (2023-....), 2023. https://ged.univ-rennes1.fr/nuxeo/site/esupversions/1ae038b9-380e-4e42-bcd4-fa3a28cb34b0.

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La conception de plates-formes de système sur puce hétérogènes est complexe avec de nombreuses combinaisons possibles. La simulation détaillée de différentes solutions est nécessaire pour déterminer le meilleur design. Les environnements de simulation existants (tels que gem5) sont limités car purement logiciels et ne prennent pas en compte les architectures hétérogènes. Pour pallier ces limitations, l'utilisation de composants reprogrammables FPGA pour accélérer la simulation est motivée. Notre travail est divisé en deux parties. La première partie est d'ordre expérimental et a étudié une approche de conception d'architectures hétérogènes en se concentrant sur la simulation de modèles de performance de composants de l'architecture (accélérateurs matériels et cœurs de processeurs) sur FPGA. La seconde partie est méthodologique et concerne un flot pour déterminer la meilleure microarchitecture en termes de rapport performance/consommation d'énergie. Ce flot combine un simulateur logiciel d'architecture et une méthode d'optimisation d'hyperparamètres pour trouver la meilleure combinaison de parallélisme, stratégies de déroulage de boucles et interfaces de mémoire. Les expérimentations ont été menées sur différents problèmes pour déterminer les solutions les plus optimales en termes d'efficacité énergétique
The design of heterogeneous system-on-chip platforms is complex with many possible combinations. Detailed simulation of different solutions is necessary to determine the best design. Existing simulation environments (such as gem5) are limited as they are purely software based and do not take into account heterogeneous architectures. To address these limitations, the use of reprogrammable FPGA components to accelerate simulation is motivated. Our work is divided into two parts. The first part is experimental and studied an approach to design heterogeneous architectures focusing on simulating performance models of architecture components (hardware accelerators and processor cores) on FPGA. The second part is methodological and concerns a flow to determine the best microarchitecture in terms of performance to energy consumption ratio. This flow combines a software architecture simulator and a hyperparameter optimization method to find the best combination of parallelism, loop unrolling strategies, and memory interfaces. Experiments were conducted on different problems to determine the most optimal solutions in terms of energy efficiency
3

Schultek, Brian Robert. "Design and Implementation of the Heterogeneous Computing Device Management Architecture." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1417801414.

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4

Huang, Zhe. "Design of heterogeneous P2P video-on-demand systems /." View abstract or full-text, 2008. http://library.ust.hk/cgi/db/thesis.pl?ECED%202008%20HUANG.

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5

McClure, Bruce Davis. "Design of an adaptive computing architecture for managing interactions in heterogeneous defence networks /." [St. Lucia, Qld.], 2002. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17146.pdf.

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6

Keir, Paul. "Design and implementation of an array language for computational science on a heterogeneous multicore architecture." Thesis, University of Glasgow, 2012. http://theses.gla.ac.uk/3645/.

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The packing of multiple processor cores onto a single chip has become a mainstream solution to fundamental physical issues relating to the microscopic scales employed in the manufacture of semiconductor components. Multicore architectures provide lower clock speeds per core, while aggregate floating-point capability continues to increase. Heterogeneous multicore chips, such as the Cell Broadband Engine (CBE) and modern graphics chips, also address the related issue of an increasing mismatch between high processor speeds, and huge latency to main memory. Such chips tackle this memory wall by the provision of addressable caches; increased bandwidth to main memory; and fast thread context switching. An associated cost is often reduced functionality of the individual accelerator cores; and the increased complexity involved in their programming. This dissertation investigates the application of a programming language supporting the first-class use of arrays; and capable of automatically parallelising array expressions; to the heterogeneous multicore domain of the CBE, as found in the Sony PlayStation 3 (PS3). The language is a pre-existing and well-documented proper subset of Fortran, known as the ‘F’ programming language. A bespoke compiler, referred to as E , is developed to support this aim, and written in the Haskell programming language. The output of the compiler is in an extended C++ dialect known as Offload C++, which targets the PS3. A significant feature of this language is its use of multiple, statically typed, address spaces. By focusing on generic, polymorphic interfaces for both the generated and hand constructed code, a number of interesting design patterns relating to the memory locality are introduced. A suite of medium-sized (100-700 lines), real-world benchmark programs are used to evaluate the performance, correctness, and scalability of the compiler technology. Absolute speedup values, well in excess of one, are observed for all of the programs. The work ultimately demonstrates that an array language can significantly reduce the effort expended to utilise a parallel heterogeneous multicore architecture, while retaining high performance. A substantial, related advantage in using standard ‘F’ is that any Fortran compiler can create debuggable, and competitively performing serial programs.
7

Okuya, Yujiro. "CAD Modification Techniques for Design Reviews on Heterogeneous Interactive Systems." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLS450.

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Les revues de design industriel bénéficient des nouvelles technologies interactives pour devenir plus réalistes, immersives et collaboratives. Toutefois, la modification des données de conception (CAO) est toujours effectuées depuis un espace de travail traditionnel par des ingénieurs qualifiés. Des problèmes de communication entre les différents experts peuvent apparaitre lors des réunions de revue de projet et engendrer des erreurs d’interprétation des modifications. J’estime que les processus actuels de révision de la conception impliquant itérativement des discussions sur la conception et un ajustement des modèles 3d devraient fusionner. Cela pourrait réduire le nombre d’itérations de correction sur les modèles durant le cycle de développement en facilitant lesdiscussions et en permettant à des utilisateurs non spécialistes CAO de modifier les données. Dans cette thèse, j’ai commencé par interviewer des ingénieurs de l‘industrie et j’ai esquissé un scénario de revue de conception dans lequel tous les membres d’un même projet peuvent générer et comparer plusieurs alternatives de conception depuis des systèmes interactifs adaptés pour répondre aux besoins de leurs différents expertises. J’ai d’abord conçu un système de couplage entre un environnement interactif temps réel et des données de CAO (RV-CAO) capable de modifier et de mettre à jour au format CAO natif. J’ai ensuite proposé des techniques d’interaction pour permettre à des utilisateurs non experts en CAO de modifier les données CAO paramétriques en utilisant des systèmes depuis un système CAVE et un mur d’image. Pour le système CAVE, j’ai créé ShapeGuide, une métaphore d’interaction basée forme permettant aux utilisateurs de générer et de choisir parmi des alternatives de conception en agissant indirectement sur les valeurs des paramètres d’un modèle CAO. J’ai étudié comment ShapeGuide peut affecter la qualité d’une tâche de modification de données CAO par rapport à un réglage de valeur de paramètre basée sur un défilement unidimensionnel. Les résultats ont montré que ShapeGuide permettait une modification plus rapide, plus efficace et préférée par les utilisateurs. Pour l’interaction depuis un mur d’images, j’ai créé ShapeCompare, qui permet à plusieurs utilisateurs de générer et de comparer plusieurs alternatives de design. J’ai étudié comment ShapeCompare affecte la collaboration entre experts par rapport à une technique de visualisation adaptée aux écrans standard. Les résultats ont montré qu’avec ShapeCompare, des paires de participants effectuaient plus rapidement une tâche de résolution de contraintes multiples et utilisaient plus d’instructions déictiques. Les résultats présentés décrivent des propositions de nouvelles pratiques de révision de conception, se basant sur l’utilisation d’interactions immersives et de murs d’images, qui permettent la modification directe des données de conception d’origine par tous les membres du projet quelle que soit leur expertise en CAO
Industrial design reviews benefit from emerging interactive technologies to become more Realistic, Immersive and Collaborative. However, the modification of design data is still managed in traditional workspace–Computer-Aided Design (CAD) systems on a workstation. As only engineers can apply modifications in such a workspace after the design review meeting, miscommunication between various experts could occur, resulting in unnecessary iterations. I argue that current processes of design reviews–design discussion and design adjustment– should merge. It could reduce the iterations, facilitate discussions and empower non-CAD experts to modify CAD data. In this dissertation, I started by interviewing engineers at an automotive industry and drew a new design review scenario in which project members can generate and compare several design alternatives in heterogeneous systems that can support needs from various experts. Based on the scenario, I firstly designed a VR-CAD system that can update the native format of CAD data in highly configurable interactive systems. I then explored interaction techniques for non-CAD experts to modify parametric CAD data with 3D and 2D interactive systems: a CAVE system and a wall-sized display. For the CAVE system, I created ShapeGuide, which allows users to generate and switch design alternatives of CAD data with a shape-based 3D interaction. I investigated how ShapeGuide affects a CAD data modification task compared to a standard one-dimensional scroll for parameter manipulation. Results showed that ShapeGuide was faster, more efficient and preferred by the users than the scroll technique. For the wall-sized display, I created ShapeCompare, which allows users to generate and distribute multiple design alternatives of CAD data using touch interaction. I investigated how ShapeCompare affects the collaboration among experts compared to a visualization technique suitable for standard screens. Results showed that pairs of participants performed a constraint solving task faster and used more deictic instructions with Shape- Compare. The presented findings for new design review practices using immersive systems and a wallsized display, allowing direct modification of the original CAD data by all project members regardless of their CAD expertise
8

Beu, Jesse Garrett. "Design of heterogeneous coherence hierarchies using manager-client pairing." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47710.

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Over the past ten years, the architecture community has witnessed the end of single-threaded performance scaling and a subsequent shift in focus toward multicore and manycore processing. While this is an exciting time for architects, with many new opportunities and design spaces to explore, this brings with it some new challenges. One area that is especially impacted is the memory subsystem. Specifically, the design, verification, and evaluation of cache coherence protocols becomes very challenging as cores become more numerous and more diverse. This dissertation examines these issues and presents Manager-Client Pairing as a solution to the challenges facing next-generation coherence protocol design. By defining a standardized coherence communication interface and permissions checking algorithm, Manager-Client Pairing enables coherence hierarchies to be constructed and evaluated quickly without the high design-cost previously associated with hierarchical composition. Further, Manager-Client Pairing also allows for verification composition, even in the presence of protocol heterogeneity. As a result, this rapid development of diverse protocols is ensured to be bug-free, enabling architects to focus on performance optimization, rather than debugging and correctness concerns, while comparing diverse coherence configurations for use in future heterogeneous systems.
9

Somers, Marc Steven. "Impact of Webpage Access on the Design of Single-Chip Heterogeneous Multiprocessors." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/32107.

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Mobile devices are currently designed similar to embedded systems where performance is derived from a specification that allows the device to interact in a periodic manner with the environment. However, as mobile devices increasingly interact with the Internet they exhibit a different style of computing that does not fit the embedded system model. At the same time, a mobile device designer needs to consider many different issues such as the number and types of processors, scheduling strategies, applications, power consumption, and dimensions of the device, which increase the total number of design decisions at an alarming rate. This research shows that by using a more realistic model of mobile devices using webpage-based benchmarks, customization can allow specialized architectures to improve performance up to 70 percent over a homogeneous multiprocessor composed of general purpose processors and 25 percent additional improvement over the next best architecture when individual user preferences were also considered. Webpage access, to include user profiling for individual utilization, is clearly a significant factor in the design of mobile devices â and thus should be included in future benchmarks based upon webpage content and webpage access patterns. When new evaluation techniques are developed, new design strategies can be discovered and employed.
Master of Science
10

Botero, Oscar. "Heterogeneous RFID framework design, analysis and evaluation." Phd thesis, Institut National des Télécommunications, 2012. http://tel.archives-ouvertes.fr/tel-00714120.

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The Internet of Things paradigm establishes interaction and communication with a huge amount of actors. The concept is not a new-from-scratch one; actually, it combines a vast number of technologies and protocols and surely adaptations of pre-existing elements to offer new services and applications. One of the key technologies of the Internet of Things is the Radio Frequency Identification just abbreviated RFID. This technology proposes a set of solutions that allow tracking and tracing persons, animals and practically any item wirelessly. Considering the Internet of Things concept, multiple technologies need to be linked in order to provide interactions that lead to the implementation of services and applications. The challenge is that these technologies are not necessarily compatible and designed to work with other technologies. Within this context, the main objective of this thesis is to design a heterogeneous framework that will permit the interaction of diverse devices such as RFID, sensors and actuators in order to provide new applications and services. For this purpose in this work, our first contribution is the design and analysis of an integration architecture for heterogeneous devices. In the second contribution, we propose an evaluation model for RFID topologies and an optimization tool that assists in the RFID network planning process. Finally, in our last contribution, we implemented a simplified version of the framework by using embedded hardware and performance metrics are provided as well as the detailed configuration of the test platform
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Книги з теми "Heterogeneous Architecture Design":

1

Rutten, Martijn Johan. Eclipse: Flexible media processing in a heterogeneous multiprocessor template. [Amsterdam]: Vossiuspers UvA, 2007.

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2

Usländer, Thomas. Heterogeneous missions accessibility: Design methodology, architecture and use of geospatial standards for the ground segment support of earth observation missions. Noordwijk: ESA Communications, 2012.

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3

Nicolescu, Gabriela. Design Technology for Heterogeneous Embedded Systems. Dordrecht: Springer Science+Business Media B.V., 2012.

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4

Bertels, Koen. Hardware/software co-design for heterogeneous multi-core platforms: The hArtes toolchain. Dordrecht: Springer, 2012.

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(Editor), Michael Hensel, and Achim Menges (Editor), eds. Morph-Ecologies: Towards Heterogeneous Space In Architecture Design. AA Publications, 2007.

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Piguet, Christian, Ian O'Connor, and Gabriela Nicolescu. Design Technology for Heterogeneous Embedded Systems. Springer, 2011.

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Piguet, Christian, Ian O'Connor, and Gabriela Nicolescu. Design Technology for Heterogeneous Embedded Systems. Springer, 2014.

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Treebased Heterogeneous Fpga Architectures Application Specific Exploration And Optimization. Springer, 2012.

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Bertels, Koen. Hardware/Software Co-Design for Heterogeneous Multi-core Platforms: The HArtes Toolchain. Springer London, Limited, 2012.

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Bertels, Koen. Hardware/Software Co-Design for Heterogeneous Multi-Core Platforms: The HArtes Toolchain. Springer Netherlands, 2014.

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Частини книг з теми "Heterogeneous Architecture Design":

1

Guo, Jianjun, Kui Dai, and Zhiying Wang. "A High Performance Heterogeneous Architecture and Its Optimization Design." In High Performance Computing and Communications, 300–309. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847366_31.

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Wang, Haitao, and Lihua Song. "Architecture Design and Implementation Methods of Heterogeneous Emergency Communication Network." In Advanced Research on Electronic Commerce, Web Application, and Communication, 122–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-20367-1_20.

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Wu, Qiang, Jinian Bian, and Hongxi Xue. "A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design." In Embedded Software and Systems, 150–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11535409_21.

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Wang, Si-Yuan Rylan. "Soft Pneumatic Robotic Architectural System: Prefabricated Inflatable Module-Based Cybernetic Adaptive Space Model Manipulated Through Human-System Interaction." In Computational Design and Robotic Fabrication, 453–65. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-8637-6_39.

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AbstractIn this paper, a cybernetic adaptive space model based on prefabricated inflatable modules and physical interaction manipulation is introduced. The research aimed to redefine an intelligent and organic trend of residing and working by providing an adjustable and performative space system. The conjunction of human-space interaction, as well as the soft and hard architectural elements adaptive to dynamic living modalities and environmental conditions, are included in the methodology. The datasets based on the human body posture are collected through IMU sensors to provide coding inputs for defining modular inflatable structures, which anticipate generating heterogeneous morphological variations apt for flexible scenarios. The elaborated pre-fabricated samples successfully conform to the expected inflating behavior through silicone patterns. The results demonstrated the possibility of future architecture as an unrestrained configuration. Integrating the shape-shifting space within modular manufacturing and interactive technology can deprive the performance of many constraints. It can render a responsive ecosystem through a behavioral transformation of the in-habitants.
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Jin, Yunye, and Hwee Pink Tan. "UNISENSE: A Unified and Sustainable Sensing and Transport Architecture for Large Scale and Heterogeneous Sensor Networks." In Complex Systems Design & Management Asia, 15–26. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-12544-2_2.

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Kriebel, Florian, Faiq Khalid, Bharath Srinivas Prabakaran, Semeen Rehman, and Muhammad Shafique. "Fault-Tolerant Computing with Heterogeneous Hardening Modes." In Dependable Embedded Systems, 161–80. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_7.

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AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).
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Chinazzo, André, Christian De Schryver, Katharina Zweig, and Norbert Wehn. "A Custom Hardware Architecture for the Link Assessment Problem." In Lecture Notes in Computer Science, 57–75. Cham: Springer Nature Switzerland, 2022. http://dx.doi.org/10.1007/978-3-031-21534-6_4.

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AbstractHeterogeneous accelerator enhanced computing architectures are a common solution in embedded computing, mainly due to the constraints in energy and power efficiency. Such accelerator enhanced systems dispatch data- and computing-intensive tasks to specialized, optimized and thus efficient hardware units, leaving most control flow tasks for the more generic but less efficient central processing units (CPUs). Nowadays, also high-performance computing (HPC) systems are becoming more heterogeneous by incorporating accelerators into the computing nodes.In this chapter, we introduce the concept of heterogeneous computing and present the design of a hardware accelerator for solving the Link Assessment (LA) problem, in introduced Chapter 3. The hardware accelerator integrates its main dedicated processing units with a customized cache design and light-weight data path. We provide detailed area, energy, and timing results for a 28 nm application specific integrated circuit (ASIC) process and DDR3 memory devices. Compared to an CPU-based cluster, our proposed solution uses 38x less memory and is 1030x more energy efficient for processing a users-movies dataset with half a million edges.
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Gu, Yu, Chun Wu, and Jiangan Li. "Design and Implementation of a Novel Interconnection Architecture from WiFi to ZigBee." In Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications, 40–47. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2456-9_5.

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AbstractThe signal layer heterogeneous communication technology is a cross-technology communication (CTC) technology, which is a direct communication technology between different wireless devices. Since ZigBee and WiFi have overlapping spectrum distribution, the ZigBee transmission will affect the CSI sequence. We propose a CTC technology based on machine learning and neural network, from Zigbee to WiFi, leveraging only WiFi channel state information (CSI). By classifying WiFi CSI, we can distinguish whether there is ZigBee signal transmission in WiFi signal. This paper uses the machine learning method and neural network method to classify CSI sequence analyzes the importance of CSI sequence features to the classifier, improves the accuracy of machine learning classifier by extracting multiple CSI sequence features, and improves the classification accuracy by neural network classifier. In our experimental data set, the highest accuracy can reach 95%. The evaluation results show that our accuracy is higher than the existing methods.
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Hemani, Ahmed, Nasim Farahini, Syed M. A. H. Jafri, Hassan Sohofi, Shuo Li, and Kolin Paul. "The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric." In The Dark Side of Silicon, 47–94. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-31596-6_3.

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Yan, Jiang. "Design and Implementation of Educational Administration System on the Basis of C/S and B/S Heterogeneous Architecture." In Communications in Computer and Information Science, 473–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-27503-6_65.

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Тези доповідей конференцій з теми "Heterogeneous Architecture Design":

1

Fallin, Chris, Chris Wilkerson, and Onur Mutlu. "The heterogeneous block architecture." In 2014 32nd IEEE International Conference on Computer Design (ICCD). IEEE, 2014. http://dx.doi.org/10.1109/iccd.2014.6974710.

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Kinsy, Michel A., Shreeya Khadka, Mihailo Isakov, and Anam Farrukh. "Hermes: Secure heterogeneous multicore architecture design." In 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2017. http://dx.doi.org/10.1109/hst.2017.7951731.

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Alhubail, Lulwah, Masoomeh Jasemi, and Nader Bagherzadeh. "NoC Design Methodologies for Heterogeneous Architecture." In 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). IEEE, 2020. http://dx.doi.org/10.1109/pdp50117.2020.00052.

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Mussbacher, Gunter, and Daniel Amyot. "Heterogeneous pointcut expressions." In 2009 ICSE Workshop on Aspect-Oriented Requirements Engineering and Architecture Design (EA). IEEE, 2009. http://dx.doi.org/10.1109/ea.2009.5071577.

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Vansina, Nico, Bruno Loyer, and Yosuke Ogata. "Managing Heterogeneous Simulations Using Architecture-Driven Design." In The 2nd Japanese Modelica Conference Tokyo, Japan, May 17-18, 2018. Linköping University Electronic Press, 2019. http://dx.doi.org/10.3384/ecp18148202.

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Lodde, Mario, Toni Roca, and José Flich. "Heterogeneous network design for effective support of invalidation-based coherency protocols." In the 2012 Interconnection Network Architecture. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2107763.2107764.

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Zhang, Ying, Li Zhao, Ramesh Illikkal, Ravi Iyer, Andrew Herdrich, and Lu Peng. "QoS management on heterogeneous architecture for parallel applications." In 2014 32nd IEEE International Conference on Computer Design (ICCD). IEEE, 2014. http://dx.doi.org/10.1109/iccd.2014.6974702.

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Chen, Sheng-Yen, and Yao-Wen Chang. "Routing-architecture-aware analytical placement for heterogeneous FPGAs." In DAC '15: The 52nd Annual Design Automation Conference 2015. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2744769.2744903.

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Wang, Shilong, Jian Yi, Xia Hong, and Z. Zhang. "Heterogeneous Autonomous Agent Architecture for Agile Manufacturing." In ASME 2002 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2002. http://dx.doi.org/10.1115/detc2002/cie-34397.

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Considering the agent-based modeling and mapping in manufacturing system, some system models are described in this paper, which are included: Domain Based Hierarchical Structure (DBHS), Cascading Agent Structure (CAS), Proximity Relation structure (PRS), and Bus-based network structure (BNS). In DBHS, one sort of agents, called static agents, individually acts as Domain Agents, Resources Agents, UserInterface Agents and Gateway Agents. And the others, named mobile agents, are the brokers of task and process flow. Static agents representing a subsystem may itself be an agent-based network and should learn as the mobile agents to deal with new situation. Mobile agents move around the network domains taking advantage of the resources to fulfill their goals. In CAS, We use Unified Modeling Language (UML) to build up the agent-based manufacturing system It is said Enterprise agent (main agent) has factory agents together with some directly jurisdictional workshop agents, cell agents, and individual resource agents. Likewise, factory agent has workshop agents together with some directly jurisdictional cell agents and individual resource agents, and so on. In PRS, the resources agents are located together by its function and abilities. There is only one agent behaves as the task-announcer. The communication just occurs among the Proximity Relational agents. In BNS, It is very similar with the society of human being connected with a network, some agents, such as ‘cost calculating’, are just cope with the matter-of-fact job. And some agents run as the individual resources that can negotiate with each other and advertise a necessary message within the whole domain or a given group of agents. The administration just relies on the individual address of agents and the group ID code of agents.
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Guevara, Marisabel, Benjamin Lubin, and Benjamin C. Lee. "Strategies for anticipating risk in heterogeneous system design." In 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2014. http://dx.doi.org/10.1109/hpca.2014.6835926.

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