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Автор: Grafiati

Опубліковано: 28 січня 2023

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Статті в журналах з теми "Microarchitectural attack"

Mao, Yuxiao, Vincent Migliore, and Vincent Nicomette. "MATANA: A Reconfigurable Framework for Runtime Attack Detection Based on the Analysis of Microarchitectural Signals." Applied Sciences 12, no. 3 (January 29, 2022): 1452. http://dx.doi.org/10.3390/app12031452.

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Microarchitectural attacks exploit target hardware properties to break software isolation techniques used by the processor. These attacks are extremely powerful and hard to detect since the determination of the program execution’s impact on the microarchitecture is at the same time not precisely understood and not easily observable at the software layer. Some approaches have attempted to benefit from existing hardware to better understand and detect the microarchitectural attacks (i.e., Hardware Performance Counters or Arm CoreSight), but such hardware was not meant to be used for cybersecurity, with reduced choice on observable signals and limited throughput of information. In this paper, we propose MATANA, an open and adaptive reconfigurable hardware/software co-designed framework. Combining fine-grained analysis of microarchitectural signals and software support, MATANA allows to design and assess detection mechanisms for attacks by characterizing their microarchitectural effects—in particular, microarchitectural attacks, but also some high-level attacks such as return-oriented programming attacks. The paper also describes a prototype implementation, built with a RISC-V softcore processor Rocket running Linux 4.15 on a Virtex-6 FPGA. We successfully used MATANA to analyze cache side-channel attacks and build attack detection logic from two different perspectives: instruction-based and memory-access-based. We also successfully detected return-oriented programming attacks by exhibiting a specific behavioral pattern on the microarchitecture.

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Lou, Xiaoxuan, Tianwei Zhang, Jun Jiang, and Yinqian Zhang. "A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks, and Defenses in Cryptography." ACM Computing Surveys 54, no. 6 (July 2021): 1–37. http://dx.doi.org/10.1145/3456629.

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Side-channel attacks have become a severe threat to the confidentiality of computer applications and systems. One popular type of such attacks is the microarchitectural attack, where the adversary exploits the hardware features to break the protection enforced by the operating system and steal the secrets from the program. In this article, we systematize microarchitectural side channels with a focus on attacks and defenses in cryptographic applications. We make three contributions. (1) We survey past research literature to categorize microarchitectural side-channel attacks. Since these are hardware attacks targeting software, we summarize the vulnerable implementations in software, as well as flawed designs in hardware. (2) We identify common strategies to mitigate microarchitectural attacks, from the application, OS, and hardware levels. (3) We conduct a large-scale evaluation on popular cryptographic applications in the real world and analyze the severity, practicality, and impact of side-channel vulnerabilities. This survey is expected to inspire side-channel research community to discover new attacks, and more importantly, propose new defense solutions against them.

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Fournaris, Apostolos, Lidia Pocero Fraile, and Odysseas Koufopavlou. "Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: a Survey of Potent Microarchitectural Attacks." Electronics 6, no. 3 (July 13, 2017): 52. http://dx.doi.org/10.3390/electronics6030052.

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Shepherd, Michael, Scott Brookes, and Robert Denz. "Transient Execution and Side Channel Analysis: a Vulnerability or a Science Experiment?" International Conference on Cyber Warfare and Security 17, no. 1 (March 2, 2022): 288–97. http://dx.doi.org/10.34190/iccws.17.1.20.

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In the world of computer security, attackers are constantly looking for new exploits to gain data from or control over a computer system. One category of exploit that can prove quite effective at accessing privileged data is side channel exploits. These exploits attempt to take advantage of vulnerabilities that are inherent in the design of a system rather than vulnerabilities in the code that has been written for and is running on said system. In other words, they exploit side effects of computation. Examples of this include measuring the power consumption of a system’s processor over time and analysing that power usage to leak system secrets or reading secrets from a system by analysing the electromagnetic radiation the system leaks as it processes data. Another type of side channel attack is a cache-based side channel attack, which exploits the timings of cache and memory accesses to determine data from the target system. We discuss some of the more common types of side channel attacks used to interpret data values from the microarchitectural changes created by transient executions. In particular, we will focus on attacks that are capable of recovering data that is processed through transient execution in some way and then wrongly accessed using a side channel, such as the Spectre and Meltdown classes of attack. We also discuss other attacks of a similar type and survey some popular mitigations for these attacks. We provide a survey of all available Spectre proof-of-concept repositories on GitHub, evaluating whether they work on different platforms. Finally, we review our experiences with these types of attacks on modern systems and comment on the attacks’ practicality, reliability, and portability. We conclude that these types of attacks are interesting, but there are some practicality and reliability concerns that make other attacks easier much of the time.

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Gnanavel, S., K. E. Narayana, K. Jayashree, P. Nancy, and Dawit Mamiru Teressa. "Implementation of Block-Level Double Encryption Based on Machine Learning Techniques for Attack Detection and Prevention." Wireless Communications and Mobile Computing 2022 (July 9, 2022): 1–9. http://dx.doi.org/10.1155/2022/4255220.

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Cloud computing is one of the most important business models of modern information technology. It provides a minimum of various services to the user interaction and low cost (hardware and software). Cloud services are based on the newline architectures on virtualization by using the multitenancy for better resource management and newline strong isolation between several virtual machines (VMs). The spying on a victim VM is challenging, particularly when one wants to use per-core microarchitectural features as a side channel. For example, the cache contains the most potential for damaging side channels, but shared information across different cores affects the cloud information. To overcome this problem, propose the Secure Block-Level Double Encryption (SBLDE) algorithm for user signature verification in the cloud server. It uses identity-based detection techniques to monitor the colocated VMs to identify abnormal cache data and channel behaviors typically during VM data transformation. The identity-based linear classification (IBLC) method is used for classifying the attacker channel when the data is transferred/retrieved from the VM cloud server. This cloud controller finds the channel misbehavior to block the port or channel, changing other available ports’ communication. The service verification provides strong user access permission on the cloud server when the unknown request to the cloud server suddenly executes the key authentication to verify the user permission. This linear classification trains the existing side-channel attack datasets to the classifier and identifies the VM cloud’s attack channel. The study focused on preventing attacks from interrupting the system and serves as an effective means for cross-VM side-channel attacks. This proposed method protects the cloud data and prevents cross-VM channel attack detection efficiently, compared to other existing methods. In this overall proposed method, SBLDE’s performance is to be evaluated and then compared with the existing method.

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Di, Bang, Daokun Hu, Zhen Xie, Jianhua Sun, Hao Chen, Jinkui Ren, and Dong Li. "TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling." ACM Transactions on Architecture and Code Optimization 19, no. 1 (March 31, 2022): 1–23. http://dx.doi.org/10.1145/3491218.

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Co-running GPU kernels on a single GPU can provide high system throughput and improve hardware utilization, but this raises concerns on application security. We reveal that translation lookaside buffer (TLB) attack, one of the common attacks on CPU, can happen on GPU when multiple GPU kernels co-run. We investigate conditions or principles under which a TLB attack can take effect, including the awareness of GPU TLB microarchitecture, being lightweight, and bypassing existing software and hardware mechanisms. This TLB-based attack can be leveraged to conduct Denial-of-Service (or Degradation-of-Service) attacks. Furthermore, we propose a solution to mitigate TLB attacks. In particular, based on the microarchitecture properties of GPU, we introduce a software-based system, TLB-pilot, that binds thread blocks of different kernels to different groups of streaming multiprocessors by considering hardware isolation of last-level TLBs and the application’s resource requirement. TLB-pilot employs lightweight online profiling to collect kernel information before kernel launches. By coordinating software- and hardware-based scheduling and employing a kernel splitting scheme to reduce load imbalance, TLB-pilot effectively mitigates TLB attacks. The result shows that when under TLB attack, TLB-pilot mitigates the attack and provides on average 56.2% and 60.6% improvement in average normalized turnaround times and overall system throughput, respectively, compared to the traditional Multi-Process Service based co-running solution. When under TLB attack, TLB-pilot also provides up to 47.3% and 64.3% improvement (41% and 42.9% on average) in average normalized turnaround times and overall system throughput, respectively, compared to a state-of-the-art co-running solution for efficiently scheduling of thread blocks.

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Gruss, Daniel. "Software-based microarchitectural attacks." it - Information Technology 60, no. 5-6 (December 19, 2018): 335–41. http://dx.doi.org/10.1515/itit-2018-0034.

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Abstract Modern processors are highly optimized systems where every single cycle of computation time matters. Many optimizations depend on the data that is being processed. Microarchitectural attacks leak this data (side channels) or exploit physical imperfections to take control of the entire system (fault attacks). In my thesis (D. Gruss. Software-based Microarchitectural Attacks. PhD thesis, Graz University of Technology, 2017), I improved over state of the art in microarchitectural attacks and defenses in three dimensions. I cover these briefly in this summary. First, I show that attacks can be fully automated. Second, I present several novel previously unknown side channels. Third, I show that attacks can be mounted in highly restricted environments such as sandboxed JavaScript code in websites, and on any computer system including smartphones, tablets, personal computers, and commercial cloud systems. These results formed one of the corner stones for attacks like Meltdown (M. Lipp et al. Meltdown: Reading kernel memory from user space. In USENIX Security Symposium, 2018) and Spectre (P. Kocher et al. Spectre attacks: Exploiting speculative execution. In S&P, 2019) which were discovered months after the thesis was concluded.

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Montasari, Reza, Amin Hosseinian-Far, Richard Hill, Farshad Montaseri, Mak Sharma, and Shahid Shabbir. "Are Timing-Based Side-Channel Attacks Feasible in Shared, Modern Computing Hardware?" International Journal of Organizational and Collective Intelligence 8, no. 2 (April 2018): 32–59. http://dx.doi.org/10.4018/ijoci.2018040103.

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This article describes how there exist various vulnerabilities in computing hardware that adversaries can exploit to mount attacks against the users of such hardware. Microarchitectural attacks, the result of these vulnerabilities, take advantage of microarchitectural performance of processor implementations, revealing hidden computing process. Leveraging microarchitectural resources, adversaries can potentially launch timing-based side-channel attacks in order to leak information via timing. In view of these security threats against computing hardware, the authors analyse current attacks that take advantage of microarchitectural elements in shared computing hardware. This analysis focuses only on timing-based side-channel attacks against the components of modern PC platforms - with references being made also to other platforms when relevant - as opposed to any other variations of side-channel attacks which have a broad application range. To this end, the authors analyse timing attacks performed against processor and cache components, again with references to other components when appropriate.

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Yong-Joon Park, Zhao Zhang, and Gyungho Lee. "Microarchitectural Protection Against Stack-Based Buffer Overflow Attacks." IEEE Micro 26, no. 4 (July 2006): 62–71. http://dx.doi.org/10.1109/mm.2006.76.

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Schwarz, Michael, and Daniel Gruss. "How Trusted Execution Environments Fuel Research on Microarchitectural Attacks." IEEE Security & Privacy 18, no. 5 (September 2020): 18–27. http://dx.doi.org/10.1109/msec.2020.2993896.

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Більше джерел

Дисертації з теми "Microarchitectural attack"

Tillman, Clara. "Understanding the MicroScope Microarchitectural Replay Attack Through a New Implementation." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-445448.

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Side-channel attacks, where information is extracted through analysis of the implementation of a computer system by a malicious adversary, constitute security vulnerabilities that may be hard to mitigate. They however suffer from noise originating from, for example, other processes or frequent cache evictions, which forces an attacker to repeat the attack a large number of times in order to obtain useful information. Some systems, like secure enclaves, already implement security mechanisms that make these kinds of attacks harder to execute. With MicroScope, a new framework structured as a kernel module, even these mechanisms can be evaded. Due to its novelty, documentation on how MicroScope is implemented and results obtained from MicroScopeassisted side-channel attacks are limited. The result presented in this thesis consists of a detailed, low level description of how the MicroScope framework functions in order to compromise a target machine, and how to execute a MicroScope-assisted side-channel replay attack. In conclusion, using the methods outlined in this thesis, it is possible to execute such an attack with the malicious intent of obtaining protected data.

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Almeida, Braga Daniel de. "Cryptography in the wild : the security of cryptographic implementations." Thesis, Rennes 1, 2022. http://www.theses.fr/2022REN1S067.

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Les attaques par canaux auxiliaire sont redoutables face aux implémentations cryptographiques. Malgré les attaques passées, et la prolifération d'outils de vérification, ces attaques affectent encore de nombreuses implémentations. Dans ce manuscrit, nous abordons deux aspects de cette problématique, centrés autour de l'attaque et de la défense. Nous avons dévoilé plusieurs attaques par canaux auxiliaires microarchitecturaux sur des implémentations de protocoles PAKE. En particulier, nous avons exposé des attaques sur Dragonfly, utilisé dans la nouvelle norme Wi-Fi WPA3, et SRP, déployé dans de nombreux logiciel tels que ProtonMail ou Apple HomeKit. Nous avons également exploré le manque d'utilisation par les développeurs d'outil permettant de détecter de telles attaques. Nous avons questionné des personnes impliqués dans différents projets cryptographiques afin d'identifier l'origine de ce manque. De leur réponses, nous avons émis des recommandations. Enfin, dans l'optique de mettre fin à la spirale d'attaques-correction sur les implémentations de Dragonfly, nous avons fournis une implémentation formellement vérifiée de la couche cryptographique du protocole, dont l'exécution est indépendante des secrets
Side-channel attacks are daunting for cryptographic implementations. Despite past attacks, and the proliferation of verification tools, these attacks still affect many implementations. In this manuscript, we address two aspects of this problem, centered around attack and defense. We unveil several microarchitectural side-channel attacks on implementations of PAKE protocols. In particular, we exposed attacks on Dragonfly, used in the new Wi-Fi standard WPA3, and SRP, deployed in many software such as ProtonMail or Apple HomeKit. We also explored the lack of use by developers of tools to detect such attacks. We questioned developers from various cryptographic projects to identify the origin of this lack. From their answers, we issued recommendations. Finally, in order to stop the spiral of attack-patch on Dragonfly implementations, we provide a formally verified implementation of the cryptographic layer of the protocol, whose execution is secret-independent

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Irazoki, Gorka. "Cross-core Microarchitectural Attacks and Countermeasures." Digital WPI, 2017. https://digitalcommons.wpi.edu/etd-dissertations/160.

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In the last decade, multi-threaded systems and resource sharing have brought a number of technologies that facilitate our daily tasks in a way we never imagined. Among others, cloud computing has emerged to offer us powerful computational resources without having to physically acquire and install them, while smartphones have almost acquired the same importance desktop computers had a decade ago. This has only been possible thanks to the ever evolving performance optimization improvements made to modern microarchitectures that efficiently manage concurrent usage of hardware resources. One of the aforementioned optimizations is the usage of shared Last Level Caches (LLCs) to balance different CPU core loads and to maintain coherency between shared memory blocks utilized by different cores. The latter for instance has enabled concurrent execution of several processes in low RAM devices such as smartphones. Although efficient hardware resource sharing has become the de-facto model for several modern technologies, it also poses a major concern with respect to security. Some of the concurrently executed co-resident processes might in fact be malicious and try to take advantage of hardware proximity. New technologies usually claim to be secure by implementing sandboxing techniques and executing processes in isolated software environments, called Virtual Machines (VMs). However, the design of these isolated environments aims at preventing pure software- based attacks and usually does not consider hardware leakages. In fact, the malicious utilization of hardware resources as covert channels might have severe consequences to the privacy of the customers. Our work demonstrates that malicious customers of such technologies can utilize the LLC as the covert channel to obtain sensitive information from a co-resident victim. We show that the LLC is an attractive resource to be targeted by attackers, as it offers high resolution and, unlike previous microarchitectural attacks, does not require core-colocation. Particularly concerning are the cases in which cryptography is compromised, as it is the main component of every security solution. In this sense, the presented work does not only introduce three attack variants that can be applicable in different scenarios, but also demonstrates the ability to recover cryptographic keys (e.g. AES and RSA) and TLS session messages across VMs, bypassing sandboxing techniques. Finally, two countermeasures to prevent microarchitectural attacks in general and LLC attacks in particular from retrieving fine- grain information are presented. Unlike previously proposed countermeasures, ours do not add permanent overheads in the system but can be utilized as preemptive defenses. The first identifies leakages in cryptographic software that can potentially lead to key extraction, and thus, can be utilized by cryptographic code designers to ensure the sanity of their libraries before deployment. The second detects microarchitectural attacks embedded into innocent-looking binaries, preventing them from being posted in official application repositories that usually have the full trust of the customer.

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Mushtaq, Maria. "Software-based Detection and Mitigation of Microarchitectural Attacks on Intel’s x86 Architecture." Thesis, Lorient, 2019. http://www.theses.fr/2019LORIS531.

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Les attaques par canaux cachés basées sur les accès aux mémoires caches constituent une sous-catégorie représentant un puissant arsenal permettant de remettre en cause la sécurité d’algorithmes cryptographiques en ciblant leurs implémentations. Malgré de nombreux efforts, les techniques de protection contre ces attaques ne sont pas encore assez matures. Ceci est principalement dû au fait que la plupart des techniques ne protègent généralement pas contre tous les scénarii d’attaques. De plus, ces solutions peuvent impacter fortement les performances des systèmes. Cette thèse propose des arguments en faveur du renforcement de la sécurité et de la confidentialité dans les systèmes informatiques modernes tout en conservant leurs performances. Pour cela, la thèse développe une protection basée sur les besoins, qui permettent au système d’exploitation d’appliquer uniquement des mesures de protection après la détection des attaques. Ainsi, la détection peut servir de première ligne de défense. Cependant, pour que la stratégie de protection basée sur la détection soit efficace, il faut que cette dernière soit fiable, n’impacte que faiblement les performances et couvre un large spectre d’attaques avant que ces dernières atteignent leur but. Dans cette optique, cette thèse propose un cadre complet pour la protection basée sur la détection d’un ensemble d’attaques exploitant les mémoires caches lors de l’exécution sous des conditions de charge variables du système. De plus, la thèse propose de coupler l’utilisation du principe de détection avec un mécanisme de protection intégré au système d’exploitation Linux. Bien que le mécanisme de protection proposé soit appliqué à Linux, la solution est extensible à d’autres systèmes d’exploitation. Cette thèse démontre que la sécurité et la confidentialité doivent être pris en compte au niveau système et que les solutions de protection doivent adopter une approche holistique
Access-driven cache-based sidechannel attacks, a sub-category of SCAs, are strong cryptanalysis techniques that break cryptographic algorithms by targeting their implementations. Despite valiant efforts, mitigation techniques against such attacks are not very effective. This is mainly because most mitigation techniques usually protect against any given specific vulnerability and do not take a system-wide approach. Moreover, these solutions either completely remove or greatly reduce the prevailing performance benefits in computing systems that are hard earned over many decades. This thesis presents arguments in favor of enhancing security and privacy in modern computing architectures while retaining the performance benefits. The thesis argues in favor of a need-based protection, which would allow the operating system to apply mitigation only after successful detection of CSCAs. Thus, detection can serve as a first line of defense against such attacks. However, for detection-based protection strategy to be effective, detection needs to be highly accurate, should incur minimum system overhead at run-time, should cover a large set of attacks and should be capable of early stage detection, i.e., before the attack completes. This thesis proposes a complete framework for detection-based protection. At first, the thesis presents a highly accurate, fast and lightweight detection framework to detect a large set of Cache-based SCAs at run-time under variable system load conditions. In the follow up, the thesis demonstrates the use of this detection framework through the proposition of an OS-level run-time detection-based mitigation mechanism for Linux generalpurpose distribution. Though the proposed mitigation mechanism is proposed for Linux general distributions, which is widely used in commodity hardware, the solution is scalable to other operating systems. We provide extensive experiments to validate the proposed detection framework and mitigation mechanism. This thesis demonstrates that security and privacy are system-wide concerns and the mitigation solutions must take a holistic approach

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Grimsdal, Gunnar, and Patrik Lundgren. "Examining the Impact of Microarchitectural Attacks on Microkernels : a study of Meltdown and Spectre." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-159999.

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Most of today's widely used operating systems are based on a monolithic design and have a very large code size which complicates verification of security-critical applications. One approach to solving this problem is to use a microkernel, i.e., a small kernel which only implements the bare necessities. A system usinga microkernel can be constructed using the operating-system framework Genode, which provides security features and a strict process hierarchy. However, these systems may still be vulnerable to microarchitectural attacks, which can bypassan operating system's security features, exploiting vulnerable hardware. This thesis aims to investigate whether microkernels are vulnerable to the microarchitectural attacks Meltdown and Spectre version 1 in the context of Genode. Furthermore, the thesis analyzes the execution cost of mitigating Spectre version 1 in a Genode's remote procedure call. The result shows how Genode does not mitigate the Meltdown attack, which will be confirmed by demonstrating a working Meltdown attack on Genode+Linux. We also determine that microkernels are vulnerable to Spectre by demonstrating a working attack against two microkernels. However, we show that the cost of mitigating this Spectre attack is small, with a cost of < 3 slowdown for remote procedure calls in Genode.

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Bowen, Lucy R. "The Performance Cost of Security." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2002.

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Historically, performance has been the most important feature when optimizing computer hardware. Modern processors are so highly optimized that every cycle of computation time matters. However, this practice of optimizing for performance at all costs has been called into question by new microarchitectural attacks, e.g. Meltdown and Spectre. Microarchitectural attacks exploit the effects of microarchitectural components or optimizations in order to leak data to an attacker. These attacks have caused processor manufacturers to introduce performance impacting mitigations in both software and silicon. To investigate the performance impact of the various mitigations, a test suite of forty-seven different tests was created. This suite was run on a series of virtual machines that tested both Ubuntu 16 and Ubuntu 18. These tests investigated the performance change across version updates and the performance impact of CPU core number vs. default microarchitectural mitigations. The testing proved that the performance impact of the microarchitectural mitigations is non-trivial, as the percent difference in performance can be as high as 200%.

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Lindqvist, Maria. "Dynamic Eviction Set Algorithms and Their Applicability to Cache Characterisation." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-420317.

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Eviction sets are groups of memory addresses that map to the same cache set. They can be used to perform efficient information-leaking attacks against the cache memory, so-called cache side channel attacks. In this project, two different algorithms that find such sets are implemented and compared. The second of the algorithms improves on the first by using a concept called group testing. It is also evaluated if these algorithms can be used to analyse or reverse engineer the cache characteristics, which is a new area of application for this type of algorithms. The results show that the optimised algorithm performs significantly better than the previous state-of-the-art algorithm. This means that countermeasures developed against this type of attacks need to be designed with the possibility of faster attacks in mind. The results also shows, as a proof-of-concept, that it is possible to use these algorithms to create a tool for cache analysis.

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Частини книг з теми "Microarchitectural attack"

Acıçmez, Onur, and çetin Kaya Koç. "Microarchitectural Attacks and Countermeasures." In Cryptographic Engineering, 475–504. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-71817-0_18.

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Grimsdal, Gunnar, Patrik Lundgren, Christian Vestlund, Felipe Boeira, and Mikael Asplund. "Can Microkernels Mitigate Microarchitectural Attacks?" In Secure IT Systems, 238–53. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-35055-0_15.

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Sepúlveda, Johanna. "Secure Cryptography Integration: NoC-Based Microarchitectural Attacks and Countermeasures." In Network-on-Chip Security and Privacy, 153–79. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-69131-8_7.

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Schwarz, Michael, Clémentine Maurice, Daniel Gruss, and Stefan Mangard. "Fantastic Timers and Where to Find Them: High-Resolution Microarchitectural Attacks in JavaScript." In Financial Cryptography and Data Security, 247–67. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-70972-7_13.

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Montasari, Reza, Bobby Tait, Hamid Jahankhani, and Fiona Carroll. "An Investigation of Microarchitectural Cache-Based Side-Channel Attacks from a Digital Forensic Perspective: Methods of Exploits and Countermeasures." In Advanced Sciences and Technologies for Security Applications, 281–306. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-88040-8_11.

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Zankl, Andreas, Hermann Seuschek, Gorka Irazoqui, and Berk Gulmezoglu. "Side-Channel Attacks in the Internet of Things." In Research Anthology on Artificial Intelligence Applications in Security, 2058–90. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-7705-9.ch091.

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The Internet of Things (IoT) rapidly closes the gap between the virtual and the physical world. As more and more information is processed through this expanding network, the security of IoT devices and backend services is increasingly important. Yet, side-channel attacks pose a significant threat to systems in practice, as the microarchitectures of processors, their power consumption, and electromagnetic emanation reveal sensitive information to adversaries. This chapter provides an extensive overview of previous attack literature. It illustrates that microarchitectural attacks can compromise the entire IoT ecosystem: from devices in the field to servers in the backend. A subsequent discussion illustrates that many of today's security mechanisms integrated in modern processors are in fact vulnerable to the previously outlined attacks. In conclusion to these observations, new countermeasures are needed that effectively defend against both microarchitectural and power/EM based side-channel attacks.

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Zankl, Andreas, Hermann Seuschek, Gorka Irazoqui, and Berk Gulmezoglu. "Side-Channel Attacks in the Internet of Things." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 325–57. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2845-6.ch013.

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Тези доповідей конференцій з теми "Microarchitectural attack"

Aciiçmez, Onur. "Yet another MicroArchitectural Attack:." In the 2007 ACM workshop. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1314466.1314469.

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Dinakarrao, Sai Manoj Pudukotai, Sairaj Amberkar, Sahil Bhat, Abhijitt Dhavlle, Hossein Sayadi, Avesta Sasan, Houman Homayoun, and Setareh Rafatirad. "Adversarial Attack on Microarchitectural Events based Malware Detectors." In DAC '19: The 56th Annual Design Automation Conference 2019. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3316781.3317762.

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Kasikci, Baris, and Kevin Loughlin. "Holistic defenses against microarchitectural attacks." In Disruptive Technologies in Information Sciences V, edited by Misty Blowers, Russell D. Hall, and Venkateswara R. Dasari. SPIE, 2021. http://dx.doi.org/10.1117/12.2589076.

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Lu, Yao, Kaiyan Chen, and Yinlong Wang. "Research on Microarchitectural Cache Attacks." In Proceedings of the 3rd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2019). Paris, France: Atlantis Press, 2019. http://dx.doi.org/10.2991/iccia-19.2019.32.

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Hoffman, Caio, Diego F. Aranha, Mario Lúcio Côrtes, and Guido Costa Souza de Araújo. "Computer Security by Hardware-Intrinsic Authentication." In Anais Estendidos do Simpósio Brasileiro de Segurança da Informação e de Sistemas Computacionais. Sociedade Brasileira de Computação - SBC, 2020. http://dx.doi.org/10.5753/sbseg_estendido.2020.19264.

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The Internet of Things (IoT) has brought evident security concerns. New solutions in security for IoT will need to reduce the dependency on nonvolatile memory for key storage, promote easier means to uniquely identify billions of devices, etc. Physical Unclonable Functions (PUFs) have been adopted as the future for key derivation and hardware fingerprinting. This work presents CSHIA: a new computer architecture that takes into account limitations and strengths of PUFs to provide code and data integrity and authenticity in a seamless design that does not demand changes in processors microarchitecture or software. We describe and analyze a full-fledged FPGA deployment of the architecture and consider attack scenarios, including side-channel attacks on PUFs.

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Skarlatos, Dimitrios, Zirui Neil Zhao, Riccardo Paccagnella, Christopher W. Fletcher, and Josep Torrellas. "Jamais vu: thwarting microarchitectural replay attacks." In ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3445814.3446716.

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JS, Rajesh, and Amin Rezaei. "Session details: Microarchitectural Attacks and Countermeasures." In ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3578475.

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Andreou, Alexandres, Andrey Bogdanov, and Elmar Tischhauser. "Cache timing attacks on recent microarchitectures." In 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2017. http://dx.doi.org/10.1109/hst.2017.7951819.

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Frigo, Pietro, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. "Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU." In 2018 IEEE Symposium on Security and Privacy (SP). IEEE, 2018. http://dx.doi.org/10.1109/sp.2018.00022.

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Mirbagher-Ajorpaz, Samira, Gilles Pokam, Esmaeil Mohammadian-Koruyeh, Elba Garza, Nael Abu-Ghazaleh, and Daniel A. Jimenez. "PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron." In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2020. http://dx.doi.org/10.1109/micro50266.2020.00093.

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