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Дисертації з теми "Risk microprocessor"

Автор: Grafiati

Опубліковано: 7 червня 2025

Оновлено: 2 серпня 2025

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1

Howe, Jonathan E. (Jonathan Emerson) 1973. "Minimizing the risk qualification test wafers have on the manufacturing readings of a new microprocessor fabrication site through data processes." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/84226.

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Thesis (S.M.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.<br>Includes bibliographical references (p. 73).<br>by Jonathan E. Howe.<br>S.M.

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2

Pittman, Richard Neil. "Extensible microprocessor without interlocked pipeline stages (emips), the reconfigurable microprocessor." Thesis, Texas A&M University, 2003. http://hdl.handle.net/1969.1/5976.

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In this thesis we propose to realize the performance benefits of applicationspecific hardware optimizations in a general-purpose, multi-user system environment using a dynamically extensible microprocessor architecture. We have called our dynamically extensible microprocessor design the Extensible Microprocessor without Interlocked Pipeline Stages, or eMIPS. The eMIPS architecture uses the interaction of fixed and configurable logic available in modern Field Programmable Gate Array (FPGA). This interaction is used to address the limitations of

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3

Junqueira, Alexandre Ambrozi. "Risco : microprocessador RISC CMOS de 32 bits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1993. http://hdl.handle.net/10183/21530.

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Este trabalho apresenta o estudo, a definição e a simulação elétrica e lógica de um microprocessador CMOS de 32 bits, com arquitetura tipo RISC - o Risco. Dentre as principais características do Risco destacam-se: dados, instruções e endereços são palavras de 32 bits; a unidade de endereçamento é a palavra, permitindo um acesso a 4 Giga palavras (16 Gbytes); a comunição com a memória é feita por um barramento multiplexado de 32 bits para dados e endereços; possui 32 registradores de 32 bits, incluídos nestes o contador de programa, o apontador de pilha, a palavra de status do processador e um

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4

Olufsen, Eskil Viksand. "Processing Core for Compressing Wireless Data : The Enhancement of a RISC Microprocessor." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10067.

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<p>This thesis explores the ability of the proprietary Texas Instruments embedded 16 bits RISC microprocessor, NanoRisc, to process common lossless compression algorithms, and propose extensions in order to increase its performance on this task. In order to measure performance of the NanoRisc microprocessor, the existing software tool chain was enhanced for profiling and simulating the improvements, and three fundamentally different adaptive data compression algorithms with different supporting data structures were implemented in the NanoRisc assembly language. On the background of profiling

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5

Wang, Wei. "An improved instruction-level power and energy model for RISC microprocessors." Thesis, University of Southampton, 2017. https://eprints.soton.ac.uk/410308/.

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Recently, the power and energy consumed by a chip has become a primary design constraint for embedded systems and is largely aaffected by software. Because aims vary with the application domain, the best program is sometimes the most power or energy efficient one rather than the fastest. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power without measurement. Therefore, it is vital to discover which factors can affect a program's power and energy consumption. In this thesis we present an instruction level model to estimate the

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6

Nash, Sean Tyrer Harry W. "MizzouSMP." Diss., Columbia, Mo. : University of Missouri--Columbia, 2009. http://hdl.handle.net/10355/6484.

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Анотація:

Title from PDF of title page (University of Missouri--Columbia, viewed on Feb 18, 2010). The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Thesis advisor: Dr. Harry Tyrer. Includes bibliographical references.

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7

DELORME, VINCENT. "Le microprocesseur f-risc : architecture haut niveau et environnement de programmation." Paris 6, 1994. http://www.theses.fr/1994PA066547.

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Une nouvelle architecture modulaire de type risc est developpee sur la base d'un jeu d'instructions a faible contenu semantique. Les specifications d'un premier microprocesseur issu de cette architecture et destine aux applications embarquees conduisent a la conception d'un circuit de complexite moderee. Ce processeur d'architecture externe de type harvard se compose en interne d'une unite centrale couplee a un processeur flottant simple precision par l'intermediaire d'un bus normalise. Le cur de type risc 32 bits muni d'un pipeline d'instructions a trois etages offre une architecture interne

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8

Fuchs, Franz Anton. "Analysis of Transient-Execution Attacks on the out-of-order CHERI-RISC-V Microprocessor Toooba." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291743.

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Transient-execution attacks have been deemed a large threat for microarchitectures through research in recent years. In this work, I reproduce and develop transient-execution attacks against RISC-V and CHERI-RISC-V microarchitectures. CHERI is an instruction set architecture (ISA) security extension that provides fine-grained memory protection and compartmentalisation. I conduct transient-execution experiments for this work on Toooba – a superscalar out-of-order processor implementing CHERI-RISC-V. I present a new subclass of transient-execution attacks dubbed Meltdown-CF(Capability Forgery).

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9

Mikulis, Mindaugas. "Procesorinio komponento bendrinimo tyrimas: analizės aspektai." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2007. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2007~D_20070816_143457-92440.

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Mikroelektronikos technologinėms galimybėms stipriai lenkiant projektavimo galimybes, projektavimo etapas reikalauja naujų metodų. Vienas iš problemos sprendimų būdų yra atkartojimo technologija. Pirmoje dalyje yra analizuojama literatūra. Apžvelgiamas atkartojimo technologijos objektas. Remiantis literatūra, pateikiamas platus ir siauras atkartojimo technologijos apibrėžimas. Pateikiami komponento apibrėžimai, komponento pakartotinio panaudojimo sąvokos ir metodai. Taip pat apžvelgiami mikroprocesoriai, mikroprocesorių architektūros. Antroje dalyje išanalizuojamas pateiktas mikroprocesorius,

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10

Bjäreholt, Johan. "RISC-V Compiler Performance:A Comparison between GCC and LLVM/clang." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14659.

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RISC-V is a new open-source instruction set architecture (ISA) that in De-cember 2016 manufactured its rst mass-produced processors. It focuses onboth eciency and performance and diers from other open-source architec-tures by not having a copyleft license permitting vendors to freely design,manufacture and sell RISC-V chips without any fees nor having to sharetheir modications on the reference implementations of the architecture.The goal of this thesis is to evaluate the performance of the GCC andLLVM/clang compilers support for the RISC-V target and their ability tooptimize for the architectu

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11

Marwood, Warren. "An integrated multiprocessor for matrix algorithms /." Title page, table of contents and abstract only, 1994. http://web4.library.adelaide.edu.au/theses/09PH/09phm391.pdf.

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12

Carro, Luigi. "Algoritmos e arquiteturas para o desenvolvimento de sistemas computacionais." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1996. http://hdl.handle.net/10183/17780.

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Este trabalho trata de arquiteturas e algoritmos para o desenvolvimento de sistemas computacionais. Tais sistemas são constituídos de um microprocessador (específico ou comercialmente disponível), de seu conjunto de programas e de um HW dedicado que será utilizado para otimização do sistema. O objetivo principal desta tese é demonstrar que, presentemente, a linha divisória entre HW e SW e cada vez mais tênue, e a transição entre um e outro pode ser feita de maneira suave pelo projetista de sistemas, na busca de um ponto ótimo no balanço entre custo e desempenho. Apresenta-se em seqüência o amb

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13

Lee, Ming-Tai, and 李銘泰. "An FPGA design of a performance-improved 8-bit RISC microprocessor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/62904091655421985678.

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碩士<br>長庚大學<br>電子工程研究所<br>94<br>In this thesis, we use Verilog Hardware Description Language (HDL) to design an 8-bit RISC microprocessor. Here, we first efficiently reorganize the input clock scheme. In addition, using the pipelining structure the instruction cycle is further reduced to two input clocks. As a result, the performance efficiency of the designed CPU is enhanced. In order to avoid possible mistakes arising during the programming task, we rearrange the memory management of the designed CPU by changing the address of the special function register to FFH. We also include an external

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14

Sheu, Yuh-Ren, and 許裕仁. "Issues of the RISC Execution Core for a Superscalar CISC Microprocessor." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/36939627583475659122.

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碩士<br>國立交通大學<br>資訊工程學系<br>85<br>Originally, Intel x86 processor is a scalar CISC processor, i.e. it can finish one x86 instruction per cycle at the most. Due to the inhibitive cost and the limitation of semiconductor process technology and electrical property, we cannot lift up the clock speed of x86 processor unendingly to gain much more performance improvement. It seems straightforward that we can build a 2-way issue superscalar x86 processor just by adding another one integer pipeline to

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15

Tanik, Haluk Kent. "ECDSA optimizations on an ARM processor for a NIST curve over GF(p)." Thesis, 2001. http://hdl.handle.net/1957/28985.

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The Elliptic Curve Digital Signature Algorithm (ECDSA) is the elliptic curve analog of the Digital Signature Algorithm (DSA) and a federal government approved digital signature method. In this thesis work, software optimization techniques were applied to speed up the ECDSA for a particular NTST curve over GF(p). The Montgomery multiplication is used extensively in the ECDSA. By taking advantage of the algorithmic properties of the Montgomery multiplication method, special structure of the curve parameters and also applying certain fundamental and specific software optimization techniques, we h

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16

Turan, Eda. "ECDSA optimizations on ARM processor for a NIST curve over GF(2m)." Thesis, 2001. http://hdl.handle.net/1957/29966.

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The Elliptic Curve Digital Signature Algorithm (ECDSA) is one of the most popular algorithms to digitally sign streams or blocks of data. In this thesis we concentrate on porting and optimizing the ECDSA on the ARM7 processor for a particular NIST curve over GF(2[superscript m]). The selected curve is a binary curve of order 233. We show that for this particular curve, the ECDSA can be implemented significantly faster than the general case. The optimized algorithms have been implemented in C and the ARM assembly. The analysis and performance results indicate that by using certain machine and c

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17

Hu, Ching-Chang, and 胡慶彰. "An 8-bits RISC Microprocessor Design for Acupuncture-like TENS Signal Process Applications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/72673584597475043480.

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碩士<br>中原大學<br>電子工程研究所<br>96<br>The transcutaneous electrical nerve stimulator has been utilized in chronic and surgical pain relief for a long while. Previous study shown that the stimulation on specific acupuncture points have extraordinary pain relieving performance. Usually the analog driving circuit of transcutaneous electrical nerve stimulator chip is manufactured by BiCMOS High-V process or assemble of electrical component. In order to integrate the analog driving circuit with signal processing block, the 0.35m CMOS technology was used to design the charge pump circuit in this study. Du

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18

Hu, Wen-hsiang, and 胡文祥. "Design and Implementation of In-Circuit Emulation of an Embedded RISC Microprocessor with DSP Capability." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/04607253852142279018.

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碩士<br>國立交通大學<br>資訊工程系<br>89<br>With the rapid development in electronics and information industry, fast time-to-market plays an important role in product success. Therefore, to shorten the design cycle is a matter of concern today. Using a in-circuit emulator (ICE) is usually the method we adopt to help debug our design when developing an application system. In the traditional processor design, there is no in-circuit emulation in mind. This complicates the design of in-circuit emulators and thus delays the whole development cycle. Besides, the traditional in-circuit emulation strategy is impra

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19

Lin, Chi-Ming, and 林啟明. "An 8-bits RISC Microprocessor Design for ISFET-based Hand-held pH-meter Signal Process Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/58157175721260121525.

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碩士<br>中原大學<br>電子工程研究所<br>94<br>The objective of this research is to design an eight-bit microcontroller, which is used in a portable array-type pH-meter with ISFET sensors. With this controller, we can improve reliability, stability and accuracy of the pH-meter system. There are a lot of reasons will make the output signals produce by the sensor array drift in different experiments, such as the read-out voltages sensed by each sensor in ISFET sensor array have different reference levels, the variation in temperature, the orders we examined, and the different response time of each sensor. There

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20

Lien, Tsai-Ju, and 練彩茹. "Design of Instruction Set and RTL Implementation of Decoder for an Embedded RISC Microprocessor with DSP Capability." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/39020726463455780041.

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碩士<br>國立交通大學<br>資訊工程系<br>89<br>Applications in telecommunication or multimedia require a new generation of fast and flexible microprocessors. A novel 32-bit hybrid RISC/DSP microprocessor is presented with RISC architecture and extended functionality for digital signal processing. This unifying of RISC and DSP was not designed by simply combining a general-purpose microprocessor and a DSP core, but a new concept for the implementation of DSP processors. With the architecture presented it has been proven that a DSP processor will achieve high performance under RISC philosophy with DSP capable i

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21

Dall, Christoffer. "The Design, Implementation, and Evaluation of Software and Architectural Support for ARM Virtualization." Thesis, 2018. https://doi.org/10.7916/D8HT4171.

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The ARM architecture is dominating in the mobile and embedded markets and is making an upwards push into the server and networking markets where virtualization is a key technology. Similar to x86, ARM has added hardware support for virtualization, but there are important differences between the ARM and x86 architectural designs. Given two widely deployed computer architectures with different approaches to hardware virtualization support, we can evaluate, in practice, benefits and drawbacks of different approaches to architectural support for virtualization. This dissertation explores n

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22

Apisake, Hongwitayakorn. "The study of trace cache memory on superscalar DLX processor." Thesis, 2003. http://hdl.handle.net/2440/120015.

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23

VIVET, Pascal. "Une méthodologie de conceptionde circuits intégrés quasi-insensibles aux délais :application à l'étude et à la réalisation d'un processeur RISC 16-bit asynchrone." Phd thesis, 2001. http://tel.archives-ouvertes.fr/tel-00002974.

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Les circuits asynchrones se caractérisent par l'absence d'horloge. Ils offrent des propriétés intéressantes pour l'intégration de systèmes dans les technologies submicroniques telles que robustesse, faible bruit, faible consommation, bonne modularité. Cependant, le manque de méthodes et outils de conception est un frein à leur développement. Les travaux présentés dans cette thèse portent sur la définition d'une méthodologie de conception de circuits intégrés asynchrones quasi-insensibles aux délais. Celle-ci permet d'une part la modélisation dans un langage de haut-niveau et la simulation dans

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24

Sun, Hongmei. "ARM processor modeling at a cycle accurate level in systemC." Thèse, 2003. http://hdl.handle.net/1866/14505.

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