Готові списки джерел за темами / VerilogHardware Description Language (HDL)

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Добірка наукової літератури з теми "VerilogHardware Description Language (HDL)"

Автор: Grafiati
Опубліковано: 3 червня 2025
Оновлено: 31 липня 2025

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Статті в журналах з теми "VerilogHardware Description Language (HDL)"

1

Vidya, Sagar Potharaju*. "FPGA IMPLEMENTATION OF ELLIPTIC CURVE DISCRETE LOGARITHMUSING VERILOG HDL." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 151–62. https://doi.org/10.5281/zenodo.1067986.

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Анотація:
Elliptic Curve Discrete Logarithm (ECDL) are most popular choice Elliptic Curve Cryptography (ECC),which gives provision for shorter key lengths as compared to as compared to its counterpart public key cryptosystems, and it can be used for security in embedded systems,wirless communications and personal communication systems. In this paper Elliptic Curve Discrete Logarithm code has been written in Verilog Hardware Description Language (HDL) and implemented on Xilinx Spartan3E Field Programmable Gate Array (FPGA),has taken 403 encoders, decoders with minimum period of 5.043 ns,maximum frequency
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2

Antigha, Richard E.E*. "APPLICATION OF AUTO REGRESSIVE INTEGRATED MOVING AVERAGE (ARIMA) IN URBAN STORMWATER DRAINAGE SYSTEMS MODELLING FOR THE CALABAR CATCHMENT, SOUTH-SOUTH, NIGERIA." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 11 (2017): 163–74. https://doi.org/10.5281/zenodo.1068882.

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Mathematical analyses were used to develop a stochastic model that predicts the influence of some hydraulic and hydrologic parameters on the perennial flooding of some parts of the Calabar Metropolis.  The model was developed based on rainfall data, cross sectional area of drains, artificial drainage density, degree imperviousness and the gradient (slope). Incorrect sizing and spread of drains as well as the existing slopes employed in the generation of the drains’ invert during construction have been seen as some of the key factors that foster flooding in the Metropolis. Malalignme
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3

Alves, Nélio Muniz Mendes, and Sérgio Schneider. "Implementation of an Embedded Hardware Description Language Using Haskell." JUCS - Journal of Universal Computer Science 9, no. (8) (2003): 795–812. https://doi.org/10.3217/jucs-009-08-0795.

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This paper describes an ongoing implementation of an embedded hardware description language (HDL) using Haskell as a host language. Traditionally, functional HDL s are made using lazy lists to model signals, so circuits are functions from lists of input values to lists of output values. We use another known approach for embedded languages, in which circuits are data structures rather than functions. This style of implementation permits one to inspect the structure of the circuit, allowing one to perform different interpretations for the same description. The approach we present can also be app
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4

Neelima, Koppala, and Subhas Chennapalli. "Low overhead optimal parity codes." TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 20, no. 3 (2022): 501–9. https://doi.org/10.12928/telkomnika.v20i3.23301.

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The error detecting and correcting codes are used in critical applications like in intensive care units, defense applications, and require highly reliable data. This brief focuses on codes to detect and correct adjacent errors within a single clock cycle by using modulo-2 addition of data bits for parity generation, syndrome calculation, error location identification and correction by improving code rate and minimizing bit overhead. The optimal parity codes devised can correct odd number of adjacent errors upto (N/2)-1 data bits when compared with the existing codes with less delay. Four optim
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5

Zhu, Yong. "Study on the Framework of ASIP Executable Specification." Applied Mechanics and Materials 263-266 (December 2012): 1768–72. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.1768.

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The research in accordance with the “description - synthesize” methodology to describe ASIP model is put forward. The executable specification described by the ADL drives the entire design process, and will be synthesized for HDL (Hardware Description Language) logic in EDA software framework to generate automatic design tools.
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6

BUTKO, Vladyslav, Kostiantyn KASIAN, and KASIAN. "COMPARISON OF COMPILERS FOR GENERATING A HARDWARE DESCRIPTION BASED ON AN IMPERATIVE PROGRAM: HDL CODER AND VITIS HLS." cientific papers of Donetsk National Technical University. Series: Informatics, Cybernetics and Computer Science 2, no. 39 (2024): 49–56. https://doi.org/10.31474/1996-1588-2024-2-39-49-56.

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Анотація:
A mathematical formula was chosen, the hardware implementation of which ensures sufficient the result accuracy of the compilers comparison. Based on it, a graph-scheme of the algorithm (GSA) was composed. According to GSA, programs were created in high-level languages (HLL): Matlab and C++. The HLL programs is not adapted to the generation of descriptions in the hardware description language (HDL) with HLS (high level synthesis) optimizations. To confirm the functional equivalence of the HLL programs, they were tested with the HLL test functions. Based on the Matlab and C++ programs, HDL was g
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7

Мірошник, Марина Анатоліївна, Юрій Васильович Пахомов, Кирило Юрійович Пшеничний та Андрій Вікторович Шафранський. "Асерційна верифікація моделей пристроїв реального часу з недетермінованими зовнішніми подіями". Інформаційно-керуючі системи на залізничному транспорті 29, № 1 (2024): 37–44. http://dx.doi.org/10.18664/ikszt.v29i1.300988.

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Анотація:
Запропоновано метод верифікації моделей пристроїв реального часу з обробкою зовнішніх подій із недермінованою тривалістю, що описані з використанням мов опису апаратури (Hardware Description Language, HDL). У методології використано апарат асерцій для опису темпоральної природи вищезазначених моделей.
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8

Ng, L. S., K. Y. Phan, and Patrick W. C. Ho. "Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)." Integration 96 (May 2024): 102140. http://dx.doi.org/10.1016/j.vlsi.2024.102140.

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9

K. Sagar Vivek, SK. Farooq Abdulla, S. Pavan, P. Manikanta, and G. Sudheer Kumar. "Development of Mechanized Hardware Description Language Signal Processing For Unmanned Aircraft System Applications." International Journal of Scientific Research in Science and Technology 12, no. 1 (2025): 388–94. https://doi.org/10.32628/ijsrst2512137.

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Future Department of Defense needs include rapid implementation and testing of signal processing algorithms on forward deployed unmanned autonomous hardware systems. Various signal processing algorithms can be designed to test the feasibility of using MATLAB with the hardware description language (HDL) Coder toolbox for rapid implementation and their use in signal processing hardware for real time aerospace and missile applications. This documents the signal processing algorithms and test inputs, MATLAB implementation, and performance and implementation results for generated very high-speed in
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10

Nhi Ho. T, To, Giao N. Pham, Quang Hung Nguyen, Binh A.Nguyen, Ngoc T. Le, and Hoanh Su Le. "Digital System Design for Traffic Light Controller System: A Systematic Approach." International Journal of Emerging Technology and Advanced Engineering 11, no. 11 (2021): 169–75. http://dx.doi.org/10.46338/ijetae1121_19.

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Анотація:
In this paper, we are going to present the finite state machine, how to implement it via hardware description language (HDL), and how to use it in a real application. At first, the specification and requirements of traffic light controller are stated. Then, the system architecture based on finite state machine (FSM) are conducted. Finally, the way of using HDL as well as the test-bench simulation are given in detail. Keywords : Digital system design, System on chip, Finite State Machine, Digital Design Education, Smart Classroom.
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Дисертації з теми "VerilogHardware Description Language (HDL)"

1

Blumenthal, Carl. "Development of the NoGAP CL Hardware Description Language and its Compiler." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8865.

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<p>The need for a more general hardware description language aimed specifically at processors, and vague notions and visions of how that language would be realized, lead to this thesis. The aim was to use the visions and initial ideas to evolve and formalize a language and begin implementing the tools to use it. The language, called NoGAP Common Language, is designed to give the programmer freedom to implement almost any processor design without being encumbered by many of the tedious tasks normally present in the creation process. While evolving the language it was chosen to borrow syntaxes
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2

Sparks, Matthew A. "A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE." UKnowledge, 2013. http://uknowledge.uky.edu/ece_etds/26.

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Анотація:
Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behav
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3

Guthrie, Thomas G. "Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Mar%5FGuthrie.pdf.

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4

Guimarães, Marcelo Alves. "Transporte TDM em redes GPON." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-07042011-152547/.

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Neste trabalho analisamos e propomos a utilização de TDM (Time Division Multiplexing) nativo canalizado/estruturado em redes PON (Passive Optical Network) com padrão GPON (Gigabit Passive Optical Network), com ênfase na estrutura de transmissão do legado das redes de telefonia. O objetivo principal é obter um aumento na eficiência de banda transmitida através da fragmentação de sinais E1 sem que seja necessário o uso de técnicas de emulação de circuito (que reduzem a eficiência de banda devido à adição de cabeçalhos). Inicialmente, é descrito o transporte TDM em redes GPON, como efetuado pelos
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5

Bäck, Carl. "Evaluation of high-level synthesis tools for generation of Verilog code from MATLAB based environments." Thesis, Luleå tekniska universitet, Institutionen för system- och rymdteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-78738.

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Анотація:
FPGAs are of interest in the signal processing domain as they provide the opportunity to run algorithms at very high speed. One possible use case is to sort incoming data in a measurement system, using e.g. a histogram method. Developing code for FPGA applications usually requires knowledge about special languages, which are not common knowledge in the signal processing domain. High-level synthesis is an approach where high-level languages, as MATLAB or C++, can be used together with a code generation tool, to directly generate an FPGA ready output. This thesis uses the development of a histog
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6

Lotlikar, Swapnil Subhash. "Design, Implementation and Evaluation of a Configurable NoC for AcENoCs FPGA Accelerated Emulation Platform." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8381.

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The heterogenous nature and the demand for extensive parallel processing in modern applications have resulted in widespread use of Multicore System-on-Chip (SoC) architectures. The emerging Network-on-Chip (NoC) architecture provides an energy-efficient and scalable communication solution for Multicore SoCs, serving as a powerful replacement for traditional bus-based solutions. The key to successful realization of such architectures is a flexible, fast and robust emulation platform for fast design space exploration. In this research, we present the design and evaluation of a highly configurabl
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Книги з теми "VerilogHardware Description Language (HDL)"

1

Patman̲āpan̲, Ṭi Ār. Design through Verilog HDL. John Wiley, 2004.

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2

Bhasker, Jayaram. A Verilog HDL primer. 2nd ed. Star Galaxy Pub., 1999.

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3

Padmanabhan, T. R. Design through Verilog HDL. Wiley, 2004.

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4

Stine, James E. Digital computer arithmetic datapath design using Verilog HDL. Kluwer Academic Publishers, 2004.

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5

Palnitkar, Samir. Verilog HDL: A guide to digital design and synthesis. Pearson Education Asia, 2001.

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6

Cavanagh, Joseph J. F. Digital design and Verilog HDL fundamentals. Taylor & Francis, 2008.

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7

International Verilog HDL Conference (5th 1996 Santa Clara, Calif.). 1996 IEEE International Verilog HDL Conference: February 26-28, 1996, Santa Clara, California. IEEE Computer Society Press, 1996.

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8

International, Verilog HDL Conference (5th 1996 Santa Clara Calif ). Proceedings, 1996 IEEE International Verilog HDL Conference: February 26-28, 1996, Santa Clara, California. IEEE Computer Society Press, 1996.

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9

International, Verilog HDL Conference (6th 1997 Santa Clara Calif ). 1997 IEEE International Verilog HDL Conference: Proceedings ; March 31-April 3, 1997, Santa Clara, California. IEEE Computer Society Press, 1997.

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10

International, Verilog HDL Conference (1st 1998 Santa Clara CA). International Verilog HDL Conference and VHDL International Users Forum: Proceedings, March 16-19, 1998, Santa Clara, CA. IEEE Conmputer Society, 1998.

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Частини книг з теми "VerilogHardware Description Language (HDL)"

1

Golze, Ulrich. "HDL Modeling with VERILOG." In VLSI Chip Design with the Hardware Description Language VERILOG. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/978-3-642-61001-1_11.

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2

"Chapter 9 Mixed-Language Description." In HDL with Digital Design. De Gruyter, 2015. http://dx.doi.org/10.1515/9781942270270-010.

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3

El Oualkadi, Ahmed. "S-? Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless Communications." In Advances in Wireless Technologies and Telecommunication. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch005.

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This chapter presents a systematic design of a S-? fractional-N Phase-Locked Loop based on hardware description language behavioral modeling. The proposed design consists of describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The description language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE standard, to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the overall system performances. The obtained results are compared w
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4

Manjunatha K. N., Raghu N., and Kiran B. "Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks." In Role of 6G Wireless Networks in AI and Blockchain-Based Applications. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-5376-6.ch006.

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This chapter explores model, design, and application-specific integrated circuit (ASIC) implementation to optimize turbo decoder using standard cell library of complementary metal oxide semiconductor (CMOS). Various constraints like channel noise, iteration, and frame length performance are analyzed and estimated through reference models. Register transfer language (RTL) model for encoder and decoder are simulated and synthesized by hardware description language (HDL). The ASIC implementation with various performance parameters like power and speed are considered to evaluate the proposed algor
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5

K. N., Manjunatha, Raghu N., and Kiran B. "Design of Efficient VLSI Architecture and Implementation of Power-Optimized Turbo Decoder for LTE Networks." In Handbook of Research on Emerging Designs and Applications for Microwave and Millimeter Wave Circuits. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-5955-3.ch015.

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Анотація:
This chapter is about model, design, and application specific integrated circuit (ASIC) implementation to optimize turbo decoder using standard cell library of complementary metal oxide semiconductor (CMOS). Various constraints like channel noise, number of iterations, and frame length performance are analyzed and estimated through reference models. Register transfer language (RTL) model for encoder and decoder is developed, simulated, and synthesized by hardware description language (HDL). The ASIC implementation with various performance parameters like power and speed are considered to evalu
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6

Wang, Zhen, and Jiang Yan. "Design of High-Speed Ethernet Data Loop Communication System Based on FPGA." In Advances in Transdisciplinary Engineering. IOS Press, 2025. https://doi.org/10.3233/atde250312.

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To address the dual requirements of network protocol processing and high-speed data transmission, this paper proposes a network protocol stack solution based on a reconfigurable hardware platform. The architecture integrates pipeline processing technology with an adaptive rate matching mechanism, implementing cross-protocol (ARP/UDP/IP/ICMP) collaborative processing and three-speed Ethernet (10/100/1000Mbps) adaptive switching capability on FPGA hardware-programmable platforms, providing high-performance communication infrastructure for industrial IoT and edge computing scenarios. At the hardw
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Jain, Dr Arpit. "CONCLUSION & FUTURESCOPE." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.7.

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The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu
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Jain, Dr Arpit. "Bibliography." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.8.

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Анотація:
The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu
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9

Jain, Dr Arpit. "Methodology and Implementation." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.5.

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Анотація:
The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu
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10

Jain, Dr Arpit. "INTRODUCTION." In Network on Chip (NoC) Implementation for 3-D Network Topological Structure in HDL Environment. Pink Petals Publication Pvt Ltd, 2023. http://dx.doi.org/10.70034/ppp/bk/noc.1.

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Анотація:
The solution for the multiprocessor system architecture is Application specific Network on Chip (NoC) architectures which are emerging as a leading technology. Modeling and simulation of multilevel network structure and synthesis for custom NoC can be beneficial in addressing several requirements such as bandwidth, inter process communication, multitasking application use, deadlock avoidance, router structures and port bandwidth. Network on chip (NoC) architecture is an approach to develop large and complex systems on a single chip. NoC is the network version of the MPSoC. A NoC can be structu
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Тези доповідей конференцій з теми "VerilogHardware Description Language (HDL)"

1

Lusardi, N., F. Garzetti, L. Gatti, and A. Geraci. "Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs." In 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC). IEEE, 2018. http://dx.doi.org/10.1109/nssmic.2018.8824537.

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2

Bogomolov, B. K., and N. A. Yurchenko. "ALU design using the VHDL language in the Aldec Active-HDL program." In Modern Problems of Telecommunications - 2024. Siberian State University of Telecommunications and Information Systems, 2024. http://dx.doi.org/10.55648/spt-2024-1-265.

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This work presents an implementation of an ALU description in the VHDL language in the Aldec Active-HDL program, ALU modeling was carried out, the results of the execution of arithmetic and logical functions executed by the ALU were obtained. This product can be used in most modern CAD systems. The device is ready for use to create a microprocessor based on it, and can also be manufactured as a separate chip.
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3

Chinedu, Okafor Kennedy, Ezekwe Chinwe Genevera, and Ogungbenro Oluwaseyi Akinyele. "Hardware description language (HDL): An efficient approach to device independent designs for VLSI market segments." In Technology (ICAST). IEEE, 2011. http://dx.doi.org/10.1109/icastech.2011.6145181.

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Yufera, Alberto, and Estefania Gallego. "Automatic Generation of Hardware Description Language (HDL) Models for 2D Bio-impedance Microelectrode Sensors Useful in Electrical Simulations." In 2010 First International Conference on Sensor Device Technologies and Applications (SENSORDEVICES). IEEE, 2010. http://dx.doi.org/10.1109/sensordevices.2010.26.

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Murdocca, Miles, Vipul Gupta, and Masoud Majidi. "A Hardware Compiler for Digital Optical Computing." In Optical Computing. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/optcomp.1991.tua2.

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Анотація:
A hardware compiler for translating descriptions of digital circuits from a hardware description language (HDL) into gate-level layouts is under development at Rutgers University. The layouts are customized for optical processors that make use of arrays of optical logic gates interconnected in free-space with regular interconnection patterns such as perfect shuffles, crossovers, or global interconnects. Specific processors that the hardware compiler supports include the S-SEED based all-optical processor developed at AT&amp;T Bell Labs, the S-SEED based all-optical processor under development
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