Academic literature on the topic '1-bit full adder'
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Journal articles on the topic "1-bit full adder"
SHUKLA, SOUMITRA, BAHNIMAN GHOSH, and MOHAMMAD WASEEM AKRAM. "1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM." SPIN 02, no. 02 (2012): 1250012. http://dx.doi.org/10.1142/s2010324712500129.
Full textN Md, Bilal, Bhaskara Rao K, and Mohan Das S. "Energy Efficient GDI Based Full Adders For Computing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 5–9. http://dx.doi.org/10.46647/ijetms.2020.v04i06.002.
Full textSingh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "PMOS based 1-Bit Full Adder Cell." International Journal of Computer Applications 42, no. 15 (2012): 8–18. http://dx.doi.org/10.5120/5766-7984.
Full textUpadhyay, Rahul Mani, R. K. Chauhan, and Manish Kumar. "Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 11, no. 4 (2023): 475–88. http://dx.doi.org/10.14201/adcaij.28558.
Full textRam, L. Adithya, V. Ajay Kumar, H. Karthik, and Sudhir Dakey. "Analysis of 1-bit Full Adders in Cadence 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 5836–44. http://dx.doi.org/10.22214/ijraset.2024.62995.
Full textMelnyk, Oleksandr, Maksym Kravets, and Valerii Kravets. "Four-bit Nanoadder Controlled by Five-Inputs Majority Elements." Electronics and Control Systems 4, no. 74 (2022): 67–72. http://dx.doi.org/10.18372/1990-5548.74.17310.
Full textEt.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.
Full textK Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.
Full textVinay, M. "Design and Implementation of 1-bit Full Subtractor Using FinFET." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 768–75. http://dx.doi.org/10.22214/ijraset.2024.63208.
Full textS, Haroon Rasheed, Mohan Das S, and Samba Sivudu Gaddam. "DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 15–18. http://dx.doi.org/10.46647/ijetms.2020.v04i06.004.
Full textBook chapters on the topic "1-bit full adder"
Mannepalli, Chaithanya, and Chaitanya Kommu. "Modified Low-Power Hybrid 1-Bit Full Adder." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_20.
Full textMowlika, Penumatsa Sushma Sri Naga, and Vemu Srinivasa Rao. "Energy-Efficient and High-Speed Hybrid 1-Bit Full Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7329-8_66.
Full textMalkhandi, Chinmay, and Rathnamala Rao. "A Full-Swing, High-Speed, and High-Impedance Hybrid 1-Bit Full Adder." In Proceedings of Second International Conference on Computational Electronics for Wireless Communications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_34.
Full textHussain, Inamul, and Saurabh Chaudhury. "Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits." In Advances in Communication, Devices and Networking. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7901-6_6.
Full textSayed, Mohammed, and Wael Badawy. "Novel 1-bit Full Adder Cells for Low-Power System-On-Chip Applications." In The Kluwer International Series in Engineering and Computer Science. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0351-4_29.
Full textSowmya, Pabba, D. Lakshmaiah, J. Manga, Gunturu Sai Shankar, and Desham Sai Prasad. "Design of Dayadi 1-bit CMOS Full Adder Based on Power Reduction Techniques." In Learning and Analytics in Intelligent Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-24318-0_11.
Full textNissi, Vesapaga Grace, and Satyajeet Sahoo. "Design of Energy-Efficient High-Speed 1-Bit Hybrid Full Adder for Fast Computation." In Innovations in Sustainable Technologies and Computing. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-8886-0_28.
Full textTomar, A., V. K. Sachan, J. Kandpal, N. Singh, P. Chauhan, and S. Bhandari. "Design of a 1-bit full adder in hybrid logic for high end computing in biomedical instrumentation." In Advances in AI for Biomedical Instrumentation, Electronics and Computing. CRC Press, 2024. http://dx.doi.org/10.1201/9781032644752-110.
Full textBhau, Parthiv, and Vijay Savani. "Efficient 1-Bit Hybrid Full Adder Design with Low Power Delay Product Using FinFET-TGDI Technology: Simulation and Comparative Study." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-97-5269-0_21.
Full textSalama, H., B. Saman, R. Gudlavalleti, et al. "Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs." In Selected Topics in Electronics and Systems. WORLD SCIENTIFIC, 2021. http://dx.doi.org/10.1142/9789811242823_0013.
Full textConference papers on the topic "1-bit full adder"
Premachand, D. R., and K. M. Srikantha. "Efficient 1-Bit Full Adder Implementation with Reduced MOSFET Count." In 2024 Second International Conference on Networks, Multimedia and Information Technology (NMITCON). IEEE, 2024. http://dx.doi.org/10.1109/nmitcon62075.2024.10699284.
Full textDevika, B., N. Dhathri, D. Priya Darshini, T. Sarayu, Satyajeet Sahoo, and Aswini K. Samantaray. "Performance Analysis of an Energy Efficient 1-Bit Hybrid Full Adder." In 2024 2nd International Conference on Networking, Embedded and Wireless Systems (ICNEWS). IEEE, 2024. http://dx.doi.org/10.1109/icnews60873.2024.10730821.
Full textRaghavaiah, Bonam, Sai Surya Mareedu, and J. Prasanth Kumar. "A Low-Power CLA Adder Using a 1-Bit Hybrid Full-Adder on the 45nm Technology." In 2024 2nd World Conference on Communication & Computing (WCONF). IEEE, 2024. http://dx.doi.org/10.1109/wconf61366.2024.10692053.
Full textDarji, Pallavi, Devansh Makwana, Minjal Pandya, Arpita Patel, Purvang Dalal, and Vinay Thumar. "Evaluation of Worst-Case Power-Delay Performance for a 1-Bit Full Adder." In 2025 IEEE 14th International Conference on Communication Systems and Network Technologies (CSNT). IEEE, 2025. https://doi.org/10.1109/csnt64827.2025.10967687.
Full textTabassum, Shaik Mohisena, M. Venkata Kavya Sri, D. Bhanu Navya Sri, Shaik Muskaan, Satyajeet Sahoo, and Aswini K. Samataray. "Design of Low Power and High Speed 1-bit Full Adder for DSP Applications." In 2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI). IEEE, 2024. http://dx.doi.org/10.1109/apci61480.2024.10616610.
Full textPathak, Yash, and Dharmendra Kumar Jhariya. "Minimizing Leakage Current & Ground Rail Fluctuations in 1-Bit 8t Full Adder Circuit Using Mtcmos Techniques." In 2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP). IEEE, 2024. http://dx.doi.org/10.1109/icecsp61809.2024.10698316.
Full textChauhan, Pallavi, Abhishek Tomar, and Neha Singh. "Design and Analysis of a 1-Bit Full Adder Utilizing a Novel Grounded Keeper XOR-XNOR Circuit." In 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. https://doi.org/10.1109/dicct64131.2025.10986359.
Full textSarker, MD Sakib Hasan, Fahad Siddique Faisal, Arif Istiaque, and Taieba Taher. "Design and Comparative Analysis of 1-BIT ALU and Full Adder using MGDI Technique for High-Performance PLC Applications." In 2024 27th International Conference on Computer and Information Technology (ICCIT). IEEE, 2024. https://doi.org/10.1109/iccit64611.2024.11022492.
Full textKhokha, Simran. "A Comprehensive Study on Low Power Novel 1-Bit CMOS Full Adders: Comparative Analysis and Performance Evaluation." In 2024 9th International Conference on Communication and Electronics Systems (ICCES). IEEE, 2024. https://doi.org/10.1109/icces63552.2024.10859972.
Full textBrodsky, Ira S., John V. Smolenski, and Miles R. Ford. "Tampa Electric Company Big Bend Station: System Design, Mat’L Selection and Construction of Units 1 and 2 Wet FGD System." In CORROSION 2000. NACE International, 2000. https://doi.org/10.5006/c2000-00584.
Full textReports on the topic "1-bit full adder"
for Social Science, Advisory Commitee. The impact of climate change on consumer food behaviours: Identification of potential trends and impacts. Food Standards Agency, 2022. http://dx.doi.org/10.46756/sci.fsa.icl350.
Full textAfrican Open Science Platform Part 1: Landscape Study. Academy of Science of South Africa (ASSAf), 2019. http://dx.doi.org/10.17159/assaf.2019/0047.
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