Academic literature on the topic '1-bit full adder'

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Journal articles on the topic "1-bit full adder"

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SHUKLA, SOUMITRA, BAHNIMAN GHOSH, and MOHAMMAD WASEEM AKRAM. "1-BIT FULL ADDER IMPLEMENTATION USING SINGLE SPIN LOGIC PARADIGM." SPIN 02, no. 02 (2012): 1250012. http://dx.doi.org/10.1142/s2010324712500129.

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This paper presents the implementation of important full adder circuits using quantum dots (QDs) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A fair comparison among these adders shows that the mirror adder implementation in SSL paradigm does not carry any advantage over the CMOS adder in terms of complexity and number of QDs, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, static and dynamic Manchester carry gate adders in SSL reduces the complexity and number of QDs, in harmony with the trend shown in transistor adders.
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N Md, Bilal, Bhaskara Rao K, and Mohan Das S. "Energy Efficient GDI Based Full Adders For Computing Applications." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 5–9. http://dx.doi.org/10.46647/ijetms.2020.v04i06.002.

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This This paper presents energy efficient GDI based 1-bit full adder cells with low power consumption and lesser delay with full swing modified basic logic gates to have reduced Power Delay Product (PDP). The various full adders are effectively realized by means of full swing OR, AND and XOR gates with the noteworthy enhancement in their performance. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technologies at a supply voltage of 1 Volts. The proposed 1-bit adder cells are compared with various basic adders based on speed, power consumption and energy (PDP). The proposed adder schemes with full swing basic cells achieve significant savings in terms of delay and energy consumption and which are more than 41% and 32% respectively in comparison to conventional “C-CMOS” 1-bit full adder and other existing adders.
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Singh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "PMOS based 1-Bit Full Adder Cell." International Journal of Computer Applications 42, no. 15 (2012): 8–18. http://dx.doi.org/10.5120/5766-7984.

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Upadhyay, Rahul Mani, R. K. Chauhan, and Manish Kumar. "Performance Evaluation of Efficient Low Power 1-bit Hybrid Full Adder." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 11, no. 4 (2023): 475–88. http://dx.doi.org/10.14201/adcaij.28558.

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The need for a low power system on a chip for embedded systems has increased enormously for human to machine interaction. The primary constraint of such embedded system is to consume less power and improve the battery performance of the device. We propose energy efficient, low power hybrid 1-bit full adder circuit in this paper, which may be integrated on chip to improve the overall performance of embedded systems. The proposed 1-bit hybrid full adder circuit designed at 130 nm technology was simulated using Mentor Graphics EDA tool. Further, a comparison is made with the previously proposed full adders, using metrics such as power dissipation, propagation delay and power delay product. Comparative performance shows that the proposed 1-bit full adder shows average improvement in terms of power dissipation (31.62 nW and 20.84 nW) and average delay (5.07ns and 11.41ns) over the existing 1-bit hybrid and cell 3 full adder circuit.
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Ram, L. Adithya, V. Ajay Kumar, H. Karthik, and Sudhir Dakey. "Analysis of 1-bit Full Adders in Cadence 45nm Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (2024): 5836–44. http://dx.doi.org/10.22214/ijraset.2024.62995.

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Abstract: A full adder is a digital circuit that performs the arithmetic operation of addition on three binary digits, producing a sum and a carry output. Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full adders are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.
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Melnyk, Oleksandr, Maksym Kravets, and Valerii Kravets. "Four-bit Nanoadder Controlled by Five-Inputs Majority Elements." Electronics and Control Systems 4, no. 74 (2022): 67–72. http://dx.doi.org/10.18372/1990-5548.74.17310.

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This paper presents a nano circuit of a full one-bit adder on the proposed five-input majority element. This innovative full adder design is used to development of a four-bit adder based on it. We offer a new single-bit full adder and a four-bit adder nano circuit in quantum-dot cellular automata technology. The proposed design four-bit adder utilizes only 231 quantum cells in a 0.49 µm2 area. It has a reduction in the number of cells, delay and energy dissipation at 1 K compared to the existing works. The QCADdesigner version 2.0.3 tool implements the developed quantum-dot cellular automata full adder and four-bit adder circuits. The implementation results show that the developed quantum-dot cellular automata full adder and four-bit adder circuits have an improvement over other quantum-dot cellular automata full adder circuits.
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Et.al, M. Naga Gowtham. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 3037–45. http://dx.doi.org/10.17762/turcomat.v12i3.1338.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.
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K Jeevitha, K Hari Kishore, E Raghuveera, Shaik Razia, M. Naga Gowtham, P. S. Hari Krishna Reddy,. "Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 5 (2021): 92–100. http://dx.doi.org/10.17762/turcomat.v12i5.734.

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In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.
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Vinay, M. "Design and Implementation of 1-bit Full Subtractor Using FinFET." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 768–75. http://dx.doi.org/10.22214/ijraset.2024.63208.

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Abstract: A full subtractor is a digital combinational circuit that performs subtraction involving three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out). Unlike a half adder, which adds only two binary digits and produces a sum and carry, a full adder considers an additional carry input from a previous less significant bit addition. The full adder's design includes three inputs: A, B, and Cin (carry-in), and two outputs: Sum (sum) and Cout (carry-out). The sum output Sum is derived by XOR-ing the three inputs, while the carry-out Cout is obtained by considering the majority function of the inputs. This means Cout is set when any two or more of the three inputs are high (logical 1). Full subtractors are fundamental components in the construction of arithmetic logic units (ALUs), binary adders, and other computational circuits in digital systems, enabling the handling of multi-bit binary addition by cascading multiple full adders.
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S, Haroon Rasheed, Mohan Das S, and Samba Sivudu Gaddam. "DESIGN OF ENERGY EFFICIENT HYBRID 1-BIT FULL ADDER FOR ARITHMETIC APPLICATIONS." International Journal of Engineering Technology and Management Sciences 4, no. 6 (2020): 15–18. http://dx.doi.org/10.46647/ijetms.2020.v04i06.004.

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This paper presents an energy efficient 1-bit full adder designed with a low voltage and high performance internal logic cells which leads to have abridged Power Delay Product (PDP). The customized XNOR and XOR gates, a necessary entity, are also presented. The simulations for the designed circuits performed in cadence virtuoso tool with 45-nm CMOS technology at a supply voltage of 0.9 Volts. The proposed 1-bit adder cell is compared with various trendy adders based on speed, power consumption and energy (PDP). The proposed adder schemes with modified internal entity cells achieve significant savings in terms of delay and energy consumption and which are more than 77% and 40.47% respectively when compared with conventional “C-CMOS” 1-bit full adder and other counter parts.
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Book chapters on the topic "1-bit full adder"

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Mannepalli, Chaithanya, and Chaitanya Kommu. "Modified Low-Power Hybrid 1-Bit Full Adder." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_20.

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Mowlika, Penumatsa Sushma Sri Naga, and Vemu Srinivasa Rao. "Energy-Efficient and High-Speed Hybrid 1-Bit Full Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7329-8_66.

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Malkhandi, Chinmay, and Rathnamala Rao. "A Full-Swing, High-Speed, and High-Impedance Hybrid 1-Bit Full Adder." In Proceedings of Second International Conference on Computational Electronics for Wireless Communications. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-6661-3_34.

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Hussain, Inamul, and Saurabh Chaudhury. "Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits." In Advances in Communication, Devices and Networking. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7901-6_6.

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Sayed, Mohammed, and Wael Badawy. "Novel 1-bit Full Adder Cells for Low-Power System-On-Chip Applications." In The Kluwer International Series in Engineering and Computer Science. Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0351-4_29.

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Sowmya, Pabba, D. Lakshmaiah, J. Manga, Gunturu Sai Shankar, and Desham Sai Prasad. "Design of Dayadi 1-bit CMOS Full Adder Based on Power Reduction Techniques." In Learning and Analytics in Intelligent Systems. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-24318-0_11.

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Nissi, Vesapaga Grace, and Satyajeet Sahoo. "Design of Energy-Efficient High-Speed 1-Bit Hybrid Full Adder for Fast Computation." In Innovations in Sustainable Technologies and Computing. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-99-8886-0_28.

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Tomar, A., V. K. Sachan, J. Kandpal, N. Singh, P. Chauhan, and S. Bhandari. "Design of a 1-bit full adder in hybrid logic for high end computing in biomedical instrumentation." In Advances in AI for Biomedical Instrumentation, Electronics and Computing. CRC Press, 2024. http://dx.doi.org/10.1201/9781032644752-110.

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Bhau, Parthiv, and Vijay Savani. "Efficient 1-Bit Hybrid Full Adder Design with Low Power Delay Product Using FinFET-TGDI Technology: Simulation and Comparative Study." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2024. http://dx.doi.org/10.1007/978-981-97-5269-0_21.

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Salama, H., B. Saman, R. Gudlavalleti, et al. "Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs." In Selected Topics in Electronics and Systems. WORLD SCIENTIFIC, 2021. http://dx.doi.org/10.1142/9789811242823_0013.

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Conference papers on the topic "1-bit full adder"

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Premachand, D. R., and K. M. Srikantha. "Efficient 1-Bit Full Adder Implementation with Reduced MOSFET Count." In 2024 Second International Conference on Networks, Multimedia and Information Technology (NMITCON). IEEE, 2024. http://dx.doi.org/10.1109/nmitcon62075.2024.10699284.

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Devika, B., N. Dhathri, D. Priya Darshini, T. Sarayu, Satyajeet Sahoo, and Aswini K. Samantaray. "Performance Analysis of an Energy Efficient 1-Bit Hybrid Full Adder." In 2024 2nd International Conference on Networking, Embedded and Wireless Systems (ICNEWS). IEEE, 2024. http://dx.doi.org/10.1109/icnews60873.2024.10730821.

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Raghavaiah, Bonam, Sai Surya Mareedu, and J. Prasanth Kumar. "A Low-Power CLA Adder Using a 1-Bit Hybrid Full-Adder on the 45nm Technology." In 2024 2nd World Conference on Communication & Computing (WCONF). IEEE, 2024. http://dx.doi.org/10.1109/wconf61366.2024.10692053.

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Darji, Pallavi, Devansh Makwana, Minjal Pandya, Arpita Patel, Purvang Dalal, and Vinay Thumar. "Evaluation of Worst-Case Power-Delay Performance for a 1-Bit Full Adder." In 2025 IEEE 14th International Conference on Communication Systems and Network Technologies (CSNT). IEEE, 2025. https://doi.org/10.1109/csnt64827.2025.10967687.

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Tabassum, Shaik Mohisena, M. Venkata Kavya Sri, D. Bhanu Navya Sri, Shaik Muskaan, Satyajeet Sahoo, and Aswini K. Samataray. "Design of Low Power and High Speed 1-bit Full Adder for DSP Applications." In 2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI). IEEE, 2024. http://dx.doi.org/10.1109/apci61480.2024.10616610.

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Pathak, Yash, and Dharmendra Kumar Jhariya. "Minimizing Leakage Current & Ground Rail Fluctuations in 1-Bit 8t Full Adder Circuit Using Mtcmos Techniques." In 2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP). IEEE, 2024. http://dx.doi.org/10.1109/icecsp61809.2024.10698316.

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Chauhan, Pallavi, Abhishek Tomar, and Neha Singh. "Design and Analysis of a 1-Bit Full Adder Utilizing a Novel Grounded Keeper XOR-XNOR Circuit." In 2025 3rd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT). IEEE, 2025. https://doi.org/10.1109/dicct64131.2025.10986359.

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Sarker, MD Sakib Hasan, Fahad Siddique Faisal, Arif Istiaque, and Taieba Taher. "Design and Comparative Analysis of 1-BIT ALU and Full Adder using MGDI Technique for High-Performance PLC Applications." In 2024 27th International Conference on Computer and Information Technology (ICCIT). IEEE, 2024. https://doi.org/10.1109/iccit64611.2024.11022492.

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Khokha, Simran. "A Comprehensive Study on Low Power Novel 1-Bit CMOS Full Adders: Comparative Analysis and Performance Evaluation." In 2024 9th International Conference on Communication and Electronics Systems (ICCES). IEEE, 2024. https://doi.org/10.1109/icces63552.2024.10859972.

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Brodsky, Ira S., John V. Smolenski, and Miles R. Ford. "Tampa Electric Company Big Bend Station: System Design, Mat’L Selection and Construction of Units 1 and 2 Wet FGD System." In CORROSION 2000. NACE International, 2000. https://doi.org/10.5006/c2000-00584.

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Abstract Tampa Electric Company (TEC) Big Bend Station is located in Apollo Beach, Florida and consists of four (4) coal-fired boilers with a total generating capacity of 1,840 MW. A limestone based forced oxidation flue gas desulfurization (FGD) system began operation in March 1985 to control sulfur dioxide emissions from Unit 4. Flue gas from Unit 3 was added to the existing FGD system for sulfur dioxide removal in 1996. To meet 1990 Clean Air Act Amendments Phase 11 requirements, TEC is required to reduce sulfur dioxide emissions from Units 1 & 2. To achieve compliance and broaden the range of fuel types and sources, TEC has elected to retrofit a new flue gas desulfurization system for the combined flue gas generated by Units 1 & 2. The FGD system will consist of a single absorber module designed to operate at a high velocity and achieve 95% sulfur dioxide removal. The absorber will utilize a Dual Flow Tray and dibasic acid (DBA) to enhance flue gas absorption capacity, while producing commercial grade gypsum. The new FGD system includes booster fans, ductwork to interface with the existing electrostatic precipitators, and a new chimney. The existing reagent preparation system was expanded to provide reagent slurry for the new system (Units 1 & 2). The dewatering equipment, consisting of primary dewatering hydroclones and rotary drum vacuum filters, was also upgraded to serve both station FGD systems. A new wastewater treatment system, sized to handle the combined blowdown from both FGD systems, is also supplied. The single absorber vessel for scrubbing the gases of Units 1&2 necessitated the selection of corrosion resistant materials that would allow for high on-line availability of the FGD system. The chloride concentration level of up to 30,000 ppm in the recycle tank during normal operation, eliminated many of the medium grade stainless steels from consideration for the scrubber/outlet duct. This paper will review the overall system and absorber designs. The materials of construction that were selected along with those that were considered will be discussed. Construction methods with specific attention to welding considerations will also be reviewed.
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Reports on the topic "1-bit full adder"

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for Social Science, Advisory Commitee. The impact of climate change on consumer food behaviours: Identification of potential trends and impacts. Food Standards Agency, 2022. http://dx.doi.org/10.46756/sci.fsa.icl350.

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The Advisory Committee on Social Sciences (ACSS) was established by the Food Standards Agency (FSA) to bring social science expertise to the Agency’s pursuit of food safety, food authenticity, and regulatory excellence. In fulfilling its remit, the Agency needs advice from a wide range of expertise, and this includes insights from disciplines such as behavioural science and economics as much as from the medical, agricultural, and animal health domains. It is crucial to understand how we as consumers, as well as the industries that feed us, might adapt our behaviours, perceive risks or alter our purchasing patterns. Climate Change is now widely accepted as one of the gravest risks facing human well-being, not least because of its possible effects on the food system. These effects could be radical and sudden and are inherently unpredictable. At the same time, humans are extraordinarily adaptable and innovative, and so responses to this threat are also unpredictable. Many people are already ‘doing their bit’ towards the ‘Net Zero’ aspiration by adapting their diet, changing their consumption patterns, or striving to avoid waste. As one of the many governmental bodies concerned with food supply the FSA has a strong interest in horizon scanning likely responses to climate change and understanding where it might impact its work. The ACSS therefore offered to help with this large task and formed a Working Group on Climate Change and Consumer Behaviours (CCCB). We were fortunate to be able to begin our work by hosting a workshop with experts in the field to illuminate the trends already being observed, or considered possible. Following this we then convened a group of colleagues across the FSA to deepen understanding of how the identified trends might impact on food safety, food authenticity and regulation. We took as our initial scope end consumers (rather than the businesses that serve them), and we looked for behaviours that appear to be ones that consumers have adopted to respond to the Net Zero call. The concepts of ‘choice’ and ‘preference’ in relation to behaviour is complex, as much behaviour does not follow choice or preference. In future, climate change may bring about changes to food availability and price that mean that choices are constrained. Equally, consumer preferences may feed back into the supply chain, and lead to a degree of choice ‘editing’ by food businesses. These complexities are beyond our scope for the moment, but, as experts participating in our workshop emphasized, must be considered. To get the full value of the expertise we were able to assemble, and the added value from our consultants, Ipsos UK who constructed and ran the first workshop, it is important to read the full report. It is also important to go directly to the centres of expertise for the insights that surfaced, but that we could only dip into and summarise. In this overview, the CCCB working group wants to highlight what we felt were some of the most interesting lines of enquiry, which are shown in table 1 below. We have to stress that these are possible trends of concern to the FSA, not necessarily with already observable effects, and more work needs to be done to explore them. We are conscious that the Science Council also has a WG on Net Zero, with a wider scope than that of the ACSS, and we are closely in touch to ensure that the work is complementary. I would therefore like to commend the work of the ACSS CCCB working group to the FSA, and we look forward to discussing how we can be of further help. I would also like to wholeheartedly thank everyone involved in making the workshops such stimulating and insightful exercises.
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African Open Science Platform Part 1: Landscape Study. Academy of Science of South Africa (ASSAf), 2019. http://dx.doi.org/10.17159/assaf.2019/0047.

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This report maps the African landscape of Open Science – with a focus on Open Data as a sub-set of Open Science. Data to inform the landscape study were collected through a variety of methods, including surveys, desk research, engagement with a community of practice, networking with stakeholders, participation in conferences, case study presentations, and workshops hosted. Although the majority of African countries (35 of 54) demonstrates commitment to science through its investment in research and development (R&D), academies of science, ministries of science and technology, policies, recognition of research, and participation in the Science Granting Councils Initiative (SGCI), the following countries demonstrate the highest commitment and political willingness to invest in science: Botswana, Ethiopia, Kenya, Senegal, South Africa, Tanzania, and Uganda. In addition to existing policies in Science, Technology and Innovation (STI), the following countries have made progress towards Open Data policies: Botswana, Kenya, Madagascar, Mauritius, South Africa and Uganda. Only two African countries (Kenya and South Africa) at this stage contribute 0.8% of its GDP (Gross Domestic Product) to R&D (Research and Development), which is the closest to the AU’s (African Union’s) suggested 1%. Countries such as Lesotho and Madagascar ranked as 0%, while the R&D expenditure for 24 African countries is unknown. In addition to this, science globally has become fully dependent on stable ICT (Information and Communication Technologies) infrastructure, which includes connectivity/bandwidth, high performance computing facilities and data services. This is especially applicable since countries globally are finding themselves in the midst of the 4th Industrial Revolution (4IR), which is not only “about” data, but which “is” data. According to an article1 by Alan Marcus (2015) (Senior Director, Head of Information Technology and Telecommunications Industries, World Economic Forum), “At its core, data represents a post-industrial opportunity. Its uses have unprecedented complexity, velocity and global reach. As digital communications become ubiquitous, data will rule in a world where nearly everyone and everything is connected in real time. That will require a highly reliable, secure and available infrastructure at its core, and innovation at the edge.” Every industry is affected as part of this revolution – also science. An important component of the digital transformation is “trust” – people must be able to trust that governments and all other industries (including the science sector), adequately handle and protect their data. This requires accountability on a global level, and digital industries must embrace the change and go for a higher standard of protection. “This will reassure consumers and citizens, benefitting the whole digital economy”, says Marcus. A stable and secure information and communication technologies (ICT) infrastructure – currently provided by the National Research and Education Networks (NRENs) – is key to advance collaboration in science. The AfricaConnect2 project (AfricaConnect (2012–2014) and AfricaConnect2 (2016–2018)) through establishing connectivity between National Research and Education Networks (NRENs), is planning to roll out AfricaConnect3 by the end of 2019. The concern however is that selected African governments (with the exception of a few countries such as South Africa, Mozambique, Ethiopia and others) have low awareness of the impact the Internet has today on all societal levels, how much ICT (and the 4th Industrial Revolution) have affected research, and the added value an NREN can bring to higher education and research in addressing the respective needs, which is far more complex than simply providing connectivity. Apart from more commitment and investment in R&D, African governments – to become and remain part of the 4th Industrial Revolution – have no option other than to acknowledge and commit to the role NRENs play in advancing science towards addressing the SDG (Sustainable Development Goals). For successful collaboration and direction, it is fundamental that policies within one country are aligned with one another. Alignment on continental level is crucial for the future Pan-African African Open Science Platform to be successful. Both the HIPSSA ((Harmonization of ICT Policies in Sub-Saharan Africa)3 project and WATRA (the West Africa Telecommunications Regulators Assembly)4, have made progress towards the regulation of the telecom sector, and in particular of bottlenecks which curb the development of competition among ISPs. A study under HIPSSA identified potential bottlenecks in access at an affordable price to the international capacity of submarine cables and suggested means and tools used by regulators to remedy them. Work on the recommended measures and making them operational continues in collaboration with WATRA. In addition to sufficient bandwidth and connectivity, high-performance computing facilities and services in support of data sharing are also required. The South African National Integrated Cyberinfrastructure System5 (NICIS) has made great progress in planning and setting up a cyberinfrastructure ecosystem in support of collaborative science and data sharing. The regional Southern African Development Community6 (SADC) Cyber-infrastructure Framework provides a valuable roadmap towards high-speed Internet, developing human capacity and skills in ICT technologies, high- performance computing and more. The following countries have been identified as having high-performance computing facilities, some as a result of the Square Kilometre Array7 (SKA) partnership: Botswana, Ghana, Kenya, Madagascar, Mozambique, Mauritius, Namibia, South Africa, Tunisia, and Zambia. More and more NRENs – especially the Level 6 NRENs 8 (Algeria, Egypt, Kenya, South Africa, and recently Zambia) – are exploring offering additional services; also in support of data sharing and transfer. The following NRENs already allow for running data-intensive applications and sharing of high-end computing assets, bio-modelling and computation on high-performance/ supercomputers: KENET (Kenya), TENET (South Africa), RENU (Uganda), ZAMREN (Zambia), EUN (Egypt) and ARN (Algeria). Fifteen higher education training institutions from eight African countries (Botswana, Benin, Kenya, Nigeria, Rwanda, South Africa, Sudan, and Tanzania) have been identified as offering formal courses on data science. In addition to formal degrees, a number of international short courses have been developed and free international online courses are also available as an option to build capacity and integrate as part of curricula. The small number of higher education or research intensive institutions offering data science is however insufficient, and there is a desperate need for more training in data science. The CODATA-RDA Schools of Research Data Science aim at addressing the continental need for foundational data skills across all disciplines, along with training conducted by The Carpentries 9 programme (specifically Data Carpentry 10 ). Thus far, CODATA-RDA schools in collaboration with AOSP, integrating content from Data Carpentry, were presented in Rwanda (in 2018), and during17-29 June 2019, in Ethiopia. Awareness regarding Open Science (including Open Data) is evident through the 12 Open Science-related Open Access/Open Data/Open Science declarations and agreements endorsed or signed by African governments; 200 Open Access journals from Africa registered on the Directory of Open Access Journals (DOAJ); 174 Open Access institutional research repositories registered on openDOAR (Directory of Open Access Repositories); 33 Open Access/Open Science policies registered on ROARMAP (Registry of Open Access Repository Mandates and Policies); 24 data repositories registered with the Registry of Data Repositories (re3data.org) (although the pilot project identified 66 research data repositories); and one data repository assigned the CoreTrustSeal. Although this is a start, far more needs to be done to align African data curation and research practices with global standards. Funding to conduct research remains a challenge. African researchers mostly fund their own research, and there are little incentives for them to make their research and accompanying data sets openly accessible. Funding and peer recognition, along with an enabling research environment conducive for research, are regarded as major incentives. The landscape report concludes with a number of concerns towards sharing research data openly, as well as challenges in terms of Open Data policy, ICT infrastructure supportive of data sharing, capacity building, lack of skills, and the need for incentives. Although great progress has been made in terms of Open Science and Open Data practices, more awareness needs to be created and further advocacy efforts are required for buy-in from African governments. A federated African Open Science Platform (AOSP) will not only encourage more collaboration among researchers in addressing the SDGs, but it will also benefit the many stakeholders identified as part of the pilot phase. The time is now, for governments in Africa, to acknowledge the important role of science in general, but specifically Open Science and Open Data, through developing and aligning the relevant policies, investing in an ICT infrastructure conducive for data sharing through committing funding to making NRENs financially sustainable, incentivising open research practices by scientists, and creating opportunities for more scientists and stakeholders across all disciplines to be trained in data management.
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